| commit | cbd2ff78c0c102dec2a029258fa16e11dc4ea3ed | [log] [tgz] |
|---|---|---|
| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | Fri Jan 20 00:29:59 2017 +0000 |
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | Fri Jan 20 00:29:59 2017 +0000 |
| tree | 739e9273a972898f948edfd451e3969bb12b777e | |
| parent | c5cf6c8ad5c7147ccd28e13a5855fa20ae78c2fb [diff] |
[MIRParser] Allow generic register specification on operand. This completes r292321 by adding support for generic registers, e.g.: %2:_(s32) = G_ADD %0, %1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292550 91177308-0d34-0410-b5e6-96231b3b80d8