| commit | 7a175729942d0d92d50149b3963133716d743a61 | [log] [tgz] |
|---|---|---|
| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | Thu Oct 11 10:39:03 2018 +0000 |
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | Thu Oct 11 10:39:03 2018 +0000 |
| tree | 5b0ab2cf7f4ee8cde706e4c6f3bbf5cbae284b60 | |
| parent | e13d09452159012b82271b7e655a02e16da76887 [diff] |
[tblgen][CodeGenSchedule] Add a check for invalid RegisterFile definitions with zero physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344235 91177308-0d34-0410-b5e6-96231b3b80d8