| commit | 055d3aae75c38b7aae3a44e0f550f6c90dcca555 | [log] [tgz] |
|---|---|---|
| author | Alex Bradbury <asb@lowrisc.org> | Fri Jun 08 10:39:05 2018 +0000 |
| committer | Alex Bradbury <asb@lowrisc.org> | Fri Jun 08 10:39:05 2018 +0000 |
| tree | f8d01542c1990bbeaacc5fb8a3ee99c21b44ab38 | |
| parent | 696a18d3c4f5075674e351b1c56db7393dd89da3 [diff] |
[RISCV] Implement MC layer support for the fence.tso instruction The instruction makes use of a previously ignored field in the fence instruction. It is introduced in the version 2.3 draft of the RISC-V specification after much work by the Memory Model Task Group. As clarified here <https://github.com/riscv/riscv-isa-manual/issues/186>, the fence.tso assembler mnemonic does not have operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334278 91177308-0d34-0410-b5e6-96231b3b80d8