| commit | 93f5fcdff38719edd5f97f9e33801bc760e24b25 | [log] [tgz] |
|---|---|---|
| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | Tue Jan 09 15:39:44 2018 +0000 |
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | Tue Jan 09 15:39:44 2018 +0000 |
| tree | 00222c48f0b15cba265258162070ad57ee70044e | |
| parent | b56f822bc764e0a64542ef67052534cf7caa06b9 [diff] |
[CodeGen] Don't print register classes in -debug output Since register classes and banks are already printed with the register definition, don't print it at the end of every instruction anymore. This follows MIR in this regard and is another step to the unification of the two formats. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322086 91177308-0d34-0410-b5e6-96231b3b80d8