| commit | 8e4eaabdb82c99ffe72b2a4ed5322f3a22944606 | [log] [tgz] |
|---|---|---|
| author | Matthias Braun <matze@braunis.de> | Tue Mar 31 19:57:53 2015 +0000 |
| committer | Matthias Braun <matze@braunis.de> | Tue Mar 31 19:57:53 2015 +0000 |
| tree | d34cb059df625d58515d547e530cc4d564857884 | |
| parent | 3f1ec42ec73d61eceddfca6071695431b50b78ed [diff] |
RegAllocGreedy: Allow target to specify register class ordering. Specify an allocation order with a register class. This is used by register allocators with a greedy heuristic. This is usefull as it is sometimes beneficial to color more constrained classes first. Differential Revision: http://reviews.llvm.org/D8626 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233743 91177308-0d34-0410-b5e6-96231b3b80d8