| commit | 9b313de7bb5db6052ef36f58baca48027ff5703a | [log] [tgz] |
|---|---|---|
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | Mon Aug 27 17:40:09 2018 +0000 |
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | Mon Aug 27 17:40:09 2018 +0000 |
| tree | 443d6b2d64834bb67a9d4a0d1dc5280a983f26f5 | |
| parent | e07ed9ed4f59d83b77de1ef470fca443f4e309e2 [diff] |
MachineVerifier: Fix assert on implicit virtreg use If the liveness of a physical register was invalid, this was attempting to iterate the subregisters of all register uses of the instruction, which would assert when it encountered an implicit virtual register operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340763 91177308-0d34-0410-b5e6-96231b3b80d8