| commit | 4e92383b67daf6e7f5770c35ab478b4f9611aacd | [log] [tgz] |
|---|---|---|
| author | Juergen Ributzka <juergen@apple.com> | Fri Aug 29 23:48:09 2014 +0000 |
| committer | Juergen Ributzka <juergen@apple.com> | Fri Aug 29 23:48:09 2014 +0000 |
| tree | f53706bf99b8548040a7396a770256d176165432 | |
| parent | e7f301e079ee4b86f0a54b1108222ee3b6938ca1 [diff] |
[MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR. Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216805 91177308-0d34-0410-b5e6-96231b3b80d8