b5e23d13a519d14a7cd6acb481c06bde362b5126 - platform_external_llvm80

commit	b5e23d13a519d14a7cd6acb481c06bde362b5126	[log] [tgz]
author	Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net>	Sun Apr 15 17:32:17 2018 +0000
committer	Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net>	Sun Apr 15 17:32:17 2018 +0000
tree	34cd8d79185f1598b44d03ca189d6a02ce56f0ba
parent	8a7e3a43d6217a3e5803c2af6776af6ba671aa03 [diff]

[MC] Moved all the remaining logic that computed instruction latency and reciprocal throughput from TargetSchedModel to MCSchedModel.

TargetSchedModel now always delegates to MCSchedModel the computation of
instruction latency and reciprocal throughput.
No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330099 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/TargetSchedule.h[diff]
include/llvm/MC/MCSchedule.h[diff]
lib/CodeGen/TargetSchedule.cpp[diff]
lib/CodeGen/TargetSubtargetInfo.cpp[diff]
lib/MC/MCSchedule.cpp[diff]

5 files changed

tree: 34cd8d79185f1598b44d03ca189d6a02ce56f0ba