b86a0cdb674549d8493043331cecd9cbf53b80da - platform_external_llvm80

commit	b86a0cdb674549d8493043331cecd9cbf53b80da	[log] [tgz]
author	Andrew Trick <atrick@apple.com>	Sat Jun 15 04:49:57 2013 +0000
committer	Andrew Trick <atrick@apple.com>	Sat Jun 15 04:49:57 2013 +0000
tree	8690d4a95ff7cf02b6f840632086b62aa1ed17fc
parent	bacb24975d7a8a6ccff0e16057a581b3831c4c7d [diff]

Machine Model: Add MicroOpBufferSize and resource BufferSize.

Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/ScheduleDAG.h[diff]
include/llvm/CodeGen/ScheduleDAGInstrs.h[diff]
include/llvm/CodeGen/TargetSchedule.h[diff]
include/llvm/MC/MCInstrItineraries.h[diff]
include/llvm/MC/MCSchedule.h[diff]
include/llvm/Target/TargetInstrInfo.h[diff]
include/llvm/Target/TargetSchedule.td[diff]
lib/CodeGen/MachineScheduler.cpp[diff]
lib/CodeGen/MachineTraceMetrics.cpp[diff]
lib/CodeGen/ScheduleDAGInstrs.cpp[diff]
lib/CodeGen/TargetInstrInfo.cpp[diff]
lib/CodeGen/TargetSchedule.cpp[diff]
lib/Target/ARM/ARMBaseInstrInfo.cpp[diff]
lib/Target/ARM/ARMScheduleA9.td[diff]
lib/Target/Hexagon/HexagonMachineScheduler.cpp[diff]
lib/Target/X86/X86SchedHaswell.td[diff]
lib/Target/X86/X86SchedSandyBridge.td[diff]
lib/Target/X86/X86Schedule.td[diff]
lib/Target/X86/X86ScheduleAtom.td[diff]
test/CodeGen/X86/misched-balance.ll[diff]
test/CodeGen/X86/misched-matmul.ll[diff]
test/CodeGen/X86/misched-matrix.ll[diff]
utils/TableGen/SubtargetEmitter.cpp[diff]

23 files changed

tree: 8690d4a95ff7cf02b6f840632086b62aa1ed17fc