| commit | 00cc11273bf644157d5e78e5dac4c67a63918fef | [log] [tgz] |
|---|---|---|
| author | Arnold Schwaighofer <aschwaighofer@apple.com> | Thu Jun 15 17:34:42 2017 +0000 |
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | Thu Jun 15 17:34:42 2017 +0000 |
| tree | 08745c617541b52a6dda6f875d092de1e883f252 | |
| parent | c9069cd453440161a86ff5af7be1f12a3869baff [diff] |
ISel: Fix FastISel of swifterror values The code assumed that we process instructions in basic block order. FastISel processes instructions in reverse basic block order. We need to pre-assign virtual registers before selecting otherwise we get def-use relationships wrong. This only affects code with swifterror registers. rdar://32659327 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305484 91177308-0d34-0410-b5e6-96231b3b80d8