| commit | 37e5cfa4aae0dd693ab0c35ff78d37f5ddfe177d | [log] [tgz] |
|---|---|---|
| author | Stepan Dyatkovskiy <stpworld@narod.ru> | Thu Apr 03 11:29:15 2014 +0000 |
| committer | Stepan Dyatkovskiy <stpworld@narod.ru> | Thu Apr 03 11:29:15 2014 +0000 |
| tree | b8f393497bcc07da41faf2778697ccc041520ac8 | |
| parent | 3f11cd0d25971e2f8231a74a27339146d786644d [diff] |
PR19320: The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8