19636dfbd89808093c6ac736abb242e035fb99b4 - platform_external_llvm80

commit	19636dfbd89808093c6ac736abb242e035fb99b4	[log] [tgz]
author	Craig Topper <craig.topper@intel.com>	Thu Apr 05 05:19:36 2018 +0000
committer	Craig Topper <craig.topper@intel.com>	Thu Apr 05 05:19:36 2018 +0000
tree	d7718a78f7b63e10c4d0e3a96602e4a2016ceb57
parent	67c388f5a13b8d813d27bb2cbedb0e3da7fddc82 [diff]

[X86] Revert r329251-329254

It's failing on the bots and I'm not sure why.

This reverts:

[X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents.
[X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128 which uses WriteShuffle256.
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
[X86] Auto-generate complete checks. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329256 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrAVX512.td[diff]
lib/Target/X86/X86InstrSSE.td[diff]
lib/Target/X86/X86SchedBroadwell.td[diff]
lib/Target/X86/X86SchedHaswell.td[diff]
lib/Target/X86/X86SchedSandyBridge.td[diff]
lib/Target/X86/X86SchedSkylakeClient.td[diff]
lib/Target/X86/X86SchedSkylakeServer.td[diff]
test/CodeGen/X86/avx-schedule.ll[diff]
test/CodeGen/X86/avx512-schedule.ll[diff]
test/CodeGen/X86/avx512-shuffle-schedule.ll[diff]
test/CodeGen/X86/extractelement-legalization-store-ordering.ll[diff]
test/CodeGen/X86/fp128-i128.ll[diff]
test/CodeGen/X86/memcpy-2.ll[diff]
test/CodeGen/X86/misched-matrix.ll[diff]
test/CodeGen/X86/mmx-schedule.ll[diff]
test/CodeGen/X86/pr31045.ll[diff]
test/CodeGen/X86/pr34080.ll[diff]
test/CodeGen/X86/schedule-x86-64-shld.ll[diff]
test/CodeGen/X86/schedule-x86_64.ll[diff]
test/CodeGen/X86/sse-schedule.ll[diff]
test/CodeGen/X86/sse2-schedule.ll[diff]

21 files changed

tree: d7718a78f7b63e10c4d0e3a96602e4a2016ceb57