| commit | bcd8c96d2e0d7a69816f5d04f21da9732ca7e3b1 | [log] [tgz] |
|---|---|---|
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | Fri Feb 10 02:07:58 2017 +0000 |
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | Fri Feb 10 02:07:58 2017 +0000 |
| tree | d0c164fd3c435d3371568081f868a62b2d41975a | |
| parent | a61fc423f3c043314efd4c0cdb1367de2077ac36 [diff] |
[AMDGPU] Override PSet for M0 This change returns empty PSet list for M0 register. Otherwise its PSet as defined by tablegen is SReg_32. This results in incorrect register pressure calculation every time an instruction uses M0. Such uses count as SReg_32 PSet and inadequately increase pressure on SGPRs. Differential Revision: https://reviews.llvm.org/D29798 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294691 91177308-0d34-0410-b5e6-96231b3b80d8