19bc3f9a843b7072d63c2545d771b08d8d821d8d - platform_external_llvm80

commit	19bc3f9a843b7072d63c2545d771b08d8d821d8d	[log] [tgz]
author	Craig Topper <craig.topper@intel.com>	Sat Nov 04 06:44:47 2017 +0000
committer	Craig Topper <craig.topper@intel.com>	Sat Nov 04 06:44:47 2017 +0000
tree	4721e5b00599ee161ea9dba3cf36f6714edb9a49
parent	5473af6661103fb6509c89880a08b2f24a3f760a [diff]

[X86] Teach shuffle lowering to use 256-bit SHUF128 when possible.

This allows masked operations to be used and allows the register allocator to use YMM16-31 if necessary.

As a follow up I'll look into teaching EVEX->VEX how to turn this back into PERM2X128 if any of the additional features don't work out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317403 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp[diff]
test/CodeGen/X86/avx-schedule.ll[diff]
test/CodeGen/X86/avx2-schedule.ll[diff]
test/CodeGen/X86/avx512-shuffle-schedule.ll[diff]
test/CodeGen/X86/avx512-shuffles/shuffle-vec.ll[diff]
test/CodeGen/X86/vector-shuffle-256-v16.ll[diff]
test/CodeGen/X86/vector-shuffle-256-v32.ll[diff]
test/CodeGen/X86/vector-shuffle-256-v4.ll[diff]
test/CodeGen/X86/vector-shuffle-256-v8.ll[diff]

9 files changed

tree: 4721e5b00599ee161ea9dba3cf36f6714edb9a49