AArch64: Disable the latency heuristic

It turned out not to improve any of our benchmarks but occasionally led
to increased register pressure and spilling.

Only enabling for the Cyclone CPU as the results on the cortex CPUs
give mixed results.

Differential Revision: http://reviews.llvm.org/D13708

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251038 91177308-0d34-0410-b5e6-96231b3b80d8
1 file changed