| commit | 855b4f981a3669a2725d706327a851ae3e7531aa | [log] [tgz] |
|---|---|---|
| author | Dylan McKay <me@dylanmckay.io> | Sat Sep 01 12:22:07 2018 +0000 |
| committer | Dylan McKay <me@dylanmckay.io> | Sat Sep 01 12:22:07 2018 +0000 |
| tree | 6eb99f8916d16490d737185a8b5120cc3f53291a | |
| parent | 051c6130853d67fc848d9b3b0b468e8c47b4b461 [diff] |
[AVR] Define the ROL instruction as an alias of ADC The 'rol Rd' instruction is equivalent to 'adc Rd'. This caused compile warnings from tablegen because of conflicting bits shared between each instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341275 91177308-0d34-0410-b5e6-96231b3b80d8