1437cc9a5273f270736b55cb4a47bcf3df11d4a9 - platform_external_llvm80

commit	1437cc9a5273f270736b55cb4a47bcf3df11d4a9	[log] [tgz]
author	Alex Bradbury <asb@lowrisc.org>	Thu Oct 19 14:29:03 2017 +0000
committer	Alex Bradbury <asb@lowrisc.org>	Thu Oct 19 14:29:03 2017 +0000
tree	01cfab8a3e7446e250939b6db31b064d970ba84c
parent	c6c4c8b8a6781cc320ae6dd2f980997e010b6ea0 [diff]

[RISCV] Prepare for the use of variable-sized register classes

While parameterising by XLen, also take the opportunity to clean up the 
formatting of the RISCV .td files.

This commit unifies the in-tree code with my patchset at 
<https://github.com/lowrisc/riscv-llvm>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316159 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp[diff]
lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h[diff]
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp[diff]
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp[diff]
lib/Target/RISCV/RISCV.td[diff]
lib/Target/RISCV/RISCVInstrFormats.td[diff]
lib/Target/RISCV/RISCVInstrInfo.td[diff]
lib/Target/RISCV/RISCVRegisterInfo.td[diff]

8 files changed

tree: 01cfab8a3e7446e250939b6db31b064d970ba84c