94f16be23805cf47f85c29ca7c5edf15faec289f - platform_external_llvm80

commit	94f16be23805cf47f85c29ca7c5edf15faec289f	[log] [tgz]
author	Alex Bradbury <asb@lowrisc.org>	Wed Mar 21 15:11:02 2018 +0000
committer	Alex Bradbury <asb@lowrisc.org>	Wed Mar 21 15:11:02 2018 +0000
tree	458e44dce120ac071d41f3127d33238645023e10
parent	30a32a618edd12c684185f53a2bfeb62e256c3be [diff]

[RISCV] Codegen support for RV32F floating point comparison operations

This patch also includes extensive tests targeted at select and br+fcmp IR
inputs. A sequence of br+fcmp required support for FPR32 registers to be added
to RISCVInstrInfo::storeRegToStackSlot and
RISCVInstrInfo::loadRegFromStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328104 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/RISCV/RISCVISelLowering.cpp[diff]
lib/Target/RISCV/RISCVInstrInfo.cpp[diff]
lib/Target/RISCV/RISCVInstrInfo.td[diff]
lib/Target/RISCV/RISCVInstrInfoF.td[diff]
test/CodeGen/RISCV/bare-select.ll[diff]
test/CodeGen/RISCV/float-br-fcmp.ll[Added - diff]
test/CodeGen/RISCV/float-fcmp.ll[Added - diff]
test/CodeGen/RISCV/float-select-fcmp.ll[Added - diff]

8 files changed

tree: 458e44dce120ac071d41f3127d33238645023e10