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review.blissroms.org / platform_external_llvm80 / 643edab2b0ae598f4790b997e8eec5721bd00155
  1. 643edab Fix APFloat from string conversion for Inf by Serguei Katkov · 8 years ago
  2. 4bebdd9 [TableGen][GlobalISel] Reset the internal map of RuleMatchers just before the emission by Quentin Colombet · 8 years ago
  3. e3014ee Fix Wasm as a follow up to r321035 and the other one by Reid Kleckner · 8 years ago
  4. 437b240 update_mir_test_checks: Accept IR as input as well as MIR by Justin Bogner · 8 years ago
  5. e812fcb [llvm-objcopy] Add option to add a progbits section from a file by Jake Ehrlich · 8 years ago
  6. 51a1d9a TargetLoweringBase: Followup to r321035 by Matthias Braun · 8 years ago
  7. ea2d46a TargetLowering: Fix InitLibcallCallingConvs() overriding things set in InitLibcalls() by Matthias Braun · 8 years ago
  8. d53e702 TargetLowering: Fix off-by-one error by Matthias Braun · 8 years ago
  9. 44b9704 [llvm-readobj] Dump wasm init functions by Sam Clegg · 8 years ago
  10. c2b744f TargetLoweringBase: Remove unnecessary watchos exception; NFC by Matthias Braun · 8 years ago
  11. 537c6ee update_mir_test_checks: Add "mir" to some states and regex names by Justin Bogner · 8 years ago
  12. 8f06a7d [X86] Don't use NOPL when the assembler is passed an empty CPU string. by Craig Topper · 8 years ago
  13. 209f048 LiveStacks: Rename LiveStack.{h|cpp} to LiveStacks.{h|cpp}; NFC by Matthias Braun · 8 years ago
  14. 4f43d6f X86/AArch64/ARM: Factor out common sincos_stret logic; NFCI by Matthias Braun · 8 years ago
  15. 40c1668 AArch64/X86: Factor out common bzero logic; NFC by Matthias Braun · 8 years ago
  16. b01d498 [Hexagon] Cache loads to select to avoid traversing mutating DAG by Krzysztof Parzyszek · 8 years ago
  17. fd4ed12 Revert part of r321026 "[X86] Don't use NOPL when the assembler is passed an empty CPU string." while I investigate how to fix an lld test failure. by Craig Topper · 8 years ago
  18. 456d279 [AArch64] Expand test coverage of vector element shuffling to Exynos by Evandro Menezes · 8 years ago
  19. df42abc [TableGen][GlobalISel] Make the arguments of the Instruction and Operand Matchers consistent by Quentin Colombet · 8 years ago
  20. b43be72 Fix buffer overrun in WindowsResourceCOFFWriter::writeSymbolTable() by Bob Haarman · 8 years ago
  21. f56fea2 Add test for .req directive starting with 'p' by Reid Kleckner · 8 years ago
  22. 2bd867a [MachineOutliner][NFC] Gardening: use std::any_of instead of bool + loop by Jessica Paquette · 8 years ago
  23. a0209c5 [X86] Don't use NOPL when the assembler is passed an empty CPU string. Update tests to force a CPU with NOPL by Craig Topper · 8 years ago
  24. ebf7d45 [TableGen][GlobalISel] Refactor optimizeRules related bit to allow code reuse by Quentin Colombet · 8 years ago
  25. b198292 Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo by Reid Kleckner · 8 years ago
  26. 7c48f0a [Analysis] Generate more precise TBAA tags when one access encloses the other by Ivan A. Kosarev · 8 years ago
  27. 833c475 [PGO] Fix handling of cold entry count for instrumented PGO by Teresa Johnson · 8 years ago
  28. d3fbd02 [TableGen][GlobalISel] Optimize MatchTable for faster instruction selection by Quentin Colombet · 8 years ago
  29. d1fe0c4 Fix more inconsistent line endings. NFC. by Dimitry Andric · 8 years ago
  30. 93e431a [X86] Minor formatting fix to getHostCPUFeatures. NFC by Craig Topper · 8 years ago
  31. d4a00a6 [MachineOutliner] Recommit r320229 by Jessica Paquette · 8 years ago
  32. 7db7ed3 [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation. by Benjamin Kramer · 8 years ago
  33. d33f76c [cmake] Update experimental target error message by Don Hinton · 8 years ago
  34. a6d921e Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header." by Paul Robinson · 8 years ago
  35. 0aa7e5a [PPC] Disable reg+reg to reg+imm transformation. by Benjamin Kramer · 8 years ago
  36. 68e8e68 Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC. by Dimitry Andric · 8 years ago
  37. 65d3bc2 [Hexagon] Higher versions of HVX imply presence of lower versions by Krzysztof Parzyszek · 8 years ago
  38. b10a40f7 [IR] Support the new TBAA metadata format in IR verifier by Ivan A. Kosarev · 8 years ago
  39. 826e27c Fix inconsistent line endings in ARCDisassembler.cpp. NFC. by Dimitry Andric · 8 years ago
  40. 7364392 i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004 by Krzysztof Parzyszek · 8 years ago
  41. 228589c [Hexagon] Generate HVX code for vector sign-, zero- and any-extends by Krzysztof Parzyszek · 8 years ago
  42. cfd421b [X86] Regenerate test to improve codegen testing for D41350 by Simon Pilgrim · 8 years ago
  43. 5966988 [Hexagon] Prefer to widen HVX vectors instead of promoting by Krzysztof Parzyszek · 8 years ago
  44. 1f57e5d Removed unused DominanceFrontier by Matt Arsenault · 8 years ago
  45. 2b18c99 [ThinLTO] Make distributed indexes test more robust by Teresa Johnson · 8 years ago
  46. 03a6f4a [PGO] add MST min edge selection heuristic to ensure non-zero entry count by Xinliang David Li · 8 years ago
  47. 65ad22d [YAML] Add support for non-printable characters by Francis Visoiu Mistrih · 8 years ago
  48. d6be214 [IR] Add MDBuilder helpers for the new TBAA metadata format by Ivan A. Kosarev · 8 years ago
  49. f829832 [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specified by Sander de Smalen · 8 years ago
  50. 6b66227 Reland "[mips] Fix the target specific instruction verifier" by Simon Dardis · 8 years ago
  51. b71c6a9 [Memcpy Loop Lowering] Remove the fixed int8 lowering. by Sean Fertile · 8 years ago
  52. a1f6793 [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction by Sander de Smalen · 8 years ago
  53. 7a7c05d [LVI] Support for ashr in LVI by Max Kazantsev · 8 years ago
  54. 1346bcc [ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524 by Diana Picus · 8 years ago
  55. afb8875 Constexprify LaneBitmask factory methods. by Benjamin Kramer · 8 years ago
  56. 5cecfe9 [ConstantRange] Support for ashr in ConstantRange computation by Max Kazantsev · 8 years ago
  57. 7a92215 Revert "[mips] Fix the target specific instruction verifier" by Simon Dardis · 8 years ago
  58. bf08176 [mips] Fix the target specific instruction verifier by Simon Dardis · 8 years ago
  59. 9d49216 [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors) by Sander de Smalen · 8 years ago
  60. 29dd081 [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support by Sander de Smalen · 8 years ago
  61. 0e72a72 [ThinLTO] Remove unused code by Eugene Leviant · 8 years ago
  62. f66f36e AArch64: work around how Cyclone handles "movi.2d vD, #0". by Tim Northover · 8 years ago
  63. b887495 [TargetLibraryInfo] Discard library functions with incorrectly sized integers by Igor Laevsky · 8 years ago
  64. 2e83f99 [ARM] Adjust test checks by Sam Parker · 8 years ago
  65. 72b2ece [DAGCombine] Move AND nodes to multiple load leaves by Sam Parker · 8 years ago
  66. 805454d [NFC][CodeGen][ExpandMemCmp] Fix documentation. by Clement Courbet · 8 years ago
  67. 2794ae2 [X86] Use mattr instead of mcpu in some of the cost model tests. by Craig Topper · 8 years ago
  68. f8bf5c2 [SROA] Disable non-whole-alloca splits by default by Hiroshi Inoue · 8 years ago
  69. a9e5853 [X86] Fix mistake that I made when splitting up the setOperationAction calls recently. by Craig Topper · 8 years ago
  70. 5f348c6 [CGP] Fix the handling select inst in complex addressing mode by Serguei Katkov · 8 years ago
  71. cff5adc [x86] add tests for finite libcall lowering (PR35672); NFC by Sanjay Patel · 8 years ago
  72. 53f8289 Re-commit "Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes()"" by Bjorn Steinbrink · 8 years ago
  73. 89e3680 [X86] Add test cases that show cases where buildvector of extract and inserts should be turned into fmsubadd. by Craig Topper · 8 years ago
  74. aa22588 [X86] Make the code that creates fmaddsub from build_vector of extracts and inserts functional and add tests. by Craig Topper · 8 years ago
  75. 7dd441d [X86] Regenerate truncated rotation tests + add missing 32-bit checks by Simon Pilgrim · 8 years ago
  76. b9eb8ce use uint32_t by Sam Clegg · 8 years ago
  77. 6e6de69 [WebAssembly] Export some more info on wasm funtions by Sam Clegg · 8 years ago
  78. ce542fd Revert "Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes()" by Bjorn Steinbrink · 8 years ago
  79. 7bf95b4 Revert "Treat sret arguments as being dereferenceable in getPointerDereferenceableBytes()" by Bjorn Steinbrink · 8 years ago
  80. 8b7a766 Treat sret arguments as being dereferenceable in getPointerDereferenceableBytes() by Bjorn Steinbrink · 8 years ago
  81. 4521272 Remove superfluous break after a return. NFCI. by Simon Pilgrim · 8 years ago
  82. eb51e21 [X86DomainReassignment] Store legal domains in a std::bitset instead of using a SmallVector that really only ever has one element as a set. by Craig Topper · 8 years ago
  83. b2ce483 Properly handle byval arguments in getPointerDereferenceableBytes() by Bjorn Steinbrink · 8 years ago
  84. 217067d Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes() by Bjorn Steinbrink · 8 years ago
  85. 43beef6 [X86] Use extract_vector_elt instead of X86ISD::VEXTRACT for isel of vXi1 extractions. by Craig Topper · 8 years ago
  86. 036a90a [X86] Canonicalize extract_vector_elt from vXi1 to always return MVT::i32. by Craig Topper · 8 years ago
  87. e03e617 [X86] Don't create X86ISD::VEXTRACT nodes directly. Use EXTRACT_VECTOR_ELT and allow that to be legaized to VEXTRACT. by Craig Topper · 8 years ago
  88. c61df73 Fix unused variable warning. by Simon Pilgrim · 8 years ago
  89. 9974ce9 [X86][AVX] lowerVectorShuffleAsBroadcast - aggressively peek through BITCASTs by Simon Pilgrim · 8 years ago
  90. ebebd80 [X86][AVX] Use extract128BitVector helper. NFCI. by Simon Pilgrim · 8 years ago
  91. e15bb62 [X86][AVX] Fix failed broadcast fold by Simon Pilgrim · 8 years ago
  92. a9c4e7f [Memcpy Loop Lowering] Only calculate residual size/bytes copied when needed. by Sean Fertile · 8 years ago
  93. 8923be6 [X86] Don't pass a zero input to the passthru operand of getVectorMaskingNode/getScalarMaskingNode when its going to emit an ISD::OR/ISD::AND. NFCI by Craig Topper · 8 years ago
  94. ab97c30 [X86] Have getVectorMaskingNode return an ISD::AND for X86ISD::VPSHUFBITQMB instead of creating a select with one input being 0. by Craig Topper · 8 years ago
  95. be2953e [X86] When using vpopcntdq for ctpop of v8i16 vectors, only promote to v8i32. by Craig Topper · 8 years ago
  96. 2ab1917 [X86] Combine some more scheduler model entries using regular expressions. by Craig Topper · 8 years ago
  97. 9d5f0f8 [X86] Use instrs instead of instregex for gather/scatter instructions in the scheduler models. Combine into single InstrRW entries. by Craig Topper · 8 years ago
  98. 905b9d3 [InstCombine] Regenerate FMUL/FMA combine tests with update_test_checks.py by Simon Pilgrim · 8 years ago
  99. ccf3928 [InstCombine] canonicalize shifty abs(): ashr+add+xor --> cmp+neg+sel by Sanjay Patel · 8 years ago
  100. 09a3b12 [X86] Remove GCCBuiltin from kand/kandn/kor/kxor/kxnor/knot intrinsics so clang can implement with native IR. by Craig Topper · 8 years ago