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review.blissroms.org / platform_external_llvm80 / 8270e68c560fce9dd457ec815e6dd141eacadb2e
  1. 8270e68 [mips] brcond + setgt/setugt instruction selection patterns. by Akira Hatanaka · 12 years ago
  2. db9dc53 yaml2obj: add -format=<fmt> to choose input YAML interpretation by Sean Silva · 12 years ago
  3. cc81b38 Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit. by Jakub Staszak · 12 years ago
  4. 9a508ef [PATCH] Fix VGATHER* operand constraints by Michael Liao · 12 years ago
  5. bcb1ea8 Represent symbols with a SymbolIndex,SectionIndex pair. by Rafael Espindola · 12 years ago
  6. 31588f3 ARM sched model: Add more ALU and CMP instructions by Arnold Schwaighofer · 12 years ago
  7. c821573 ARM sched model: Add divsion, loads, branches, vfp cvt by Arnold Schwaighofer · 12 years ago
  8. d87bd56 ARMInstrInfo: Improve isSwiftFastImmShift by Arnold Schwaighofer · 12 years ago
  9. fcce70a SubtargetEmitter fix by Arnold Schwaighofer · 12 years ago
  10. 2248cf5 This is a simple patch that changes RRX and RRXS to accept all registers as operands. by Mihai Popa · 12 years ago
  11. 7e12946 The GNU/HURD is also using the libc. Therefor, endian.h should be included, not machine/endian.h. See full build log https://buildd.debian.org/status/fetch.php?pkg=llvm-toolchain-3.3&arch=hurd-i386&ver=1%3A3.3~%2Brc3-1~exp1&stamp=1370358869 by Sylvestre Ledru · 12 years ago
  12. d7aad34 Fix a tblgen subtargetemitter bug, for future Swift support. by Andrew Trick · 12 years ago
  13. 032d624 PR15662: Optimized debug info produces out of order function parameters by David Blaikie · 12 years ago
  14. ad7ecc6 R600: Make sure to schedule AR register uses and defs in the same clause by Tom Stellard · 12 years ago
  15. 23a22cd Don't print default values for NumberOfAuxSymbols and AuxiliaryData. by Rafael Espindola · 12 years ago
  16. 0962b16 Handle (at least don't crash on) relocations with no symbols. by Rafael Espindola · 12 years ago
  17. 5fd5fe0 Move BinaryRef to a new include/llvm/Object/YAML.h file. by Rafael Espindola · 12 years ago
  18. 6afb65c Revert "R600: Add a pass that merge Vector Register" by Rafael Espindola · 12 years ago
  19. 6c1202c Handle relocations that don't point to symbols. by Rafael Espindola · 12 years ago
  20. cc5a6cb [docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE() macro by Sean Silva · 12 years ago
  21. bbbdba8 R600: Add a pass that merge Vector Register by Vincent Lejeune · 12 years ago
  22. e67a4af R600: Const/Neg/Abs can be folded to dot4 by Vincent Lejeune · 12 years ago
  23. 00ed010 Cortex-R5 can issue Thumb2 integer division instructions. by Evan Cheng · 12 years ago
  24. 8a22708 Revert series of sched model patches until I figure out what is going on. by Arnold Schwaighofer · 12 years ago
  25. f500aa0 ARM sched model: Add VFP div instruction on Swift by Arnold Schwaighofer · 12 years ago
  26. 858f6f8 ARM sched model: Add SIMD/VFP load/store instructions on Swift by Arnold Schwaighofer · 12 years ago
  27. e52041c ARM sched model: Add integer VFP/SIMD instructions on Swift by Arnold Schwaighofer · 12 years ago
  28. f3a2329 ARM sched model: Add integer load/store instructions on Swift by Arnold Schwaighofer · 12 years ago
  29. 755d129 ARM sched model: Add integer arithmetic instructions on Swift by Arnold Schwaighofer · 12 years ago
  30. eb9948e ARM sched model: Cortex A9 - More InstRW sched resources by Arnold Schwaighofer · 12 years ago
  31. 002faf2 ARM sched model: Add branch thumb instructions by Arnold Schwaighofer · 12 years ago
  32. 16d9150 ARM sched model: Add branch thumb2 instructions by Arnold Schwaighofer · 12 years ago
  33. 36ea791 ARM sched model: Add branch instructions by Arnold Schwaighofer · 12 years ago
  34. fdbca2f ARM sched model: Add preload thumb2 instructions by Arnold Schwaighofer · 12 years ago
  35. d3b8445 ARM sched model: Add preload instructions by Arnold Schwaighofer · 12 years ago
  36. 23cb39a ARM sched model: Add more ALU and CMP thumb instructions by Arnold Schwaighofer · 12 years ago
  37. 1942e32 ARM sched model: Add more ALU and CMP thumb2 instructions by Arnold Schwaighofer · 12 years ago
  38. 4c53731 ARM sched model: Add more ALU and CMP instructions by Arnold Schwaighofer · 12 years ago
  39. 611c6e1 ARM sched model: Add divsion, loads, branches, vfp cvt by Arnold Schwaighofer · 12 years ago
  40. ede7eea ARMInstrInfo: Improve isSwiftFastImmShift by Arnold Schwaighofer · 12 years ago
  41. 54d63cc SubtargetEmitter fix by Arnold Schwaighofer · 12 years ago
  42. 2b18526 Fix link. by Richard Smith · 12 years ago
  43. 1e06bcb Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., by Venkatraman Govindaraju · 12 years ago
  44. 5a57dbe IndVarSimplify: check if loop invariant expansion can trap by David Majnemer · 12 years ago
  45. 35e7751 ARM: Fix crash in ARM backend inside of ARMConstantIslandPass by David Majnemer · 12 years ago
  46. 8240ef0 Remove "-Wl,-seg1addr -Wl,0xE0000000" from link options. by Bob Wilson · 12 years ago
  47. 98017a0 R600: Swizzle texture/export instructions by Vincent Lejeune · 12 years ago
  48. 932843832 R600: Add a test for r183108 by Vincent Lejeune · 12 years ago
  49. babae05 Second part of pr16069 by Rafael Espindola · 12 years ago
  50. deb2e9c Typo: s/caes/cases/ in SimplifyCFG by Hans Wennborg · 12 years ago
  51. f102f31 Preserve const correctness. by Benjamin Kramer · 12 years ago
  52. 164de54 Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp. by Vladimir Medic · 12 years ago
  53. 888ca96 [llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume that symbols with zero size are in fact large enough. by Alexey Samsonov · 12 years ago
  54. 1c611ec We are now in 3.4 land. We don't need the 3.3 releaese notes in ToT anymore. by Bill Wendling · 12 years ago
  55. b30718a IEEE-754R 5.7.2 General Operations is* operations (except for isCanonical). by Michael Gottesman · 12 years ago
  56. f3d3952 Silencing an MSVC warning about mixing bool and unsigned int. by Aaron Ballman · 12 years ago
  57. f56a6de Silencing an MSVC warning about */ being found outside of a comment. by Aaron Ballman · 12 years ago
  58. 45c7544 Fix a defect in code-layout pass, improving Benchmarks/Olden/em3d/em3d by about 30% by Shuxin Yang · 12 years ago
  59. 4526d1c Delete dead safety check. by Nick Lewycky · 12 years ago
  60. 3931bdb SimplifyCFG: Do not transform PHI to select if doing so would be unsafe by David Majnemer · 12 years ago
  61. 404fa72 SimplifyCFG: Small cleanup, use ICmpInst::isEquality() by David Majnemer · 12 years ago
  62. 031a179 Remove dead code. by Rafael Espindola · 12 years ago
  63. 15e5c46 Update RuntimeDyldELF::findOPDEntrySection the new relocation iterators. by Rafael Espindola · 12 years ago
  64. d1100b3 Enable mcjit tests on ppc64 when building with cmake. by Rafael Espindola · 12 years ago
  65. e5fcc0d R600/SI: Add support for work item and work group intrinsics by Tom Stellard · 12 years ago
  66. e7397ee R600/SI: Add a calling convention for compute shaders by Tom Stellard · 12 years ago
  67. e86f9d7 R600/SI: Custom lower i64 sign_extend by Tom Stellard · 12 years ago
  68. 17e8ad6 R600/SI: Adjust some instructions' out register class after ISel by Tom Stellard · 12 years ago
  69. b89a467 R600/SI: Handle REG_SEQUENCE in fitsRegClass() by Tom Stellard · 12 years ago
  70. 051a28e R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() by Tom Stellard · 12 years ago
  71. 8a72c73 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() by Tom Stellard · 12 years ago
  72. 1321835 R600/SI: Add support for global loads by Tom Stellard · 12 years ago
  73. 4956bc6 R600/SI: Rework MUBUF store instructions by Tom Stellard · 12 years ago
  74. 0c92287 R600: 3 op instructions have no write bit but the result are store in PV by Vincent Lejeune · 12 years ago
  75. fdf7ab1 R600: CALL_FS consumes a stack size entry by Vincent Lejeune · 12 years ago
  76. 96fe0be R600: use capital letter for PV channel by Vincent Lejeune · 12 years ago
  77. 0962e14 R600: Constraints input regs of interp_xy,_zw by Vincent Lejeune · 12 years ago
  78. 3e1d45b [asan] ASan Linux MIPS32 support (llvm part), patch by Jyun-Yan Y by Kostya Serebryany · 12 years ago
  79. b8ce457 X86: sub_xmm registers are 128 bits wide. by Ahmed Bougacha · 12 years ago
  80. 625b109 Correct handling invalid filename in llvm-symbolizer by Alexey Samsonov · 12 years ago
  81. abff3aa Introduce needsCleanup() for APFloat and APInt. by Manuel Klimek · 12 years ago
  82. e7cbb79 Sparc: Add support for indirect branch and blockaddress in Sparc backend. by Venkatraman Govindaraju · 12 years ago
  83. 891c0cd [Object/COFF] Fix Windows .lib name handling. by Rui Ueyama · 12 years ago
  84. 85cc972 Sparc: When storing 0, use %g0 directly in the store instruction instead of by Venkatraman Govindaraju · 12 years ago
  85. 65ca7aa Sparc: Combine add/or/sethi instruction with restore if possible. by Venkatraman Govindaraju · 12 years ago
  86. 0a972fa [Object/COFF] Add dos_header, pe32{,plus}_header and data_directory. by Rui Ueyama · 12 years ago
  87. 2ee6c7f Whitespace. by Jim Grosbach · 12 years ago
  88. dd48226 Sparc: Perform leaf procedure optimization by default by Venkatraman Govindaraju · 12 years ago
  89. 44dbb74 Try to avoid "integer literal too big" warnings from older GCCs. by Benjamin Kramer · 12 years ago
  90. e4546cb When determining the new index for an insertelement, we may not assume that an by Nick Lewycky · 12 years ago
  91. a0b34d6 Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions. by Venkatraman Govindaraju · 12 years ago
  92. f7dad78 SimplifyCFG: Fix typo in comment for ComputeSpeculationCost by David Majnemer · 12 years ago
  93. 7c2b4be Move getRealLinkageName to a common place and remove all the duplicates of it. by Benjamin Kramer · 12 years ago
  94. 6dd56e6 Move object construction into [] so the temporary can be moved. by Benjamin Kramer · 12 years ago
  95. da8b91a DenseMap: Move the key into place when we use the move version of operator[]. by Benjamin Kramer · 12 years ago
  96. 8e85192 APInt: Simplify code. No functionality change. by Benjamin Kramer · 12 years ago
  97. 77e5c2a APFloat: Use isDenormal instead of hand-rolled code to check for denormals. by Benjamin Kramer · 12 years ago
  98. 95a565a Disable new legacy JIT test on ARM. by Tim Northover · 12 years ago
  99. 3ba14fa Revert r183069: "TMP: LEA64_32r fixing" by Tim Northover · 12 years ago
  100. 4d3ace4 TMP: LEA64_32r fixing by Tim Northover · 12 years ago