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review.blissroms.org / platform_external_llvm80 / f4a66d2005f585737cfe5e7dbe133fe9e9ec0b83
  1. f4a66d2 Correct wrong register in this example, pointed out by Baoshan Pang. by Duncan Sands · 12 years ago
  2. 80ada58 Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  3. 41e632d Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  4. ed8b5b5 Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  5. 637eab6 Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  6. 54a56fa Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  7. 9eb856b [objc-arc] Ensure that the cfg path count does not overflow when we multiply TopDownPathCount/BottomUpPathCount. by Michael Gottesman · 12 years ago
  8. 57148c1 Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  9. 4393f48 Don't cache the instruction info and register info objects. by Bill Wendling · 12 years ago
  10. 37bfb18 DIBuilder: No functionality change. by Manman Ren · 12 years ago
  11. c6752d5 ARM sched model: Use the right resources for DIV by Arnold Schwaighofer · 12 years ago
  12. 873ff29 ARM sched model: Add VFP div instruction on Swift by Arnold Schwaighofer · 12 years ago
  13. 0efc782 CodeGenSchedule: Use resize instead of copying a vector by Arnold Schwaighofer · 12 years ago
  14. 7f155d7 ARM sched model: Add SIMD/VFP load/store instructions on Swift by Arnold Schwaighofer · 12 years ago
  15. 01021a8 [Sparc]: Use cmp instruction instead of subcc to compare integers. by Venkatraman Govindaraju · 12 years ago
  16. 6a72c84 Simplify code. No functionality change. by Jakub Staszak · 12 years ago
  17. 326ae27 Remove unneeded #include. by Jakub Staszak · 12 years ago
  18. 45dc032 CodeGenSchedule: smallvector.push_back(smallvector[0]) is dangerous by Arnold Schwaighofer · 12 years ago
  19. 81c5d11 R600: Rewrite an awkward loop in R600MachineScheduler by Vincent Lejeune · 12 years ago
  20. 9342b9c Jeffrey Yasskin volunteered to benchmark the vectorizer on -O2 or -Os when compiling chrome. This patch adds a new flag to enable vectorization on all levels and not only on -O3. It should go away once we make a decision. by Nadav Rotem · 12 years ago
  21. babfebb Fix break in r183446 - helps to increment the iterator in a loop by David Blaikie · 12 years ago
  22. 6b10d85 Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift" by Arnold Schwaighofer · 12 years ago
  23. b20fdff Debug Info: simplify parameter ordering preservation by David Blaikie · 12 years ago
  24. 5bf5b96 ARM sched model: Add SIMD/VFP load/store instructions on Swift by Arnold Schwaighofer · 12 years ago
  25. 285bd8e Move the test for the data in code into the ARM directory as it is an ARM by Kevin Enderby · 12 years ago
  26. 5be946b ARM sched model: Add integer VFP/SIMD instructions on Swift by Arnold Schwaighofer · 12 years ago
  27. 3facc43 Re-apply "Use IRBuilder instead of ConstantInt methods." with the fixed issues. by Jakub Staszak · 12 years ago
  28. d9445b6 ARM sched model: Add integer load/store instructions on Swift by Arnold Schwaighofer · 12 years ago
  29. 67c2056 ARM sched model: Add integer arithmetic instructions on Swift by Arnold Schwaighofer · 12 years ago
  30. d8f8c35 ARM sched model: Cortex A9 - More InstRW sched resources by Arnold Schwaighofer · 12 years ago
  31. ab9ba53 Add a testcase from pr16244. by Rafael Espindola · 12 years ago
  32. f1f6dce ARM sched model: Add branch thumb instructions by Arnold Schwaighofer · 12 years ago
  33. a6db677 ARM sched model: Add branch thumb2 instructions by Arnold Schwaighofer · 12 years ago
  34. 87aab6d ARM sched model: Add branch instructions by Arnold Schwaighofer · 12 years ago
  35. 3ba4778 ARM sched model: Add preload thumb2 instructions by Arnold Schwaighofer · 12 years ago
  36. 239f8a4 Remove unimplemented definition. Found using [-Wunused-member-function]. by Jakub Staszak · 12 years ago
  37. e022a6b ARM sched model: Add preload instructions by Arnold Schwaighofer · 12 years ago
  38. 54154f3 Teach llvm-objdump with the -macho parser how to use the data in code table by Kevin Enderby · 12 years ago
  39. f2988a0 ARM sched model: Add more ALU and CMP thumb instructions by Arnold Schwaighofer · 12 years ago
  40. 7de80e0 Revert "Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit." by Rafael Espindola · 12 years ago
  41. 826de68 ARM sched model: Add more ALU and CMP thumb2 instructions by Arnold Schwaighofer · 12 years ago
  42. 5f035d0 R600: Remove leftover code in R600MachineScheduler.cpp by Vincent Lejeune · 12 years ago
  43. e3a0e7f Print symbol names in relocations when dumping COFF as YAML. by Rafael Espindola · 12 years ago
  44. 2ed7659 Cast to the correct type. Pointer, not reference. by Bill Wendling · 12 years ago
  45. 0ac8574 R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized] by NAKAMURA Takumi · 12 years ago
  46. 7b6d32a R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable] by NAKAMURA Takumi · 12 years ago
  47. 3ebcf38 Trailing linefeed. by NAKAMURA Takumi · 12 years ago
  48. b88cef5 Cast to the proper type. by Bill Wendling · 12 years ago
  49. c6e2ab3 Remove unneeded cast<>. by Jakub Staszak · 12 years ago
  50. 272d881 Add some class documentation to BinaryRef. by Sean Silva · 12 years ago
  51. 6a2e7ac Cache the TargetLowering info object as a pointer. by Bill Wendling · 12 years ago
  52. f2d03d7 Use IRBuilder instead of ConstantInt methods. by Jakub Staszak · 12 years ago
  53. 384ceb8 Don't cache the TargetLoweringInfo object inside of the FunctionLowering object. by Bill Wendling · 12 years ago
  54. cfb476f Rename operator== parameter to `RHS`. by Sean Silva · 12 years ago
  55. 0d861a2 Remove error-prone methods of BinaryRef. by Sean Silva · 12 years ago
  56. 4370ddb Add writeAsHex(raw_ostream &) method to BinaryRef. by Sean Silva · 12 years ago
  57. c170230 R600: Replace predicate loop with predicate function by Tom Stellard · 12 years ago
  58. 6acc982 Rename BinaryRef::isBinary to more descriptive DataIsHexString. by Sean Silva · 12 years ago
  59. 63958fb Add BinaryRef binary_size() method. by Sean Silva · 12 years ago
  60. 2b10689 Comment BinaryRef::Data. by Sean Silva · 12 years ago
  61. 0836838 Add space to assert message. by Bill Wendling · 12 years ago
  62. 639adc5 Add writeAsBinary(raw_ostream &) method to BinaryRef. by Sean Silva · 12 years ago
  63. f3d6e32 R600: Add a pass that merge Vector Register by Vincent Lejeune · 12 years ago
  64. f41d317 [docs] Add link to C++ ABI document. by Sean Silva · 12 years ago
  65. c85756f [docs] Add link to SysV ABI document. by Sean Silva · 12 years ago
  66. d56d756 [ELF] Add ELFOSABI_GNU. by Sean Silva · 12 years ago
  67. c9f2cc7 Don't hide the first ELF symbol. by Rafael Espindola · 12 years ago
  68. 5121197 R600: Schedule copy from phys register at beginning of block by Vincent Lejeune · 12 years ago
  69. 6ed30e0 yaml2obj: split out COFF logic into separate file by Sean Silva · 12 years ago
  70. 8270e68 [mips] brcond + setgt/setugt instruction selection patterns. by Akira Hatanaka · 12 years ago
  71. db9dc53 yaml2obj: add -format=<fmt> to choose input YAML interpretation by Sean Silva · 12 years ago
  72. cc81b38 Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit. by Jakub Staszak · 12 years ago
  73. 9a508ef [PATCH] Fix VGATHER* operand constraints by Michael Liao · 12 years ago
  74. bcb1ea8 Represent symbols with a SymbolIndex,SectionIndex pair. by Rafael Espindola · 12 years ago
  75. 31588f3 ARM sched model: Add more ALU and CMP instructions by Arnold Schwaighofer · 12 years ago
  76. c821573 ARM sched model: Add divsion, loads, branches, vfp cvt by Arnold Schwaighofer · 12 years ago
  77. d87bd56 ARMInstrInfo: Improve isSwiftFastImmShift by Arnold Schwaighofer · 12 years ago
  78. fcce70a SubtargetEmitter fix by Arnold Schwaighofer · 12 years ago
  79. 2248cf5 This is a simple patch that changes RRX and RRXS to accept all registers as operands. by Mihai Popa · 12 years ago
  80. 7e12946 The GNU/HURD is also using the libc. Therefor, endian.h should be included, not machine/endian.h. See full build log https://buildd.debian.org/status/fetch.php?pkg=llvm-toolchain-3.3&arch=hurd-i386&ver=1%3A3.3~%2Brc3-1~exp1&stamp=1370358869 by Sylvestre Ledru · 12 years ago
  81. d7aad34 Fix a tblgen subtargetemitter bug, for future Swift support. by Andrew Trick · 12 years ago
  82. 032d624 PR15662: Optimized debug info produces out of order function parameters by David Blaikie · 12 years ago
  83. ad7ecc6 R600: Make sure to schedule AR register uses and defs in the same clause by Tom Stellard · 12 years ago
  84. 23a22cd Don't print default values for NumberOfAuxSymbols and AuxiliaryData. by Rafael Espindola · 12 years ago
  85. 0962b16 Handle (at least don't crash on) relocations with no symbols. by Rafael Espindola · 12 years ago
  86. 5fd5fe0 Move BinaryRef to a new include/llvm/Object/YAML.h file. by Rafael Espindola · 12 years ago
  87. 6afb65c Revert "R600: Add a pass that merge Vector Register" by Rafael Espindola · 12 years ago
  88. 6c1202c Handle relocations that don't point to symbols. by Rafael Espindola · 12 years ago
  89. cc5a6cb [docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE() macro by Sean Silva · 12 years ago
  90. bbbdba8 R600: Add a pass that merge Vector Register by Vincent Lejeune · 12 years ago
  91. e67a4af R600: Const/Neg/Abs can be folded to dot4 by Vincent Lejeune · 12 years ago
  92. 00ed010 Cortex-R5 can issue Thumb2 integer division instructions. by Evan Cheng · 12 years ago
  93. 8a22708 Revert series of sched model patches until I figure out what is going on. by Arnold Schwaighofer · 12 years ago
  94. f500aa0 ARM sched model: Add VFP div instruction on Swift by Arnold Schwaighofer · 12 years ago
  95. 858f6f8 ARM sched model: Add SIMD/VFP load/store instructions on Swift by Arnold Schwaighofer · 12 years ago
  96. e52041c ARM sched model: Add integer VFP/SIMD instructions on Swift by Arnold Schwaighofer · 12 years ago
  97. f3a2329 ARM sched model: Add integer load/store instructions on Swift by Arnold Schwaighofer · 12 years ago
  98. 755d129 ARM sched model: Add integer arithmetic instructions on Swift by Arnold Schwaighofer · 12 years ago
  99. eb9948e ARM sched model: Cortex A9 - More InstRW sched resources by Arnold Schwaighofer · 12 years ago
  100. 002faf2 ARM sched model: Add branch thumb instructions by Arnold Schwaighofer · 12 years ago