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review.blissroms.org / platform_external_llvm80 / refs/heads/r / lib / CodeGen / MachineCSE.cpp
  1. 315f6cf [MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again) by Roman Tereshin · 7 years ago
  2. 42b5443 [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal. by Carlos Alberto Enciso · 7 years ago
  3. 03c16fb [DWARF] Missing location debug information with -O2. by Carlos Alberto Enciso · 7 years ago
  4. b1c42de [MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs() by Roman Tereshin · 7 years ago
  5. 0818e78 Rename DEBUG macro to LLVM_DEBUG. by Nicola Zaghen · 7 years ago
  6. 24abe71 [DebugInfo] Examine all uses of isDebugValue() for debug instructions. by Shiva Chen · 7 years ago
  7. 53458b4 [MachineCSE] Rewrite a loop checking if a block is in a set of blocks without using a set. NFC. by Michael Zolotukhin · 7 years ago
  8. 3df0e39 GlobalISel: Make MachineCSE runnable in the middle of the GlobalISel by Justin Bogner · 8 years ago
  9. d318139 MachineFunction: Return reference from getFunction(); NFC by Matthias Braun · 8 years ago
  10. fd11bc0 [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. by Francis Visoiu Mistrih · 8 years ago
  11. a4ec08b [CodeGen] Print register names in lowercase in both MIR and debug output by Francis Visoiu Mistrih · 8 years ago
  12. 8c81e85 [MachineCSE] Add new callback for is caller preserved or constant physregs by Tony Jiang · 8 years ago
  13. e3a9b4c Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
  14. 4831923 Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering by David Blaikie · 8 years ago
  15. 2de563a [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
  16. e3e43d9 Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
  17. 94c4904 CodeGen: Rename DEBUG_TYPE to match passnames by Matthias Braun · 8 years ago
  18. 3bfeab4 MachineCSE: Respect interblock physreg liveness by Mikael Holmen · 8 years ago
  19. f295c8c [codegen] Add generic functions to skip debug values. by Florian Hahn · 9 years ago
  20. 15cdf2c MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC by Matthias Braun · 9 years ago
  21. e7555f0 [CodeGen] Rename MachineInstr::isInvariantLoad to isDereferenceableInvariantLoad. NFC by Justin Lebar · 9 years ago
  22. 567409d CodeGen: Use MachineInstr& in TargetInstrInfo, NFC by Duncan P. N. Exon Smith · 9 years ago
  23. 1e455c5 Re-commit optimization bisect support (r267022) without new pass manager support. by Andrew Kaylor · 9 years ago
  24. 8866d94 Revert "Initial implementation of optimization bisect support." by Vedant Kumar · 9 years ago
  25. c852398 Initial implementation of optimization bisect support. by Andrew Kaylor · 9 years ago
  26. e7221e6 [SSP, 2/2] Create llvm.stackguard() intrinsic and lower it to LOAD_STACK_GUARD by Tim Shen · 9 years ago
  27. f4e4e5e rangify; NFCI by Sanjay Patel · 10 years ago
  28. 9146833 [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible by Chandler Carruth · 10 years ago
  29. 7d66bd3 MachineCSE: Add a target query for the LookAheadLimit heurisitic by Tom Stellard · 10 years ago
  30. 1bfcd1f Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. by Benjamin Kramer · 10 years ago
  31. a602c10 MachineCSE: Clear dead-def flag on CSE. by Matthias Braun · 11 years ago
  32. 88d2b58 [MachineCSE] Clear kill-flag on registers imp-def'd by the CSE'd instruction. by Ahmed Bougacha · 11 years ago
  33. 0679d2d In Machine CSE pass, the source register of a COPY machine instruction can by Jiangning Liu · 11 years ago
  34. 6035518 Have MachineFunction cache a pointer to the subtarget to make lookups by Eric Christopher · 11 years ago
  35. 9f85dcc Remove the TargetMachine forwards for TargetSubtargetInfo based by Eric Christopher · 11 years ago
  36. f3224d0 Add TargetInstrInfo interface isAsCheapAsAMove. by Jiangning Liu · 11 years ago
  37. 8677f2f [Modules] Remove potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 11 years ago
  38. 5fa58a5 Disable each MachineFunctionPass for 'optnone' functions, unless that by Paul Robinson · 11 years ago
  39. 92fca73 Switch a number of loops in lib/CodeGen over to range-based for-loops, now that by Owen Anderson · 11 years ago
  40. bf63022 Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing by Owen Anderson · 11 years ago
  41. 9f998de [C++11] Add 'override' keyword to virtual methods that override their base class. by Craig Topper · 12 years ago
  42. 7d7d996 Replace PROLOG_LABEL with a new CFI_INSTRUCTION. by Rafael Espindola · 12 years ago
  43. d628f19 [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. by Benjamin Kramer · 12 years ago
  44. ff7e4b1 Disabled subregister copy coalescing during MachineCSE. by Andrew Trick · 12 years ago
  45. c4c5a1d Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies. by Andrew Trick · 12 years ago
  46. 2eead99 Revert "Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies." by Rafael Espindola · 12 years ago
  47. b961a26 Allow MachineCSE to coalesce trivial subregister copies the same way by Andrew Trick · 12 years ago
  48. 86d2896 whitespace by Andrew Trick · 12 years ago
  49. a0ec3f9 Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. by Craig Topper · 12 years ago
  50. d04a8d4 Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  51. 39834da CSE: allow PerformTrivialCoalescing to check copies across basic block by Manman Ren · 13 years ago
  52. bb8ddc7 Don't use iterator after being erased. by Jakub Staszak · 13 years ago
  53. b64e211 Do not consider a machine instruction that uses and defines the same by Ulrich Weigand · 13 years ago
  54. feab72c Remove unused BitVectors from getAllocatableSet(). by Jakob Stoklund Olesen · 13 years ago
  55. fb9ebbf Switch most getReservedRegs() clients to the MRI equivalent. by Jakob Stoklund Olesen · 13 years ago
  56. 5fa2d45 MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps already. by Benjamin Kramer · 13 years ago
  57. cfc0ad6 PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely. by Benjamin Kramer · 13 years ago
  58. 39ad568 X86: enable CSE between CMP and SUB by Manman Ren · 13 years ago
  59. ba86b13 MachineCSE: Update the heuristics for isProfitableToCSE. by Manman Ren · 13 years ago
  60. 96cb112 Remove tabs. by Bill Wendling · 13 years ago
  61. 7a7a6db Remove ParentMap. You can just ask the domnode for its parent. No functionality by Nick Lewycky · 13 years ago
  62. f152fe8 Switch some getAliasSet clients to MCRegAliasIterator. by Jakob Stoklund Olesen · 13 years ago
  63. e4fd907 Use uint16_t to store register overlaps to reduce static data. by Craig Topper · 14 years ago
  64. 2129a0f Handle regmasks in MachineCSE. by Jakob Stoklund Olesen · 14 years ago
  65. c2e08db Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786. by Lang Hames · 14 years ago
  66. 1834df8 Oop - r150653 + r150654 broke one of my test cases. Backing out for now... by Lang Hames · 14 years ago
  67. f7e31b9 MachineCSE shouldn't extend the live ranges of reserved or allocatable registers. by Lang Hames · 14 years ago
  68. 1dd8c85 Codegen pass definition cleanup. No functionality. by Andrew Trick · 14 years ago
  69. 1df91b0 whitespace by Andrew Trick · 14 years ago
  70. 5b8a1db Persuade GCC that there is nothing worth warning about here (there isn't). by Duncan Sands · 14 years ago
  71. f96703e Avoid CSE of instructions which define physical registers across MBBs unless by Evan Cheng · 14 years ago
  72. 97b5beb Allow machine-cse to look across MBB boundary when cse'ing instructions that by Evan Cheng · 14 years ago
  73. 5a96b3d Add bundle aware API for querying instruction properties and switch the code by Evan Cheng · 14 years ago
  74. f6fb7ed We need to verify that the machine instruction we're using as a replacement for by Bill Wendling · 14 years ago
  75. e837dea - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and by Evan Cheng · 14 years ago
  76. 5e926ac Re-revert r130877; it's apparently causing a regression on 197.parser, by Eli Friedman · 14 years ago
  77. 5f6bf5d Minor correction to r130877; fixes PR9846 and hopefully the buildbot failures. by Eli Friedman · 14 years ago
  78. baf717a Re-commit r130862 with a minor change to avoid an iterator running off the edge in some cases. by Eli Friedman · 14 years ago
  79. 24d4c99 Back out r130862; it appears to be breaking bootstrap. by Eli Friedman · 14 years ago
  80. 49cec1d Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . by Eli Friedman · 14 years ago
  81. cfea985 Fix a couple of places where changes are made but not tracked. by Evan Cheng · 14 years ago
  82. 622a11b fit in 80 cols and use MBB::isSuccessor instead of a hand rolled std::find. by Chris Lattner · 15 years ago
  83. c9df025 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. by Jakob Stoklund Olesen · 15 years ago
  84. c36b706 Do not model all INLINEASM instructions as having unmodelled side effects. by Evan Cheng · 15 years ago
  85. 53eeba5 Use a RecyclingAllocator to allocate values for MachineCSE's ScopedHashTable for by Cameron Zwarich · 15 years ago
  86. a63cde2 Teach machine cse to commute instructions. by Evan Cheng · 15 years ago
  87. 189c1ec Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857. by Evan Cheng · 15 years ago
  88. 081c34b Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which by Owen Anderson · 15 years ago
  89. 2ab36d3 Begin adding static dependence information to passes, which will allow us to by Owen Anderson · 15 years ago
  90. ce665bd Now with fewer extraneous semicolons! by Owen Anderson · 15 years ago
  91. bf4699c Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE. by Jakob Stoklund Olesen · 15 years ago
  92. c2b768f Machine CSE was forgetting to clear some data structures. by Evan Cheng · 15 years ago
  93. f437f73 Fix a potential bug that can cause miscomparison with and without debug info. by Evan Cheng · 15 years ago
  94. 6542416 Machine CSE preserves CFG. Pass manager was freeing machineloopinfo after machine cse before. by Evan Cheng · 15 years ago
  95. 90c579d Reapply r110396, with fixes to appease the Linux buildbot gods. by Owen Anderson · 15 years ago
  96. 1f74590 Revert r110396 to fix buildbots. by Owen Anderson · 15 years ago
  97. 9ccaf53 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static by Owen Anderson · 15 years ago
  98. d13db2c Fix batch of converting RegisterPass<> to INTIALIZE_PASS(). by Owen Anderson · 15 years ago
  99. 04c528a Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. by Jakob Stoklund Olesen · 15 years ago
  100. 0bc25f4 Convert EXTRACT_SUBREG to COPY when emitting machine instrs. by Jakob Stoklund Olesen · 15 years ago