commit 21f77e99412570346f497e017e92b0e5fdff8210
author Ramakant Singh <ramakant@codeaurora.org> Sun Jul 28 10:39:20 2019 +0530
committer Gerrit - the friendly Code Review server <code-review@localhost> Tue Sep 17 22:04:07 2019 -0700
tree 669738164e4e09cba993a6ab7d5d0e146324d4ee
parent 6fe8dfe472279da74ca575eccb28b80607f3533e

sdm: Get supported value for base layer staging

Change-Id: I8f1f6c8f4b2b4b20a227b616861c43df0185e523
CRs-Fixed: 2494858

libdrmutils/drm_interface.h

diff --git a/libdrmutils/drm_interface.h b/libdrmutils/drm_interface.h
index c22ed6f..316dbe4 100644
--- a/libdrmutils/drm_interface.h
+++ b/libdrmutils/drm_interface.h
@@ -510,6 +510,7 @@
   bool concurrent_writeback = false;
   uint32_t num_mnocports;
   uint32_t mnoc_bus_width;
+  bool use_baselayer_for_stage = false;
 };
 
 enum struct DRMPlaneType {

sdm/include/private/hw_info_types.h

diff --git a/sdm/include/private/hw_info_types.h b/sdm/include/private/hw_info_types.h
index f1dfc0d..3e2f74e 100644
--- a/sdm/include/private/hw_info_types.h
+++ b/sdm/include/private/hw_info_types.h
@@ -314,6 +314,7 @@
   int secure_disp_blend_stage = -1;
   uint32_t num_mnocports = 2;
   uint32_t mnoc_bus_width = 32;
+  bool use_baselayer_for_stage = false;
 };
 
 struct HWSplitInfo {

sdm/libs/core/drm/hw_info_drm.cpp

diff --git a/sdm/libs/core/drm/hw_info_drm.cpp b/sdm/libs/core/drm/hw_info_drm.cpp
index 11a05ba..f9b2d14 100644
--- a/sdm/libs/core/drm/hw_info_drm.cpp
+++ b/sdm/libs/core/drm/hw_info_drm.cpp
@@ -340,6 +340,7 @@
   // In case driver doesn't report bus width default to 256 bit bus.
   hw_resource->num_mnocports = info.num_mnocports ? info.num_mnocports : 2;
   hw_resource->mnoc_bus_width = info.mnoc_bus_width ? info.mnoc_bus_width : 32;
+  hw_resource->use_baselayer_for_stage = info.use_baselayer_for_stage;
 }
 
 void HWInfoDRM::GetHWPlanesInfo(HWResourceInfo *hw_resource) {