sdm: Add support for split bandwidth voting
Define interface to enable split bandwidth voting for MNOC, LLCC and
DRAM buses separately.
Change-Id: If8da2cb41270adbe606a1b36d9884ea21c9efd7d
CRs-Fixed: 2063498
diff --git a/libdrmutils/drm_interface.h b/libdrmutils/drm_interface.h
index 866ade6..97c8ad8 100644
--- a/libdrmutils/drm_interface.h
+++ b/libdrmutils/drm_interface.h
@@ -155,19 +155,48 @@
* uint32_t - core_clk
*/
CRTC_SET_CORE_CLK,
- /*
- * Op: Sets overall SDE core average bandwidth
+ /*
+ * Op: Sets MNOC bus average bandwidth
* Arg: uint32_t - CRTC ID
* uint32_t - core_ab
*/
CRTC_SET_CORE_AB,
/*
- * Op: Sets overall SDE core instantaneous bandwidth
+ * Op: Sets MNOC bus instantaneous bandwidth
* Arg: uint32_t - CRTC ID
* uint32_t - core_ib
*/
CRTC_SET_CORE_IB,
/*
+ * Op: Sets LLCC Bus average bandwidth
+ * Arg: uint32_t - CRTC ID
+ * uint32_t - llcc_ab
+ */
+ CRTC_SET_LLCC_AB,
+ /*
+ * Op: Sets LLCC Bus instantaneous bandwidth
+ * Arg: uint32_t - CRTC ID
+ * uint32_t - llcc_ib
+ */
+ CRTC_SET_LLCC_IB,
+ /*
+ * Op: Sets DRAM bus average bandwidth
+ * Arg: uint32_t - CRTC ID
+ * uint32_t - dram_ab
+ */
+ CRTC_SET_DRAM_AB,
+ /*
+ * Op: Sets DRAM bus instantaneous bandwidth
+ * Arg: uint32_t - CRTC ID
+ * uint32_t - dram_ib
+ */
+ CRTC_SET_DRAM_IB,
+ /*
+ * Op: Sets rotator clock for inline rotation
+ * Arg: uint32_t - CRTC ID
+ * uint32_t - rot_clk
+ */
+ CRTC_SET_ROT_CLK, /*
* Op: Returns release fence for this frame. Should be called after Commit() on
* DRMAtomicReqInterface.
* Arg: uint32_t - CRTC ID
diff --git a/sdm/include/private/hw_info_types.h b/sdm/include/private/hw_info_types.h
index 64e8454..78dbfad 100644
--- a/sdm/include/private/hw_info_types.h
+++ b/sdm/include/private/hw_info_types.h
@@ -507,13 +507,22 @@
Handle pvt_data = NULL; // Private data used by sdm extension only.
};
+struct HWQosData {
+ uint64_t core_ab_bps = 0;
+ uint64_t core_ib_bps = 0;
+ uint64_t llcc_ab_bps = 0;
+ uint64_t llcc_ib_bps = 0;
+ uint64_t dram_ab_bps = 0;
+ uint64_t dram_ib_bps = 0;
+ uint32_t clock_hz = 0;
+ uint32_t rot_clock_hz = 0;
+};
+
struct HWLayers {
HWLayersInfo info;
HWLayerConfig config[kMaxSDELayers];
float output_compression = 1.0f;
- uint64_t ab_bps = 0;
- uint64_t ib_bps = 0;
- uint32_t clock_hz = 0;
+ HWQosData qos_data = {};
HWAVRInfo hw_avr_info = {};
};
diff --git a/sdm/libs/core/drm/hw_device_drm.cpp b/sdm/libs/core/drm/hw_device_drm.cpp
index 839eaed..50e30fa 100644
--- a/sdm/libs/core/drm/hw_device_drm.cpp
+++ b/sdm/libs/core/drm/hw_device_drm.cpp
@@ -620,6 +620,7 @@
HWLayersInfo &hw_layer_info = hw_layers->info;
uint32_t hw_layer_count = UINT32(hw_layer_info.hw_layers.size());
+ HWQosData &qos_data = hw_layers->qos_data;
// TODO(user): Once destination scalar is enabled we can always send ROIs if driver allows
if (hw_panel_info_.partial_update) {
@@ -712,12 +713,20 @@
}
}
- drm_atomic_intf_->Perform(DRMOps::CRTC_SET_CORE_CLK, token_.crtc_id, hw_layers->clock_hz);
- drm_atomic_intf_->Perform(DRMOps::CRTC_SET_CORE_AB, token_.crtc_id, hw_layers->ab_bps);
- drm_atomic_intf_->Perform(DRMOps::CRTC_SET_CORE_IB, token_.crtc_id, hw_layers->ib_bps);
+ drm_atomic_intf_->Perform(DRMOps::CRTC_SET_CORE_CLK, token_.crtc_id, qos_data.clock_hz);
+ drm_atomic_intf_->Perform(DRMOps::CRTC_SET_CORE_AB, token_.crtc_id, qos_data.core_ab_bps);
+ drm_atomic_intf_->Perform(DRMOps::CRTC_SET_CORE_IB, token_.crtc_id, qos_data.core_ib_bps);
+ drm_atomic_intf_->Perform(DRMOps::CRTC_SET_LLCC_AB, token_.crtc_id, qos_data.llcc_ab_bps);
+ drm_atomic_intf_->Perform(DRMOps::CRTC_SET_LLCC_IB, token_.crtc_id, qos_data.llcc_ib_bps);
+ drm_atomic_intf_->Perform(DRMOps::CRTC_SET_DRAM_AB, token_.crtc_id, qos_data.dram_ab_bps);
+ drm_atomic_intf_->Perform(DRMOps::CRTC_SET_DRAM_IB, token_.crtc_id, qos_data.dram_ib_bps);
+ drm_atomic_intf_->Perform(DRMOps::CRTC_SET_ROT_CLK, token_.crtc_id, qos_data.rot_clock_hz);
- DLOGI_IF(kTagDriverConfig, "System: clock=%d Hz, ab=%llu Bps ib=%llu Bps", hw_layers->clock_hz,
- hw_layers->ab_bps, hw_layers->ib_bps);
+ DLOGI_IF(kTagDriverConfig, "System Clock=%d Hz, Core: AB=%llu Bps, IB=%llu Bps, " \
+ "LLCC: AB=%llu Bps, IB=%llu Bps, DRAM AB=%llu Bps, IB=%llu Bps Rot Clock=%d",
+ qos_data.clock_hz, qos_data.core_ab_bps, qos_data.core_ib_bps, qos_data.llcc_ab_bps,
+ qos_data.llcc_ib_bps, qos_data.dram_ab_bps, qos_data.dram_ib_bps,
+ qos_data.rot_clock_hz);
}
}