display: Get pipe line-width based on constraints
Driver populates the pipe line-width based on constraints
sde-limit-cases= "vig", "dma", "scale", "inline_rot";
sde-limit-ids= <0x1 0x2 0x4 0x8>;
sde-limit-values= <0x1 4096>,
<0x5 2560>,
<0x2 2880>,
<0x9 1088>;
CRs-Fixed: 2510306
Change-Id: I612db7c63fb7ee683704947284b63764711c0e7d
diff --git a/libdrmutils/drm_interface.h b/libdrmutils/drm_interface.h
index 424fd90..62db78e 100644
--- a/libdrmutils/drm_interface.h
+++ b/libdrmutils/drm_interface.h
@@ -511,6 +511,12 @@
uint32_t num_mnocports;
uint32_t mnoc_bus_width;
bool use_baselayer_for_stage = false;
+ uint32_t vig_limit_index = 0;
+ uint32_t dma_limit_index = 0;
+ uint32_t scaling_limit_index = 0;
+ uint32_t rotation_limit_index = 0;
+ uint32_t line_width_constraints_count = 0;
+ std::vector< std::pair <uint32_t, uint32_t> > line_width_limits;
};
enum struct DRMPlaneType {