diff --git a/libdrmutils/drm_interface.h b/libdrmutils/drm_interface.h
index 424fd90..62db78e 100644
--- a/libdrmutils/drm_interface.h
+++ b/libdrmutils/drm_interface.h
@@ -511,6 +511,12 @@
   uint32_t num_mnocports;
   uint32_t mnoc_bus_width;
   bool use_baselayer_for_stage = false;
+  uint32_t vig_limit_index = 0;
+  uint32_t dma_limit_index = 0;
+  uint32_t scaling_limit_index = 0;
+  uint32_t rotation_limit_index = 0;
+  uint32_t line_width_constraints_count = 0;
+  std::vector< std::pair <uint32_t, uint32_t> > line_width_limits;
 };
 
 enum struct DRMPlaneType {
diff --git a/sdm/include/private/hw_info_types.h b/sdm/include/private/hw_info_types.h
index 1c59d9d..429cb16 100644
--- a/sdm/include/private/hw_info_types.h
+++ b/sdm/include/private/hw_info_types.h
@@ -35,9 +35,12 @@
 #include <string>
 #include <bitset>
 #include <memory>
+#include <utility>
 
 namespace sdm {
 using std::string;
+using std::pair;
+using std::vector;
 
 const int kMaxSDELayers = 16;   // Maximum number of layers that can be handled by MDP5 hardware
                                 // in a given layer stack.
@@ -259,6 +262,11 @@
   kInlineRotationV1p1,
 };
 
+const int  kPipeVigLimit      = (1 << 0);
+const int  kPipeDmaLimit      = (1 << 1);
+const int  kPipeScalingLimit  = (1 << 2);
+const int  kPipeRotationLimit = (1 << 3);
+
 struct HWResourceInfo {
   uint32_t hw_version = 0;
   uint32_t hw_revision = 0;
@@ -325,6 +333,9 @@
   uint32_t num_mnocports = 2;
   uint32_t mnoc_bus_width = 32;
   bool use_baselayer_for_stage = false;
+  uint32_t line_width_constraints_count = 0;
+  vector< pair <uint32_t, uint32_t> > line_width_limits;
+  vector< pair <uint32_t, uint32_t> > line_width_constraints;
 };
 
 struct HWSplitInfo {
diff --git a/sdm/libs/core/drm/hw_info_drm.cpp b/sdm/libs/core/drm/hw_info_drm.cpp
index f9b2d14..e541298 100644
--- a/sdm/libs/core/drm/hw_info_drm.cpp
+++ b/sdm/libs/core/drm/hw_info_drm.cpp
@@ -341,6 +341,15 @@
   hw_resource->num_mnocports = info.num_mnocports ? info.num_mnocports : 2;
   hw_resource->mnoc_bus_width = info.mnoc_bus_width ? info.mnoc_bus_width : 32;
   hw_resource->use_baselayer_for_stage = info.use_baselayer_for_stage;
+  hw_resource->line_width_constraints_count = info.line_width_constraints_count;
+  if (info.line_width_constraints_count) {
+    auto &width_constraints = hw_resource->line_width_constraints;
+    hw_resource->line_width_limits = std::move(info.line_width_limits);
+    width_constraints.push_back(std::make_pair(kPipeVigLimit, info.vig_limit_index));
+    width_constraints.push_back(std::make_pair(kPipeDmaLimit, info.dma_limit_index));
+    width_constraints.push_back(std::make_pair(kPipeScalingLimit, info.scaling_limit_index));
+    width_constraints.push_back(std::make_pair(kPipeRotationLimit, info.rotation_limit_index));
+  }
 }
 
 void HWInfoDRM::GetHWPlanesInfo(HWResourceInfo *hw_resource) {