core and RF config related configurations updated
diff --git a/halimpl/pn54x/libnfc-nxp-PN553_example.conf b/halimpl/pn54x/libnfc-nxp-PN553_example.conf
index 14a2bc4..dd58776 100644
--- a/halimpl/pn54x/libnfc-nxp-PN553_example.conf
+++ b/halimpl/pn54x/libnfc-nxp-PN553_example.conf
@@ -92,41 +92,7 @@
NXP_SET_CONFIG_ALWAYS=0x00
###############################################################################
-# Core configuration extensions
-# It includes
-# Wired mode settings A0ED, A0EE
-# Tag Detector A040, A041, A043
-# Low Power mode A007
-# Clock settings A002, A003
-# PbF settings A008
-# Clock timeout settings A004
-# eSE (SVDD) PWR REQ settings A0F2
-# How eSE connected to PN553 A012
-# UICC2 bit rate A0D1
-# SWP1A interface A0D4
-# DWP intf behavior config, SVDD Load activated by default if set to 0x31 - A037
-NXP_CORE_CONF_EXTN={20, 02, 25, 09,
- A0, EC, 01, 01,
- A0, ED, 01, 00,
- A0, 5E, 01, 01,
- A0, 12, 01, 02,
- A0, 40, 01, 01,
- A0, DD, 01, 2D,
- A0, D1, 01, 02,
- A0, D4, 01, 01,
- A0, 37, 01, 35
- }
-# A0, F2, 01, 01,
-# A0, 40, 01, 01,
-# A0, 41, 01, 02,
-# A0, 43, 01, 04,
-# A0, 02, 01, 01,
-# A0, 03, 01, 11,
-# A0, 07, 01, 03,
-# A0, 08, 01, 01
-# }
-###############################################################################
# Core configuration rf field filter settings to enable set to 01 to disable set
# to 00 last bit
NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00 }