commit d401e7dbbda764022a86ec7e954c45e41593530f
author Manjunatha Venkatesh <manjunatha.venkatesh@nxp.com> Mon Nov 27 15:26:48 2017 +0530
committer nxpandroid <srikrishna.pramoda@nxp.com> Wed Nov 29 13:18:05 2017 +0530
tree fbff63421759f7b0df09c612731c0c610fd55f9d
parent 4a8764af13d2aefca513054e8d230118d5b31280

Switching NFCC clock source from XTAL to PLL is not working.

Switching NFCC clock source from XTAL to PLL is not working.

halimpl/pn54x/hal/phNxpNciHal.c

diff --git a/halimpl/pn54x/hal/phNxpNciHal.c b/halimpl/pn54x/hal/phNxpNciHal.c
index 6c24db9..7185388 100644
--- a/halimpl/pn54x/hal/phNxpNciHal.c
+++ b/halimpl/pn54x/hal/phNxpNciHal.c
@@ -3175,8 +3175,9 @@
 
 if(nfcFL.chipType == pn553) {
     static uint8_t set_clock_cmd[] = {0x20, 0x02, 0x05, 0x01, 0xA0, 0x03, 0x01, 0x08};
+    uint8_t setClkCmdLen = sizeof(set_clock_cmd);
     unsigned long  clockSource, frequency;
-    uint32_t pllSetRetryCount = 3, dpllSetRetryCount = 3;
+    uint32_t pllSetRetryCount = 3, dpllSetRetryCount = 3,setClockCmdWriteRetryCnt = 0;
     uint8_t *pCmd4PllSetting;
     uint8_t *pCmd4DpllSetting;
     uint32_t pllCmdLen, dpllCmdLen;
@@ -3280,6 +3281,12 @@
     switch(clockSource)
     {
         case CLK_SRC_PLL:
+            set_clock_cmd[setClkCmdLen -1] = 0x00;
+            while(status != NFCSTATUS_SUCCESS && setClockCmdWriteRetryCnt++ < MAX_RETRY_COUNT)
+            status = phNxpNciHal_send_ext_cmd(setClkCmdLen, set_clock_cmd);
+
+            status = NFCSTATUS_FAILED;
+
             while(status != NFCSTATUS_SUCCESS && pllSetRetryCount -- > 0)
                 status = phNxpNciHal_send_ext_cmd(pllCmdLen, pCmd4PllSetting);
 
@@ -3291,7 +3298,7 @@
             break;
 
         case CLK_SRC_XTAL:
-            status = phNxpNciHal_send_ext_cmd(sizeof(set_clock_cmd), set_clock_cmd);
+            status = phNxpNciHal_send_ext_cmd(setClkCmdLen, set_clock_cmd);
             if (status != NFCSTATUS_SUCCESS)
             {
                 NXPLOG_NCIHAL_E("XTAL clock setting failed !!");