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review.blissroms.org / platform_art / 07ec8e17c978e3bda0202693e6432b56349a5867 / . / src / compiler / codegen / x86 / codegen_x86.h
blob: 4ef186a2212b252d9cfd443d6b1d1258e2a073bf [file] [log] [blame]
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_SRC_COMPILER_CODEGEN_X86_CODEGENX86_H_
18#define ART_SRC_COMPILER_CODEGEN_X86_CODEGENX86_H_
19
20#include "../../compiler_internals.h"
Ian Rogers07ec8e12012-12-01 01:26:51 -0800[diff] [blame^]21#include "x86_lir.h"
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]22
23namespace art {
24
25class X86Codegen : public Codegen {
26 public:
27 // Required for target - codegen helpers.
28 virtual bool SmallLiteralDivide(CompilationUnit* cu, Instruction::Code dalvik_opcode,
29 RegLocation rl_src, RegLocation rl_dest, int lit);
30 virtual int LoadHelper(CompilationUnit* cu, int offset);
31 virtual LIR* LoadBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest,
32 OpSize size, int s_reg);
33 virtual LIR* LoadBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_dest_lo,
34 int r_dest_hi, int s_reg);
35 virtual LIR* LoadBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_dest, int scale,
36 OpSize size);
37 virtual LIR* LoadBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
38 int displacement, int r_dest, int r_dest_hi, OpSize size,
39 int s_reg);
40 virtual LIR* LoadConstantNoClobber(CompilationUnit* cu, int r_dest, int value);
41 virtual LIR* LoadConstantValueWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi,
42 int val_lo, int val_hi);
43 virtual void LoadPair(CompilationUnit* cu, int base, int low_reg, int high_reg);
44 virtual LIR* StoreBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_src,
45 OpSize size);
46 virtual LIR* StoreBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_src_lo,
47 int r_src_hi);
48 virtual LIR* StoreBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_src, int scale,
49 OpSize size);
50 virtual LIR* StoreBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
51 int displacement, int r_src, int r_src_hi, OpSize size,
52 int s_reg);
53 virtual void MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg);
54
55 // Required for target - register utilities.
56 virtual bool IsFpReg(int reg);
57 virtual bool SameRegType(int reg1, int reg2);
58 virtual int AllocTypedTemp(CompilationUnit* cu, bool fp_hint, int reg_class);
59 virtual int AllocTypedTempPair(CompilationUnit* cu, bool fp_hint, int reg_class);
60 virtual int S2d(int low_reg, int high_reg);
61 virtual int TargetReg(SpecialTargetRegister reg);
62 virtual RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg);
63 virtual RegLocation GetReturnAlt(CompilationUnit* cu);
64 virtual RegLocation GetReturnWideAlt(CompilationUnit* cu);
65 virtual RegLocation LocCReturn();
66 virtual RegLocation LocCReturnDouble();
67 virtual RegLocation LocCReturnFloat();
68 virtual RegLocation LocCReturnWide();
69 virtual uint32_t FpRegMask();
70 virtual uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg);
71 virtual void AdjustSpillMask(CompilationUnit* cu);
72 virtual void ClobberCalleeSave(CompilationUnit *cu);
73 virtual void FlushReg(CompilationUnit* cu, int reg);
74 virtual void FlushRegWide(CompilationUnit* cu, int reg1, int reg2);
75 virtual void FreeCallTemps(CompilationUnit* cu);
76 virtual void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free);
77 virtual void LockCallTemps(CompilationUnit* cu);
78 virtual void MarkPreservedSingle(CompilationUnit* cu, int v_reg, int reg);
79 virtual void CompilerInitializeRegAlloc(CompilationUnit* cu);
80
81 // Required for target - miscellaneous.
82 virtual AssemblerStatus AssembleInstructions(CompilationUnit* cu, uintptr_t start_addr);
83 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
84 virtual void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir);
85 virtual const char* GetTargetInstFmt(int opcode);
86 virtual const char* GetTargetInstName(int opcode);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]87 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
88 virtual uint64_t GetPCUseDefEncoding();
89 virtual uint64_t GetTargetInstFlags(int opcode);
90 virtual int GetInsnSize(LIR* lir);
91 virtual bool IsUnconditionalBranch(LIR* lir);
92
93 // Required for target - Dalvik-level generators.
94 virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
95 RegLocation rl_src2);
96 virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
97 RegLocation rl_src2);
98 virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
99 RegLocation rl_dest, RegLocation rl_src1,
100 RegLocation rl_src2);
101 virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
102 RegLocation rl_src1, RegLocation rl_src2);
103 virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
104 RegLocation rl_src1, RegLocation rl_src2);
105 virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
106 RegLocation rl_src);
107 virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier);
108 virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min);
109 virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info);
110 virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
111 virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
112 RegLocation rl_src2);
113 virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
114 RegLocation rl_src2);
115 virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
116 RegLocation rl_src2);
117 virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
118 int offset, ThrowKind kind);
119 virtual RegLocation GenDivRem(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int reg_hi,
120 bool is_div);
121 virtual RegLocation GenDivRemLit(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int lit,
122 bool is_div);
123 virtual void GenCmpLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
124 RegLocation rl_src2);
125 virtual void GenDivZeroCheck(CompilationUnit* cu, int reg_lo, int reg_hi);
126 virtual void GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs,
127 RegLocation rl_method);
128 virtual void GenExitSequence(CompilationUnit* cu);
129 virtual void GenFillArrayData(CompilationUnit* cu, uint32_t table_offset,
130 RegLocation rl_src);
131 virtual void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
132 bool is_double);
133 virtual void GenFusedLongCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir);
134 virtual void GenMemBarrier(CompilationUnit* cu, MemBarrierKind barrier_kind);
135 virtual void GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src);
136 virtual void GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src);
137 virtual void GenMultiplyByTwoBitMultiplier(CompilationUnit* cu, RegLocation rl_src,
138 RegLocation rl_result, int lit, int first_bit,
139 int second_bit);
140 virtual void GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
141 virtual void GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
142 virtual void GenPackedSwitch(CompilationUnit* cu, uint32_t table_offset,
143 RegLocation rl_src);
144 virtual void GenSparseSwitch(CompilationUnit* cu, uint32_t table_offset,
145 RegLocation rl_src);
146 virtual void GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
147 SpecialCaseHandler special_case);
148
149 // Single operation generators.
150 virtual LIR* OpUnconditionalBranch(CompilationUnit* cu, LIR* target);
151 virtual LIR* OpCmpBranch(CompilationUnit* cu, ConditionCode cond, int src1, int src2,
152 LIR* target);
153 virtual LIR* OpCmpImmBranch(CompilationUnit* cu, ConditionCode cond, int reg, int check_value,
154 LIR* target);
155 virtual LIR* OpCondBranch(CompilationUnit* cu, ConditionCode cc, LIR* target);
156 virtual LIR* OpDecAndBranch(CompilationUnit* cu, ConditionCode c_code, int reg,
157 LIR* target);
158 virtual LIR* OpFpRegCopy(CompilationUnit* cu, int r_dest, int r_src);
159 virtual LIR* OpIT(CompilationUnit* cu, ConditionCode cond, const char* guide);
160 virtual LIR* OpMem(CompilationUnit* cu, OpKind op, int rBase, int disp);
161 virtual LIR* OpPcRelLoad(CompilationUnit* cu, int reg, LIR* target);
162 virtual LIR* OpReg(CompilationUnit* cu, OpKind op, int r_dest_src);
163 virtual LIR* OpRegCopy(CompilationUnit* cu, int r_dest, int r_src);
164 virtual LIR* OpRegCopyNoInsert(CompilationUnit* cu, int r_dest, int r_src);
165 virtual LIR* OpRegImm(CompilationUnit* cu, OpKind op, int r_dest_src1, int value);
166 virtual LIR* OpRegMem(CompilationUnit* cu, OpKind op, int r_dest, int rBase, int offset);
167 virtual LIR* OpRegReg(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2);
168 virtual LIR* OpRegRegImm(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int value);
169 virtual LIR* OpRegRegReg(CompilationUnit* cu, OpKind op, int r_dest, int r_src1,
170 int r_src2);
171 virtual LIR* OpTestSuspend(CompilationUnit* cu, LIR* target);
172 virtual LIR* OpThreadMem(CompilationUnit* cu, OpKind op, int thread_offset);
173 virtual LIR* OpVldm(CompilationUnit* cu, int rBase, int count);
174 virtual LIR* OpVstm(CompilationUnit* cu, int rBase, int count);
175 virtual void OpLea(CompilationUnit* cu, int rBase, int reg1, int reg2, int scale,
176 int offset);
177 virtual void OpRegCopyWide(CompilationUnit* cu, int dest_lo, int dest_hi, int src_lo,
178 int src_hi);
179 virtual void OpTlsCmp(CompilationUnit* cu, int offset, int val);
180
181 void OpRegThreadMem(CompilationUnit* cu, OpKind op, int r_dest, int thread_offset);
182 void SpillCoreRegs(CompilationUnit* cu);
183 void UnSpillCoreRegs(CompilationUnit* cu);
184 static const X86EncodingMap EncodingMap[kX86Last];
185};
186
187} // namespace art
188
189#endif // ART_SRC_COMPILER_CODEGEN_X86_CODEGENX86_H_