Gitiles
Code Review Sign In
review.blissroms.org / platform_art / 11b63d13f0a3be0f74390b66b58614a37f9aa6c1 / . / compiler / dex / quick / x86 / codegen_x86.h
blob: 478654d0b41a8f05a067322e82344c9340bbdfc7 [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700[diff] [blame]17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]19
20#include "dex/compiler_internals.h"
21#include "x86_lir.h"
22
23namespace art {
24
25class X86Mir2Lir : public Mir2Lir {
26 public:
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]27 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29 // Required for target - codegen helpers.
buzbee11b63d12013-08-27 07:34:17 -0700[diff] [blame^]30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]31 RegLocation rl_dest, int lit);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]32 int LoadHelper(ThreadOffset offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
35 int s_reg);
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
38 int r_dest, int r_dest_hi, OpSize size, int s_reg);
39 LIR* LoadConstantNoClobber(int r_dest, int value);
40 LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
45 int r_src, int r_src_hi, OpSize size, int s_reg);
46 void MarkGCCard(int val_reg, int tgt_addr_reg);
47
48 // Required for target - register utilities.
49 bool IsFpReg(int reg);
50 bool SameRegType(int reg1, int reg2);
51 int AllocTypedTemp(bool fp_hint, int reg_class);
52 int AllocTypedTempPair(bool fp_hint, int reg_class);
53 int S2d(int low_reg, int high_reg);
54 int TargetReg(SpecialTargetRegister reg);
55 RegisterInfo* GetRegInfo(int reg);
56 RegLocation GetReturnAlt();
57 RegLocation GetReturnWideAlt();
58 RegLocation LocCReturn();
59 RegLocation LocCReturnDouble();
60 RegLocation LocCReturnFloat();
61 RegLocation LocCReturnWide();
62 uint32_t FpRegMask();
63 uint64_t GetRegMaskCommon(int reg);
64 void AdjustSpillMask();
65 void ClobberCalleeSave();
66 void FlushReg(int reg);
67 void FlushRegWide(int reg1, int reg2);
68 void FreeCallTemps();
69 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
70 void LockCallTemps();
71 void MarkPreservedSingle(int v_reg, int reg);
72 void CompilerInitializeRegAlloc();
73
74 // Required for target - miscellaneous.
75 AssemblerStatus AssembleInstructions(uintptr_t start_addr);
76 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
77 void SetupTargetResourceMasks(LIR* lir);
78 const char* GetTargetInstFmt(int opcode);
79 const char* GetTargetInstName(int opcode);
80 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
81 uint64_t GetPCUseDefEncoding();
82 uint64_t GetTargetInstFlags(int opcode);
83 int GetInsnSize(LIR* lir);
84 bool IsUnconditionalBranch(LIR* lir);
85
86 // Required for target - Dalvik-level generators.
87 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
88 RegLocation rl_src1, RegLocation rl_src2);
89 void GenArrayObjPut(int opt_flags, RegLocation rl_array,
90 RegLocation rl_index, RegLocation rl_src, int scale);
91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
92 RegLocation rl_index, RegLocation rl_dest, int scale);
93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
94 RegLocation rl_index, RegLocation rl_src, int scale);
95 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
96 RegLocation rl_src1, RegLocation rl_shift);
97 void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
98 void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
99 void GenAndLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
100 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
101 RegLocation rl_src1, RegLocation rl_src2);
102 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
103 RegLocation rl_src1, RegLocation rl_src2);
104 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105 RegLocation rl_src2);
106 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
107 bool GenInlinedCas32(CallInfo* info, bool need_write_barrier);
108 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
109 bool GenInlinedSqrt(CallInfo* info);
110 void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
111 void GenOrLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
112 void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
113 void GenXorLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
114 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
115 ThrowKind kind);
116 RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
117 RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
118 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
119 void GenDivZeroCheck(int reg_lo, int reg_hi);
120 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
121 void GenExitSequence();
122 void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
123 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
124 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
125 void GenSelect(BasicBlock* bb, MIR* mir);
126 void GenMemBarrier(MemBarrierKind barrier_kind);
127 void GenMonitorEnter(int opt_flags, RegLocation rl_src);
128 void GenMonitorExit(int opt_flags, RegLocation rl_src);
129 void GenMoveException(RegLocation rl_dest);
130 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result,
131 int lit, int first_bit, int second_bit);
132 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
133 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
134 void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
135 void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
136 void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
137
138 // Single operation generators.
139 LIR* OpUnconditionalBranch(LIR* target);
140 LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
141 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
142 LIR* OpCondBranch(ConditionCode cc, LIR* target);
143 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
144 LIR* OpFpRegCopy(int r_dest, int r_src);
145 LIR* OpIT(ConditionCode cond, const char* guide);
146 LIR* OpMem(OpKind op, int rBase, int disp);
147 LIR* OpPcRelLoad(int reg, LIR* target);
148 LIR* OpReg(OpKind op, int r_dest_src);
149 LIR* OpRegCopy(int r_dest, int r_src);
150 LIR* OpRegCopyNoInsert(int r_dest, int r_src);
151 LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
152 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
153 LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
154 LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
155 LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
156 LIR* OpTestSuspend(LIR* target);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]157 LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]158 LIR* OpVldm(int rBase, int count);
159 LIR* OpVstm(int rBase, int count);
160 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
161 void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]162 void OpTlsCmp(ThreadOffset offset, int val);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]163
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]164 void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]165 void SpillCoreRegs();
166 void UnSpillCoreRegs();
167 static const X86EncodingMap EncodingMap[kX86Last];
168 bool InexpensiveConstantInt(int32_t value);
169 bool InexpensiveConstantFloat(int32_t value);
170 bool InexpensiveConstantLong(int64_t value);
171 bool InexpensiveConstantDouble(int64_t value);
172
173 private:
174 void EmitDisp(int base, int disp);
175 void EmitOpReg(const X86EncodingMap* entry, uint8_t reg);
176 void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp);
177 void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg);
178 void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp);
179 void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,
180 int scale, int disp);
181 void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,
182 uint8_t reg);
183 void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp);
184 void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2);
185 void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
186 void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
187 void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm);
188 void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
189 void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
190 void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl);
191 void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition);
192 void EmitJmp(const X86EncodingMap* entry, int rel);
193 void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc);
194 void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp);
195 void EmitCallThread(const X86EncodingMap* entry, int disp);
196 void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index,
197 int scale, int table_or_disp);
198 void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset);
199 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir);
200};
201
202} // namespace art
203
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700[diff] [blame]204#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_