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review.blissroms.org / platform_art / 15bf9804820b73765899e4b3e0d8a1fa15e0dbd3 / . / src / compiler / Dataflow.cc
blob: 8196ce9ebd9611d3595c73f2797a334583b637a0 [file] [log] [blame]
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "Dalvik.h"
18#include "Dataflow.h"
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]19
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]20namespace art {
21
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]22/*
23 * Main table containing data flow attributes for each bytecode. The
24 * first kNumPackedOpcodes entries are for Dalvik bytecode
25 * instructions, where extended opcode at the MIR level are appended
26 * afterwards.
27 *
28 * TODO - many optimization flags are incomplete - they will only limit the
29 * scope of optimizations but will not cause mis-optimizations.
30 */
buzbeeba938cb2012-02-03 14:47:55 -0800[diff] [blame]31const int oatDataFlowAttributes[kMirOpLast] = {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]32 // 00 NOP
33 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]34
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]35 // 01 MOVE vA, vB
36 DF_DA | DF_UB | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]37
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]38 // 02 MOVE_FROM16 vAA, vBBBB
39 DF_DA | DF_UB | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]40
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]41 // 03 MOVE_16 vAAAA, vBBBB
42 DF_DA | DF_UB | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]43
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]44 // 04 MOVE_WIDE vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]45 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]46
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]47 // 05 MOVE_WIDE_FROM16 vAA, vBBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]48 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]49
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]50 // 06 MOVE_WIDE_16 vAAAA, vBBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]51 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]52
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]53 // 07 MOVE_OBJECT vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]54 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]55
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]56 // 08 MOVE_OBJECT_FROM16 vAA, vBBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]57 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]58
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]59 // 09 MOVE_OBJECT_16 vAAAA, vBBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]60 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]61
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]62 // 0A MOVE_RESULT vAA
63 DF_DA,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]64
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]65 // 0B MOVE_RESULT_WIDE vAA
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]66 DF_DA | DF_A_WIDE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]67
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]68 // 0C MOVE_RESULT_OBJECT vAA
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]69 DF_DA | DF_REF_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]70
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]71 // 0D MOVE_EXCEPTION vAA
72 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]73
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]74 // 0E RETURN_VOID
75 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]76
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]77 // 0F RETURN vAA
78 DF_UA,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]79
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]80 // 10 RETURN_WIDE vAA
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]81 DF_UA | DF_A_WIDE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]82
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]83 // 11 RETURN_OBJECT vAA
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]84 DF_UA | DF_REF_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]85
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]86 // 12 CONST_4 vA, #+B
87 DF_DA | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]88
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]89 // 13 CONST_16 vAA, #+BBBB
90 DF_DA | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]91
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]92 // 14 CONST vAA, #+BBBBBBBB
93 DF_DA | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]94
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]95 // 15 CONST_HIGH16 VAA, #+BBBB0000
96 DF_DA | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]97
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]98 // 16 CONST_WIDE_16 vAA, #+BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]99 DF_DA | DF_A_WIDE | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]100
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]101 // 17 CONST_WIDE_32 vAA, #+BBBBBBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]102 DF_DA | DF_A_WIDE | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]103
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]104 // 18 CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]105 DF_DA | DF_A_WIDE | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]106
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]107 // 19 CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]108 DF_DA | DF_A_WIDE | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]109
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]110 // 1A CONST_STRING vAA, string@BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]111 DF_DA | DF_REF_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]112
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]113 // 1B CONST_STRING_JUMBO vAA, string@BBBBBBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]114 DF_DA | DF_REF_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]115
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]116 // 1C CONST_CLASS vAA, type@BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]117 DF_DA | DF_REF_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]118
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]119 // 1D MONITOR_ENTER vAA
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]120 DF_UA | DF_NULL_CHK_0 | DF_REF_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]121
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]122 // 1E MONITOR_EXIT vAA
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]123 DF_UA | DF_NULL_CHK_0 | DF_REF_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]124
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]125 // 1F CHK_CAST vAA, type@BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]126 DF_UA | DF_REF_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]127
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]128 // 20 INSTANCE_OF vA, vB, type@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]129 DF_DA | DF_UB | DF_CORE_A | DF_REF_B | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]130
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]131 // 21 ARRAY_LENGTH vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]132 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]133
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]134 // 22 NEW_INSTANCE vAA, type@BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]135 DF_DA | DF_NON_NULL_DST | DF_REF_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]136
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]137 // 23 NEW_ARRAY vA, vB, type@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]138 DF_DA | DF_UB | DF_NON_NULL_DST | DF_REF_A | DF_CORE_B | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]139
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]140 // 24 FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
141 DF_FORMAT_35C | DF_NON_NULL_RET | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]142
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]143 // 25 FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB
144 DF_FORMAT_3RC | DF_NON_NULL_RET | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]145
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]146 // 26 FILL_ARRAY_DATA vAA, +BBBBBBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]147 DF_UA | DF_REF_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]148
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]149 // 27 THROW vAA
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]150 DF_UA | DF_REF_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]151
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]152 // 28 GOTO
153 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]154
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]155 // 29 GOTO_16
156 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]157
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]158 // 2A GOTO_32
159 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]160
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]161 // 2B PACKED_SWITCH vAA, +BBBBBBBB
162 DF_UA,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]163
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]164 // 2C SPARSE_SWITCH vAA, +BBBBBBBB
165 DF_UA,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]166
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]167 // 2D CMPL_FLOAT vAA, vBB, vCC
168 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]169
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]170 // 2E CMPG_FLOAT vAA, vBB, vCC
171 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]172
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]173 // 2F CMPL_DOUBLE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]174 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]175
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]176 // 30 CMPG_DOUBLE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]177 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]178
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]179 // 31 CMP_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]180 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]181
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]182 // 32 IF_EQ vA, vB, +CCCC
183 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]184
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]185 // 33 IF_NE vA, vB, +CCCC
186 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]187
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]188 // 34 IF_LT vA, vB, +CCCC
189 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]190
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]191 // 35 IF_GE vA, vB, +CCCC
192 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]193
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]194 // 36 IF_GT vA, vB, +CCCC
195 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]196
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]197 // 37 IF_LE vA, vB, +CCCC
198 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]199
200
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]201 // 38 IF_EQZ vAA, +BBBB
202 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]203
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]204 // 39 IF_NEZ vAA, +BBBB
205 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]206
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]207 // 3A IF_LTZ vAA, +BBBB
208 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]209
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]210 // 3B IF_GEZ vAA, +BBBB
211 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]212
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]213 // 3C IF_GTZ vAA, +BBBB
214 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]215
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]216 // 3D IF_LEZ vAA, +BBBB
217 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]218
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]219 // 3E UNUSED_3E
220 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]221
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]222 // 3F UNUSED_3F
223 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]224
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]225 // 40 UNUSED_40
226 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]227
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]228 // 41 UNUSED_41
229 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]230
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]231 // 42 UNUSED_42
232 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]233
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]234 // 43 UNUSED_43
235 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]236
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]237 // 44 AGET vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]238 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]239
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]240 // 45 AGET_WIDE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]241 DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]242
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]243 // 46 AGET_OBJECT vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]244 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_A | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]245
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]246 // 47 AGET_BOOLEAN vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]247 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]248
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]249 // 48 AGET_BYTE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]250 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]251
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]252 // 49 AGET_CHAR vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]253 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]254
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]255 // 4A AGET_SHORT vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]256 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]257
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]258 // 4B APUT vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]259 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]260
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]261 // 4C APUT_WIDE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]262 DF_UA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_2 | DF_RANGE_CHK_3 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]263
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]264 // 4D APUT_OBJECT vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]265 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_A | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]266
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]267 // 4E APUT_BOOLEAN vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]268 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]269
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]270 // 4F APUT_BYTE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]271 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]272
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]273 // 50 APUT_CHAR vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]274 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]275
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]276 // 51 APUT_SHORT vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]277 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]278
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]279 // 52 IGET vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]280 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]281
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]282 // 53 IGET_WIDE vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]283 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]284
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]285 // 54 IGET_OBJECT vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]286 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_A | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]287
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]288 // 55 IGET_BOOLEAN vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]289 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]290
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]291 // 56 IGET_BYTE vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]292 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]293
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]294 // 57 IGET_CHAR vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]295 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]296
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]297 // 58 IGET_SHORT vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]298 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]299
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]300 // 59 IPUT vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]301 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]302
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]303 // 5A IPUT_WIDE vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]304 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]305
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]306 // 5B IPUT_OBJECT vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]307 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_A | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]308
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]309 // 5C IPUT_BOOLEAN vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]310 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]311
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]312 // 5D IPUT_BYTE vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]313 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]314
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]315 // 5E IPUT_CHAR vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]316 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]317
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]318 // 5F IPUT_SHORT vA, vB, field@CCCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]319 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]320
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]321 // 60 SGET vAA, field@BBBB
322 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]323
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]324 // 61 SGET_WIDE vAA, field@BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]325 DF_DA | DF_A_WIDE | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]326
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]327 // 62 SGET_OBJECT vAA, field@BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]328 DF_DA | DF_REF_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]329
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]330 // 63 SGET_BOOLEAN vAA, field@BBBB
331 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]332
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]333 // 64 SGET_BYTE vAA, field@BBBB
334 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]335
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]336 // 65 SGET_CHAR vAA, field@BBBB
337 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]338
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]339 // 66 SGET_SHORT vAA, field@BBBB
340 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]341
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]342 // 67 SPUT vAA, field@BBBB
343 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]344
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]345 // 68 SPUT_WIDE vAA, field@BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]346 DF_UA | DF_A_WIDE | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]347
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]348 // 69 SPUT_OBJECT vAA, field@BBBB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]349 DF_UA | DF_REF_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]350
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]351 // 6A SPUT_BOOLEAN vAA, field@BBBB
352 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]353
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]354 // 6B SPUT_BYTE vAA, field@BBBB
355 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]356
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]357 // 6C SPUT_CHAR vAA, field@BBBB
358 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]359
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]360 // 6D SPUT_SHORT vAA, field@BBBB
361 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]362
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]363 // 6E INVOKE_VIRTUAL {vD, vE, vF, vG, vA}
364 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]365
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]366 // 6F INVOKE_SUPER {vD, vE, vF, vG, vA}
367 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]368
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]369 // 70 INVOKE_DIRECT {vD, vE, vF, vG, vA}
370 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]371
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]372 // 71 INVOKE_STATIC {vD, vE, vF, vG, vA}
373 DF_FORMAT_35C | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]374
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]375 // 72 INVOKE_INTERFACE {vD, vE, vF, vG, vA}
376 DF_FORMAT_35C | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]377
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]378 // 73 UNUSED_73
379 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]380
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]381 // 74 INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN}
382 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]383
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]384 // 75 INVOKE_SUPER_RANGE {vCCCC .. vNNNN}
385 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]386
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]387 // 76 INVOKE_DIRECT_RANGE {vCCCC .. vNNNN}
388 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]389
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]390 // 77 INVOKE_STATIC_RANGE {vCCCC .. vNNNN}
391 DF_FORMAT_3RC | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]392
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]393 // 78 INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN}
394 DF_FORMAT_3RC | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]395
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]396 // 79 UNUSED_79
397 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]398
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]399 // 7A UNUSED_7A
400 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]401
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]402 // 7B NEG_INT vA, vB
403 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]404
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]405 // 7C NOT_INT vA, vB
406 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]407
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]408 // 7D NEG_LONG vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]409 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]410
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]411 // 7E NOT_LONG vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]412 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]413
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]414 // 7F NEG_FLOAT vA, vB
415 DF_DA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]416
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]417 // 80 NEG_DOUBLE vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]418 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]419
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]420 // 81 INT_TO_LONG vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]421 DF_DA | DF_A_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]422
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]423 // 82 INT_TO_FLOAT vA, vB
424 DF_DA | DF_UB | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]425
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]426 // 83 INT_TO_DOUBLE vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]427 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]428
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]429 // 84 LONG_TO_INT vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]430 DF_DA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]431
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]432 // 85 LONG_TO_FLOAT vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]433 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]434
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]435 // 86 LONG_TO_DOUBLE vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]436 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]437
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]438 // 87 FLOAT_TO_INT vA, vB
439 DF_DA | DF_UB | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]440
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]441 // 88 FLOAT_TO_LONG vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]442 DF_DA | DF_A_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]443
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]444 // 89 FLOAT_TO_DOUBLE vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]445 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]446
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]447 // 8A DOUBLE_TO_INT vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]448 DF_DA | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]449
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]450 // 8B DOUBLE_TO_LONG vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]451 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]452
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]453 // 8C DOUBLE_TO_FLOAT vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]454 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]455
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]456 // 8D INT_TO_BYTE vA, vB
457 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]458
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]459 // 8E INT_TO_CHAR vA, vB
460 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]461
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]462 // 8F INT_TO_SHORT vA, vB
463 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]464
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]465 // 90 ADD_INT vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]466 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]467
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]468 // 91 SUB_INT vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]469 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]470
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]471 // 92 MUL_INT vAA, vBB, vCC
472 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]473
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]474 // 93 DIV_INT vAA, vBB, vCC
475 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]476
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]477 // 94 REM_INT vAA, vBB, vCC
478 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]479
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]480 // 95 AND_INT vAA, vBB, vCC
481 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]482
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]483 // 96 OR_INT vAA, vBB, vCC
484 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]485
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]486 // 97 XOR_INT vAA, vBB, vCC
487 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]488
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]489 // 98 SHL_INT vAA, vBB, vCC
490 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]491
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]492 // 99 SHR_INT vAA, vBB, vCC
493 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]494
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]495 // 9A USHR_INT vAA, vBB, vCC
496 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]497
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]498 // 9B ADD_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]499 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]500
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]501 // 9C SUB_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]502 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]503
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]504 // 9D MUL_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]505 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]506
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]507 // 9E DIV_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]508 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]509
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]510 // 9F REM_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]511 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]512
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]513 // A0 AND_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]514 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]515
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]516 // A1 OR_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]517 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]518
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]519 // A2 XOR_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]520 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]521
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]522 // A3 SHL_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]523 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]524
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]525 // A4 SHR_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]526 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]527
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]528 // A5 USHR_LONG vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]529 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]530
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]531 // A6 ADD_FLOAT vAA, vBB, vCC
532 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]533
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]534 // A7 SUB_FLOAT vAA, vBB, vCC
535 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]536
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]537 // A8 MUL_FLOAT vAA, vBB, vCC
538 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]539
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]540 // A9 DIV_FLOAT vAA, vBB, vCC
541 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]542
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]543 // AA REM_FLOAT vAA, vBB, vCC
544 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]545
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]546 // AB ADD_DOUBLE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]547 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]548
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]549 // AC SUB_DOUBLE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]550 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]551
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]552 // AD MUL_DOUBLE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]553 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]554
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]555 // AE DIV_DOUBLE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]556 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]557
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]558 // AF REM_DOUBLE vAA, vBB, vCC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]559 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]560
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]561 // B0 ADD_INT_2ADDR vA, vB
562 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]563
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]564 // B1 SUB_INT_2ADDR vA, vB
565 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]566
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]567 // B2 MUL_INT_2ADDR vA, vB
568 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]569
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]570 // B3 DIV_INT_2ADDR vA, vB
571 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]572
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]573 // B4 REM_INT_2ADDR vA, vB
574 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]575
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]576 // B5 AND_INT_2ADDR vA, vB
577 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]578
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]579 // B6 OR_INT_2ADDR vA, vB
580 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]581
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]582 // B7 XOR_INT_2ADDR vA, vB
583 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]584
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]585 // B8 SHL_INT_2ADDR vA, vB
586 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]587
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]588 // B9 SHR_INT_2ADDR vA, vB
589 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]590
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]591 // BA USHR_INT_2ADDR vA, vB
592 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]593
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]594 // BB ADD_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]595 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]596
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]597 // BC SUB_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]598 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]599
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]600 // BD MUL_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]601 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]602
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]603 // BE DIV_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]604 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]605
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]606 // BF REM_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]607 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]608
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]609 // C0 AND_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]610 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]611
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]612 // C1 OR_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]613 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]614
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]615 // C2 XOR_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]616 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]617
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]618 // C3 SHL_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]619 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]620
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]621 // C4 SHR_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]622 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]623
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]624 // C5 USHR_LONG_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]625 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]626
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]627 // C6 ADD_FLOAT_2ADDR vA, vB
628 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]629
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]630 // C7 SUB_FLOAT_2ADDR vA, vB
631 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]632
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]633 // C8 MUL_FLOAT_2ADDR vA, vB
634 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]635
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]636 // C9 DIV_FLOAT_2ADDR vA, vB
637 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]638
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]639 // CA REM_FLOAT_2ADDR vA, vB
640 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]641
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]642 // CB ADD_DOUBLE_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]643 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]644
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]645 // CC SUB_DOUBLE_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]646 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]647
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]648 // CD MUL_DOUBLE_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]649 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]650
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]651 // CE DIV_DOUBLE_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]652 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]653
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]654 // CF REM_DOUBLE_2ADDR vA, vB
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]655 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]656
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]657 // D0 ADD_INT_LIT16 vA, vB, #+CCCC
658 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]659
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]660 // D1 RSUB_INT vA, vB, #+CCCC
661 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]662
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]663 // D2 MUL_INT_LIT16 vA, vB, #+CCCC
664 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]665
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]666 // D3 DIV_INT_LIT16 vA, vB, #+CCCC
667 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]668
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]669 // D4 REM_INT_LIT16 vA, vB, #+CCCC
670 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]671
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]672 // D5 AND_INT_LIT16 vA, vB, #+CCCC
673 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]674
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]675 // D6 OR_INT_LIT16 vA, vB, #+CCCC
676 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]677
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]678 // D7 XOR_INT_LIT16 vA, vB, #+CCCC
679 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]680
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]681 // D8 ADD_INT_LIT8 vAA, vBB, #+CC
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]682 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]683
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]684 // D9 RSUB_INT_LIT8 vAA, vBB, #+CC
685 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]686
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]687 // DA MUL_INT_LIT8 vAA, vBB, #+CC
688 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]689
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]690 // DB DIV_INT_LIT8 vAA, vBB, #+CC
691 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]692
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]693 // DC REM_INT_LIT8 vAA, vBB, #+CC
694 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]695
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]696 // DD AND_INT_LIT8 vAA, vBB, #+CC
697 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]698
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]699 // DE OR_INT_LIT8 vAA, vBB, #+CC
700 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]701
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]702 // DF XOR_INT_LIT8 vAA, vBB, #+CC
703 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]704
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]705 // E0 SHL_INT_LIT8 vAA, vBB, #+CC
706 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]707
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]708 // E1 SHR_INT_LIT8 vAA, vBB, #+CC
709 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]710
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]711 // E2 USHR_INT_LIT8 vAA, vBB, #+CC
712 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]713
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]714 // E3 IGET_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]715 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]716
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]717 // E4 IPUT_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]718 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]719
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]720 // E5 SGET_VOLATILE
721 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]722
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]723 // E6 SPUT_VOLATILE
724 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]725
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]726 // E7 IGET_OBJECT_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]727 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_A | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]728
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]729 // E8 IGET_WIDE_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]730 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]731
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]732 // E9 IPUT_WIDE_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]733 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2 | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]734
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]735 // EA SGET_WIDE_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]736 DF_DA | DF_A_WIDE | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]737
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]738 // EB SPUT_WIDE_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]739 DF_UA | DF_A_WIDE | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]740
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]741 // EC BREAKPOINT
742 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]743
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]744 // ED THROW_VERIFICATION_ERROR
745 DF_NOP | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]746
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]747 // EE EXECUTE_INLINE
748 DF_FORMAT_35C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]749
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]750 // EF EXECUTE_INLINE_RANGE
751 DF_FORMAT_3RC,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]752
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]753 // F0 INVOKE_OBJECT_INIT_RANGE
754 DF_NOP | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]755
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]756 // F1 RETURN_VOID_BARRIER
757 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]758
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]759 // F2 IGET_QUICK
760 DF_DA | DF_UB | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]761
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]762 // F3 IGET_WIDE_QUICK
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]763 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]764
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]765 // F4 IGET_OBJECT_QUICK
766 DF_DA | DF_UB | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]767
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]768 // F5 IPUT_QUICK
769 DF_UA | DF_UB | DF_NULL_CHK_1,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]770
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]771 // F6 IPUT_WIDE_QUICK
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]772 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]773
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]774 // F7 IPUT_OBJECT_QUICK
775 DF_UA | DF_UB | DF_NULL_CHK_1,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]776
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]777 // F8 INVOKE_VIRTUAL_QUICK
778 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]779
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]780 // F9 INVOKE_VIRTUAL_QUICK_RANGE
781 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]782
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]783 // FA INVOKE_SUPER_QUICK
784 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]785
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]786 // FB INVOKE_SUPER_QUICK_RANGE
787 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]788
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]789 // FC IPUT_OBJECT_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]790 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_A | DF_REF_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]791
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]792 // FD SGET_OBJECT_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]793 DF_DA | DF_REF_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]794
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]795 // FE SPUT_OBJECT_VOLATILE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]796 DF_UA | DF_REF_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]797
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]798 // FF UNUSED_FF
799 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]800
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]801 // Beginning of extended MIR opcodes
802 // 100 MIR_PHI
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]803 DF_DA | DF_NULL_TRANSFER_N,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]804
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]805 // 101 MIR_COPY
806 DF_DA | DF_UB | DF_IS_MOVE,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]807
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]808 // 102 MIR_FUSED_CMPL_FLOAT
809 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]810
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]811 // 103 MIR_FUSED_CMPG_FLOAT
812 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]813
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]814 // 104 MIR_FUSED_CMPL_DOUBLE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]815 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]816
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]817 // 105 MIR_FUSED_CMPG_DOUBLE
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]818 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]819
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]820 // 106 MIR_FUSED_CMP_LONG
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]821 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]822
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]823 // 107 MIR_NOP
824 DF_NOP,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]825
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]826 // 108 MIR_NULL_RANGE_UP_CHECK
827 0,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]828
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]829 // 109 MIR_NULL_RANGE_DOWN_CHECK
830 0,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]831
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]832 // 110 MIR_LOWER_BOUND
833 0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]834};
835
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]836/* Return the base virtual register for a SSA name */
837int SRegToVReg(const CompilationUnit* cUnit, int ssaReg)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]838{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]839 DCHECK_LT(ssaReg, (int)cUnit->ssaBaseVRegs->numUsed);
840 return GET_ELEM_N(cUnit->ssaBaseVRegs, int, ssaReg);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]841}
842
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]843int SRegToSubscript(const CompilationUnit* cUnit, int ssaReg)
844{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]845 DCHECK(ssaReg < (int)cUnit->ssaSubscripts->numUsed);
846 return GET_ELEM_N(cUnit->ssaSubscripts, int, ssaReg);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]847}
848
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]849int getSSAUseCount(CompilationUnit* cUnit, int sReg)
850{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]851 DCHECK(sReg < (int)cUnit->rawUseCounts.numUsed);
852 return cUnit->rawUseCounts.elemList[sReg];
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]853}
854
855
buzbeeba938cb2012-02-03 14:47:55 -0800[diff] [blame]856char* oatGetDalvikDisassembly(CompilationUnit* cUnit,
Elliott Hughesadb8c672012-03-06 16:49:32 -0800[diff] [blame]857 const DecodedInstruction& insn, const char* note)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]858{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]859 char buffer[256];
860 Instruction::Code opcode = insn.opcode;
861 int dfAttributes = oatDataFlowAttributes[opcode];
862 int flags;
863 char* ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]864
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]865 buffer[0] = 0;
866 if ((int)opcode >= (int)kMirOpFirst) {
867 if ((int)opcode == (int)kMirOpPhi) {
868 strcpy(buffer, "PHI");
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]869 } else {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]870 sprintf(buffer, "Opcode %#x", opcode);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]871 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]872 flags = 0;
873 } else {
874 strcpy(buffer, Instruction::Name(opcode));
875 flags = Instruction::Flags(opcode);
876 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]877
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]878 if (note)
879 strcat(buffer, note);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]880
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]881 /* For branches, decode the instructions to print out the branch targets */
882 if (flags & Instruction::kBranch) {
883 Instruction::Format dalvikFormat = Instruction::FormatOf(insn.opcode);
884 int offset = 0;
885 switch (dalvikFormat) {
886 case Instruction::k21t:
887 snprintf(buffer + strlen(buffer), 256, " v%d,", insn.vA);
888 offset = (int) insn.vB;
889 break;
890 case Instruction::k22t:
891 snprintf(buffer + strlen(buffer), 256, " v%d, v%d,", insn.vA, insn.vB);
892 offset = (int) insn.vC;
893 break;
894 case Instruction::k10t:
895 case Instruction::k20t:
896 case Instruction::k30t:
897 offset = (int) insn.vA;
898 break;
899 default:
900 LOG(FATAL) << "Unexpected branch format " << (int)dalvikFormat
901 << " / opcode " << (int)opcode;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]902 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]903 snprintf(buffer + strlen(buffer), 256, " (%c%x)",
904 offset > 0 ? '+' : '-',
905 offset > 0 ? offset : -offset);
906 } else if (dfAttributes & DF_FORMAT_35C) {
907 unsigned int i;
908 for (i = 0; i < insn.vA; i++) {
909 if (i != 0) strcat(buffer, ",");
910 snprintf(buffer + strlen(buffer), 256, " v%d", insn.arg[i]);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]911 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]912 }
913 else if (dfAttributes & DF_FORMAT_3RC) {
914 snprintf(buffer + strlen(buffer), 256,
915 " v%d..v%d", insn.vC, insn.vC + insn.vA - 1);
916 } else {
917 if (dfAttributes & DF_A_IS_REG) {
918 snprintf(buffer + strlen(buffer), 256, " v%d", insn.vA);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]919 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]920 if (dfAttributes & DF_B_IS_REG) {
921 snprintf(buffer + strlen(buffer), 256, ", v%d", insn.vB);
922 } else if ((int)opcode < (int)kMirOpFirst) {
923 snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn.vB);
924 }
925 if (dfAttributes & DF_C_IS_REG) {
926 snprintf(buffer + strlen(buffer), 256, ", v%d", insn.vC);
927 } else if ((int)opcode < (int)kMirOpFirst) {
928 snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn.vC);
929 }
930 }
931 int length = strlen(buffer) + 1;
932 ret = (char*)oatNew(cUnit, length, false, kAllocDFInfo);
933 memcpy(ret, buffer, length);
934 return ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]935}
936
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]937char* getSSAName(const CompilationUnit* cUnit, int ssaReg, char* name)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]938{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]939 sprintf(name, "v%d_%d", SRegToVReg(cUnit, ssaReg),
940 SRegToSubscript(cUnit, ssaReg));
941 return name;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]942}
943
944/*
945 * Dalvik instruction disassembler with optional SSA printing.
946 */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]947char* oatFullDisassembler(CompilationUnit* cUnit, const MIR* mir)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]948{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]949 char buffer[256];
950 char operand0[32], operand1[32];
951 const DecodedInstruction* insn = &mir->dalvikInsn;
952 Instruction::Code opcode = insn->opcode;
953 int dfAttributes = oatDataFlowAttributes[opcode];
954 char* ret;
955 int length;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]956
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]957 buffer[0] = 0;
958 if (static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst)) {
959 if (static_cast<int>(opcode) == static_cast<int>(kMirOpPhi)) {
960 snprintf(buffer, 256, "PHI %s = (%s",
961 getSSAName(cUnit, mir->ssaRep->defs[0], operand0),
962 getSSAName(cUnit, mir->ssaRep->uses[0], operand1));
963 int i;
964 for (i = 1; i < mir->ssaRep->numUses; i++) {
965 snprintf(buffer + strlen(buffer), 256, ", %s",
966 getSSAName(cUnit, mir->ssaRep->uses[i], operand0));
967 }
968 snprintf(buffer + strlen(buffer), 256, ")");
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]969 } else {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]970 sprintf(buffer, "Opcode %#x", opcode);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]971 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]972 goto done;
973 } else {
974 strcpy(buffer, Instruction::Name(opcode));
975 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]976
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]977 /* For branches, decode the instructions to print out the branch targets */
978 if (Instruction::Flags(insn->opcode) & Instruction::kBranch) {
979 Instruction::Format dalvikFormat = Instruction::FormatOf(insn->opcode);
980 int delta = 0;
981 switch (dalvikFormat) {
982 case Instruction::k21t:
983 snprintf(buffer + strlen(buffer), 256, " %s, ",
984 getSSAName(cUnit, mir->ssaRep->uses[0], operand0));
985 delta = (int) insn->vB;
986 break;
987 case Instruction::k22t:
988 snprintf(buffer + strlen(buffer), 256, " %s, %s, ",
989 getSSAName(cUnit, mir->ssaRep->uses[0], operand0),
990 getSSAName(cUnit, mir->ssaRep->uses[1], operand1));
991 delta = (int) insn->vC;
992 break;
993 case Instruction::k10t:
994 case Instruction::k20t:
995 case Instruction::k30t:
996 delta = (int) insn->vA;
997 break;
998 default:
999 LOG(FATAL) << "Unexpected branch format: " << (int)dalvikFormat;
1000 }
1001 snprintf(buffer + strlen(buffer), 256, " %04x",
1002 mir->offset + delta);
1003 } else if (dfAttributes & (DF_FORMAT_35C | DF_FORMAT_3RC)) {
1004 unsigned int i;
1005 for (i = 0; i < insn->vA; i++) {
1006 if (i != 0) strcat(buffer, ",");
1007 snprintf(buffer + strlen(buffer), 256, " %s",
1008 getSSAName(cUnit, mir->ssaRep->uses[i], operand0));
1009 }
1010 } else {
1011 int udIdx;
1012 if (mir->ssaRep->numDefs) {
1013
1014 for (udIdx = 0; udIdx < mir->ssaRep->numDefs; udIdx++) {
1015 snprintf(buffer + strlen(buffer), 256, " %s",
1016 getSSAName(cUnit, mir->ssaRep->defs[udIdx], operand0));
1017 }
1018 strcat(buffer, ",");
1019 }
1020 if (mir->ssaRep->numUses) {
1021 /* No leading ',' for the first use */
1022 snprintf(buffer + strlen(buffer), 256, " %s",
1023 getSSAName(cUnit, mir->ssaRep->uses[0], operand0));
1024 for (udIdx = 1; udIdx < mir->ssaRep->numUses; udIdx++) {
1025 snprintf(buffer + strlen(buffer), 256, ", %s",
1026 getSSAName(cUnit, mir->ssaRep->uses[udIdx], operand0));
1027 }
1028 }
1029 if (static_cast<int>(opcode) < static_cast<int>(kMirOpFirst)) {
1030 Instruction::Format dalvikFormat = Instruction::FormatOf(opcode);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1031 switch (dalvikFormat) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1032 case Instruction::k11n: // op vA, #+B
1033 case Instruction::k21s: // op vAA, #+BBBB
1034 case Instruction::k21h: // op vAA, #+BBBB00000[00000000]
1035 case Instruction::k31i: // op vAA, #+BBBBBBBB
1036 case Instruction::k51l: // op vAA, #+BBBBBBBBBBBBBBBB
1037 snprintf(buffer + strlen(buffer), 256, " #%#x", insn->vB);
1038 break;
1039 case Instruction::k21c: // op vAA, thing@BBBB
1040 case Instruction::k31c: // op vAA, thing@BBBBBBBB
1041 snprintf(buffer + strlen(buffer), 256, " @%#x", insn->vB);
1042 break;
1043 case Instruction::k22b: // op vAA, vBB, #+CC
1044 case Instruction::k22s: // op vA, vB, #+CCCC
1045 snprintf(buffer + strlen(buffer), 256, " #%#x", insn->vC);
1046 break;
1047 case Instruction::k22c: // op vA, vB, thing@CCCC
1048 snprintf(buffer + strlen(buffer), 256, " @%#x", insn->vC);
1049 break;
1050 /* No need for special printing */
1051 default:
1052 break;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1053 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1054 }
1055 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1056
1057done:
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1058 length = strlen(buffer) + 1;
1059 ret = (char*) oatNew(cUnit, length, false, kAllocDFInfo);
1060 memcpy(ret, buffer, length);
1061 return ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1062}
1063
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]1064char* oatGetSSAString(CompilationUnit* cUnit, SSARepresentation* ssaRep)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1065{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1066 char buffer[256];
1067 char* ret;
1068 int i;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1069
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1070 buffer[0] = 0;
1071 for (i = 0; i < ssaRep->numDefs; i++) {
1072 int ssaReg = ssaRep->defs[i];
1073 sprintf(buffer + strlen(buffer), "s%d(v%d_%d) ", ssaReg,
1074 SRegToVReg(cUnit, ssaReg), SRegToSubscript(cUnit, ssaReg));
1075 }
1076
1077 if (ssaRep->numDefs) {
1078 strcat(buffer, "<- ");
1079 }
1080
1081 for (i = 0; i < ssaRep->numUses; i++) {
1082 int len = strlen(buffer);
1083 int ssaReg = ssaRep->uses[i];
1084
1085 if (snprintf(buffer + len, 250 - len, "s%d(v%d_%d) ", ssaReg,
1086 SRegToVReg(cUnit, ssaReg),
1087 SRegToSubscript(cUnit, ssaReg))) {
1088 strcat(buffer, "...");
1089 break;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1090 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1091 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1092
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1093 int length = strlen(buffer) + 1;
1094 ret = (char*)oatNew(cUnit, length, false, kAllocDFInfo);
1095 memcpy(ret, buffer, length);
1096 return ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1097}
1098
1099/* Any register that is used before being defined is considered live-in */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1100inline void handleLiveInUse(CompilationUnit* cUnit, ArenaBitVector* useV,
1101 ArenaBitVector* defV, ArenaBitVector* liveInV,
1102 int dalvikRegId)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1103{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1104 oatSetBit(cUnit, useV, dalvikRegId);
1105 if (!oatIsBitSet(defV, dalvikRegId)) {
1106 oatSetBit(cUnit, liveInV, dalvikRegId);
1107 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1108}
1109
1110/* Mark a reg as being defined */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1111inline void handleDef(CompilationUnit* cUnit, ArenaBitVector* defV,
1112 int dalvikRegId)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1113{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1114 oatSetBit(cUnit, defV, dalvikRegId);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1115}
1116
1117/*
1118 * Find out live-in variables for natural loops. Variables that are live-in in
1119 * the main loop body are considered to be defined in the entry block.
1120 */
1121bool oatFindLocalLiveIn(CompilationUnit* cUnit, BasicBlock* bb)
1122{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1123 MIR* mir;
1124 ArenaBitVector *useV, *defV, *liveInV;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1125
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1126 if (bb->dataFlowInfo == NULL) return false;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1127
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1128 useV = bb->dataFlowInfo->useV =
1129 oatAllocBitVector(cUnit, cUnit->numDalvikRegisters, false, kBitMapUse);
1130 defV = bb->dataFlowInfo->defV =
1131 oatAllocBitVector(cUnit, cUnit->numDalvikRegisters, false, kBitMapDef);
1132 liveInV = bb->dataFlowInfo->liveInV =
1133 oatAllocBitVector(cUnit, cUnit->numDalvikRegisters, false,
1134 kBitMapLiveIn);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1135
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1136 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1137 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
1138 DecodedInstruction *dInsn = &mir->dalvikInsn;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1139
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1140 if (dfAttributes & DF_HAS_USES) {
1141 if (dfAttributes & DF_UA) {
1142 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1143 if (dfAttributes & DF_A_WIDE) {
1144 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA+1);
1145 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1146 }
1147 if (dfAttributes & DF_UB) {
1148 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1149 if (dfAttributes & DF_B_WIDE) {
1150 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB+1);
1151 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1152 }
1153 if (dfAttributes & DF_UC) {
1154 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1155 if (dfAttributes & DF_C_WIDE) {
1156 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC+1);
1157 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1158 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1159 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1160 if (dfAttributes & DF_FORMAT_35C) {
1161 for (unsigned int i = 0; i < dInsn->vA; i++) {
1162 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->arg[i]);
1163 }
1164 }
1165 if (dfAttributes & DF_FORMAT_3RC) {
1166 for (unsigned int i = 0; i < dInsn->vA; i++) {
1167 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC+i);
1168 }
1169 }
1170 if (dfAttributes & DF_HAS_DEFS) {
1171 handleDef(cUnit, defV, dInsn->vA);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1172 if (dfAttributes & DF_A_WIDE) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1173 handleDef(cUnit, defV, dInsn->vA+1);
1174 }
1175 }
1176 }
1177 return true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1178}
1179
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1180int addNewSReg(CompilationUnit* cUnit, int vReg)
1181{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1182 // Compiler temps always have a subscript of 0
1183 int subscript = (vReg < 0) ? 0 : ++cUnit->SSALastDefs[vReg];
1184 int ssaReg = cUnit->numSSARegs++;
1185 oatInsertGrowableList(cUnit, cUnit->ssaBaseVRegs, vReg);
1186 oatInsertGrowableList(cUnit, cUnit->ssaSubscripts, subscript);
buzbee2cfc6392012-05-07 14:51:40 -0700[diff] [blame]1187 char* name = (char*)oatNew(cUnit, SSA_NAME_MAX, true, kAllocDFInfo);
1188 oatInsertGrowableList(cUnit, cUnit->ssaStrings, (intptr_t)getSSAName(cUnit, ssaReg, name));
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1189 DCHECK_EQ(cUnit->ssaBaseVRegs->numUsed, cUnit->ssaSubscripts->numUsed);
1190 return ssaReg;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1191}
1192
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1193/* Find out the latest SSA register for a given Dalvik register */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1194void handleSSAUse(CompilationUnit* cUnit, int* uses, int dalvikReg,
1195 int regIndex)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1196{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1197 DCHECK((dalvikReg >= 0) && (dalvikReg < cUnit->numDalvikRegisters));
1198 uses[regIndex] = cUnit->vRegToSSAMap[dalvikReg];
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1199}
1200
1201/* Setup a new SSA register for a given Dalvik register */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1202void handleSSADef(CompilationUnit* cUnit, int* defs, int dalvikReg,
1203 int regIndex)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1204{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1205 DCHECK((dalvikReg >= 0) && (dalvikReg < cUnit->numDalvikRegisters));
1206 int ssaReg = addNewSReg(cUnit, dalvikReg);
1207 cUnit->vRegToSSAMap[dalvikReg] = ssaReg;
1208 defs[regIndex] = ssaReg;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1209}
1210
buzbeeec5adf32011-09-11 15:25:43 -0700[diff] [blame]1211/* Look up new SSA names for format_35c instructions */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1212void dataFlowSSAFormat35C(CompilationUnit* cUnit, MIR* mir)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1213{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1214 DecodedInstruction *dInsn = &mir->dalvikInsn;
1215 int numUses = dInsn->vA;
1216 int i;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1217
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1218 mir->ssaRep->numUses = numUses;
1219 mir->ssaRep->uses = (int *)oatNew(cUnit, sizeof(int) * numUses, true,
1220 kAllocDFInfo);
1221 // NOTE: will be filled in during type & size inference pass
1222 mir->ssaRep->fpUse = (bool *)oatNew(cUnit, sizeof(bool) * numUses, true,
buzbee5abfa3e2012-01-31 17:01:43 -0800[diff] [blame]1223 kAllocDFInfo);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1224
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1225 for (i = 0; i < numUses; i++) {
1226 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->arg[i], i);
1227 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1228}
1229
buzbeeec5adf32011-09-11 15:25:43 -0700[diff] [blame]1230/* Look up new SSA names for format_3rc instructions */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1231void dataFlowSSAFormat3RC(CompilationUnit* cUnit, MIR* mir)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1232{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1233 DecodedInstruction *dInsn = &mir->dalvikInsn;
1234 int numUses = dInsn->vA;
1235 int i;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1236
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1237 mir->ssaRep->numUses = numUses;
1238 mir->ssaRep->uses = (int *)oatNew(cUnit, sizeof(int) * numUses, true,
1239 kAllocDFInfo);
1240 // NOTE: will be filled in during type & size inference pass
1241 mir->ssaRep->fpUse = (bool *)oatNew(cUnit, sizeof(bool) * numUses, true,
buzbee5abfa3e2012-01-31 17:01:43 -0800[diff] [blame]1242 kAllocDFInfo);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1243
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1244 for (i = 0; i < numUses; i++) {
1245 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+i, i);
1246 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1247}
1248
1249/* Entry function to convert a block into SSA representation */
1250bool oatDoSSAConversion(CompilationUnit* cUnit, BasicBlock* bb)
1251{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1252 MIR* mir;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1253
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1254 if (bb->dataFlowInfo == NULL) return false;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1255
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1256 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1257 mir->ssaRep = (struct SSARepresentation *)
1258 oatNew(cUnit, sizeof(SSARepresentation), true, kAllocDFInfo);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1259
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1260 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1261
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1262 // If not a pseudo-op, note non-leaf or can throw
1263 if (static_cast<int>(mir->dalvikInsn.opcode) <
1264 static_cast<int>(kNumPackedOpcodes)) {
1265 int flags = Instruction::Flags(mir->dalvikInsn.opcode);
buzbeecefd1872011-09-09 09:59:52 -0700[diff] [blame]1266
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1267 if (flags & Instruction::kThrow) {
1268 cUnit->attrs &= ~METHOD_IS_THROW_FREE;
1269 }
buzbeecefd1872011-09-09 09:59:52 -0700[diff] [blame]1270
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1271 if (flags & Instruction::kInvoke) {
1272 cUnit->attrs &= ~METHOD_IS_LEAF;
1273 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1274 }
1275
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1276 int numUses = 0;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1277
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1278 if (dfAttributes & DF_FORMAT_35C) {
1279 dataFlowSSAFormat35C(cUnit, mir);
1280 continue;
buzbee5abfa3e2012-01-31 17:01:43 -0800[diff] [blame]1281 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1282
1283 if (dfAttributes & DF_FORMAT_3RC) {
1284 dataFlowSSAFormat3RC(cUnit, mir);
1285 continue;
1286 }
1287
1288 if (dfAttributes & DF_HAS_USES) {
1289 if (dfAttributes & DF_UA) {
1290 numUses++;
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1291 if (dfAttributes & DF_A_WIDE) {
1292 numUses ++;
1293 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1294 }
1295 if (dfAttributes & DF_UB) {
1296 numUses++;
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1297 if (dfAttributes & DF_B_WIDE) {
1298 numUses ++;
1299 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1300 }
1301 if (dfAttributes & DF_UC) {
1302 numUses++;
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1303 if (dfAttributes & DF_C_WIDE) {
1304 numUses ++;
1305 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1306 }
1307 }
1308
1309 if (numUses) {
1310 mir->ssaRep->numUses = numUses;
1311 mir->ssaRep->uses = (int *)oatNew(cUnit, sizeof(int) * numUses,
1312 false, kAllocDFInfo);
1313 mir->ssaRep->fpUse = (bool *)oatNew(cUnit, sizeof(bool) * numUses,
1314 false, kAllocDFInfo);
1315 }
1316
1317 int numDefs = 0;
1318
1319 if (dfAttributes & DF_HAS_DEFS) {
1320 numDefs++;
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1321 if (dfAttributes & DF_A_WIDE) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1322 numDefs++;
1323 }
1324 }
1325
1326 if (numDefs) {
1327 mir->ssaRep->numDefs = numDefs;
1328 mir->ssaRep->defs = (int *)oatNew(cUnit, sizeof(int) * numDefs,
1329 false, kAllocDFInfo);
1330 mir->ssaRep->fpDef = (bool *)oatNew(cUnit, sizeof(bool) * numDefs,
1331 false, kAllocDFInfo);
1332 }
1333
1334 DecodedInstruction *dInsn = &mir->dalvikInsn;
1335
1336 if (dfAttributes & DF_HAS_USES) {
1337 numUses = 0;
1338 if (dfAttributes & DF_UA) {
1339 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
1340 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA, numUses++);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1341 if (dfAttributes & DF_A_WIDE) {
1342 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
1343 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA+1, numUses++);
1344 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1345 }
1346 if (dfAttributes & DF_UB) {
1347 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
1348 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB, numUses++);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1349 if (dfAttributes & DF_B_WIDE) {
1350 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
1351 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB+1, numUses++);
1352 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1353 }
1354 if (dfAttributes & DF_UC) {
1355 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
1356 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC, numUses++);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1357 if (dfAttributes & DF_C_WIDE) {
1358 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
1359 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+1, numUses++);
1360 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1361 }
1362 }
1363 if (dfAttributes & DF_HAS_DEFS) {
1364 mir->ssaRep->fpDef[0] = dfAttributes & DF_FP_A;
1365 handleSSADef(cUnit, mir->ssaRep->defs, dInsn->vA, 0);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1366 if (dfAttributes & DF_A_WIDE) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1367 mir->ssaRep->fpDef[1] = dfAttributes & DF_FP_A;
1368 handleSSADef(cUnit, mir->ssaRep->defs, dInsn->vA+1, 1);
1369 }
1370 }
1371 }
1372
1373 if (!cUnit->disableDataflow) {
1374 /*
1375 * Take a snapshot of Dalvik->SSA mapping at the end of each block. The
1376 * input to PHI nodes can be derived from the snapshot of all
1377 * predecessor blocks.
1378 */
1379 bb->dataFlowInfo->vRegToSSAMap =
1380 (int *)oatNew(cUnit, sizeof(int) * cUnit->numDalvikRegisters, false,
1381 kAllocDFInfo);
1382
1383 memcpy(bb->dataFlowInfo->vRegToSSAMap, cUnit->vRegToSSAMap,
1384 sizeof(int) * cUnit->numDalvikRegisters);
1385 }
1386 return true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1387}
1388
1389/* Setup a constant value for opcodes thare have the DF_SETS_CONST attribute */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1390void setConstant(CompilationUnit* cUnit, int ssaReg, int value)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1391{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1392 oatSetBit(cUnit, cUnit->isConstantV, ssaReg);
1393 cUnit->constantValues[ssaReg] = value;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1394}
1395
1396bool oatDoConstantPropagation(CompilationUnit* cUnit, BasicBlock* bb)
1397{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1398 MIR* mir;
1399 ArenaBitVector *isConstantV = cUnit->isConstantV;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1400
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1401 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1402 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1403
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1404 DecodedInstruction *dInsn = &mir->dalvikInsn;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1405
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1406 if (!(dfAttributes & DF_HAS_DEFS)) continue;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1407
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1408 /* Handle instructions that set up constants directly */
1409 if (dfAttributes & DF_SETS_CONST) {
1410 if (dfAttributes & DF_DA) {
1411 switch (dInsn->opcode) {
1412 case Instruction::CONST_4:
1413 case Instruction::CONST_16:
1414 case Instruction::CONST:
1415 setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
1416 break;
1417 case Instruction::CONST_HIGH16:
1418 setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB << 16);
1419 break;
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1420 case Instruction::CONST_WIDE_16:
1421 case Instruction::CONST_WIDE_32:
1422 setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
1423 setConstant(cUnit, mir->ssaRep->defs[1], 0);
1424 break;
1425 case Instruction::CONST_WIDE:
1426 setConstant(cUnit, mir->ssaRep->defs[0], (int) dInsn->vB_wide);
1427 setConstant(cUnit, mir->ssaRep->defs[1],
1428 (int) (dInsn->vB_wide >> 32));
1429 break;
1430 case Instruction::CONST_WIDE_HIGH16:
1431 setConstant(cUnit, mir->ssaRep->defs[0], 0);
1432 setConstant(cUnit, mir->ssaRep->defs[1], dInsn->vB << 16);
1433 break;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1434 default:
1435 break;
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1436 }
buzbee2cfc6392012-05-07 14:51:40 -0700[diff] [blame]1437 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1438 /* Handle instructions that set up constants directly */
buzbee2cfc6392012-05-07 14:51:40 -0700[diff] [blame]1439 } else if (dfAttributes & DF_IS_MOVE) {
1440 int i;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1441
buzbee2cfc6392012-05-07 14:51:40 -0700[diff] [blame]1442 for (i = 0; i < mir->ssaRep->numUses; i++) {
1443 if (!oatIsBitSet(isConstantV, mir->ssaRep->uses[i])) break;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1444 }
1445 /* Move a register holding a constant to another register */
1446 if (i == mir->ssaRep->numUses) {
1447 setConstant(cUnit, mir->ssaRep->defs[0],
1448 cUnit->constantValues[mir->ssaRep->uses[0]]);
buzbeebff24652012-05-06 16:22:05 -0700[diff] [blame]1449 if (dfAttributes & DF_A_WIDE) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1450 setConstant(cUnit, mir->ssaRep->defs[1],
1451 cUnit->constantValues[mir->ssaRep->uses[1]]);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1452 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1453 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1454 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1455 }
1456 /* TODO: implement code to handle arithmetic operations */
1457 return true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1458}
1459
1460/* Setup the basic data structures for SSA conversion */
1461void oatInitializeSSAConversion(CompilationUnit* cUnit)
1462{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1463 int i;
1464 int numDalvikReg = cUnit->numDalvikRegisters;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1465
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1466 cUnit->ssaBaseVRegs = (GrowableList *)oatNew(cUnit, sizeof(GrowableList),
1467 false, kAllocDFInfo);
1468 cUnit->ssaSubscripts = (GrowableList *)oatNew(cUnit, sizeof(GrowableList),
1469 false, kAllocDFInfo);
buzbee2cfc6392012-05-07 14:51:40 -0700[diff] [blame]1470 cUnit->ssaStrings = (GrowableList *)oatNew(cUnit, sizeof(GrowableList),
1471 false, kAllocDFInfo);
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1472 // Create the ssa mappings, estimating the max size
1473 oatInitGrowableList(cUnit, cUnit->ssaBaseVRegs,
1474 numDalvikReg + cUnit->defCount + 128,
1475 kListSSAtoDalvikMap);
1476 oatInitGrowableList(cUnit, cUnit->ssaSubscripts,
1477 numDalvikReg + cUnit->defCount + 128,
1478 kListSSAtoDalvikMap);
buzbee2cfc6392012-05-07 14:51:40 -0700[diff] [blame]1479 oatInitGrowableList(cUnit, cUnit->ssaStrings,
1480 numDalvikReg + cUnit->defCount + 128,
1481 kListSSAtoDalvikMap);
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1482 /*
1483 * Initial number of SSA registers is equal to the number of Dalvik
1484 * registers.
1485 */
1486 cUnit->numSSARegs = numDalvikReg;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1487
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1488 /*
1489 * Initialize the SSA2Dalvik map list. For the first numDalvikReg elements,
1490 * the subscript is 0 so we use the ENCODE_REG_SUB macro to encode the value
1491 * into "(0 << 16) | i"
1492 */
1493 for (i = 0; i < numDalvikReg; i++) {
1494 oatInsertGrowableList(cUnit, cUnit->ssaBaseVRegs, i);
1495 oatInsertGrowableList(cUnit, cUnit->ssaSubscripts, 0);
buzbee2cfc6392012-05-07 14:51:40 -0700[diff] [blame]1496 char* name = (char*)oatNew(cUnit, SSA_NAME_MAX, true, kAllocDFInfo);
1497 oatInsertGrowableList(cUnit, cUnit->ssaStrings, (intptr_t)getSSAName(cUnit, i, name));
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1498 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1499
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1500 /*
1501 * Initialize the DalvikToSSAMap map. There is one entry for each
1502 * Dalvik register, and the SSA names for those are the same.
1503 */
1504 cUnit->vRegToSSAMap = (int *)oatNew(cUnit, sizeof(int) * numDalvikReg,
1505 false, kAllocDFInfo);
1506 /* Keep track of the higest def for each dalvik reg */
1507 cUnit->SSALastDefs = (int *)oatNew(cUnit, sizeof(int) * numDalvikReg,
1508 false, kAllocDFInfo);
buzbeef0cde542011-09-13 14:55:02 -0700[diff] [blame]1509
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1510 for (i = 0; i < numDalvikReg; i++) {
1511 cUnit->vRegToSSAMap[i] = i;
1512 cUnit->SSALastDefs[i] = 0;
1513 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1514
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1515 /* Add ssa reg for Method* */
1516 cUnit->methodSReg = addNewSReg(cUnit, SSA_METHOD_BASEREG);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1517
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1518 /*
1519 * Allocate the BasicBlockDataFlow structure for the entry and code blocks
1520 */
1521 GrowableListIterator iterator;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1522
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1523 oatGrowableListIteratorInit(&cUnit->blockList, &iterator);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1524
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1525 while (true) {
1526 BasicBlock* bb = (BasicBlock *) oatGrowableListIteratorNext(&iterator);
1527 if (bb == NULL) break;
1528 if (bb->hidden == true) continue;
1529 if (bb->blockType == kDalvikByteCode ||
1530 bb->blockType == kEntryBlock ||
1531 bb->blockType == kExitBlock) {
1532 bb->dataFlowInfo = (BasicBlockDataFlow *)
1533 oatNew(cUnit, sizeof(BasicBlockDataFlow), true, kAllocDFInfo);
1534 }
1535 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1536}
1537
1538/* Clear the visited flag for each BB */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1539bool oatClearVisitedFlag(struct CompilationUnit* cUnit, struct BasicBlock* bb)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1540{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1541 bb->visited = false;
1542 return true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1543}
1544
1545void oatDataFlowAnalysisDispatcher(CompilationUnit* cUnit,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1546 bool (*func)(CompilationUnit*, BasicBlock*),
1547 DataFlowAnalysisMode dfaMode,
1548 bool isIterative)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1549{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1550 bool change = true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1551
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1552 while (change) {
1553 change = false;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1554
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1555 switch (dfaMode) {
1556 /* Scan all blocks and perform the operations specified in func */
1557 case kAllNodes:
1558 {
1559 GrowableListIterator iterator;
1560 oatGrowableListIteratorInit(&cUnit->blockList, &iterator);
1561 while (true) {
1562 BasicBlock* bb =
1563 (BasicBlock *) oatGrowableListIteratorNext(&iterator);
1564 if (bb == NULL) break;
1565 if (bb->hidden == true) continue;
1566 change |= (*func)(cUnit, bb);
1567 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1568 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1569 break;
1570 /* Scan reachable blocks and perform the ops specified in func. */
1571 case kReachableNodes:
1572 {
1573 int numReachableBlocks = cUnit->numReachableBlocks;
1574 int idx;
1575 const GrowableList *blockList = &cUnit->blockList;
1576
1577 for (idx = 0; idx < numReachableBlocks; idx++) {
1578 int blockIdx = cUnit->dfsOrder.elemList[idx];
1579 BasicBlock* bb = (BasicBlock *)
1580 oatGrowableListGetElement(blockList, blockIdx);
1581 change |= (*func)(cUnit, bb);
1582 }
1583 }
1584 break;
1585
1586 /* Scan reachable blocks by pre-order dfs and invoke func on each. */
1587 case kPreOrderDFSTraversal:
1588 {
1589 int numReachableBlocks = cUnit->numReachableBlocks;
1590 int idx;
1591 const GrowableList *blockList = &cUnit->blockList;
1592
1593 for (idx = 0; idx < numReachableBlocks; idx++) {
1594 int dfsIdx = cUnit->dfsOrder.elemList[idx];
1595 BasicBlock* bb = (BasicBlock *)
1596 oatGrowableListGetElement(blockList, dfsIdx);
1597 change |= (*func)(cUnit, bb);
1598 }
1599 }
1600 break;
1601 /* Scan reachable blocks post-order dfs and invoke func on each. */
1602 case kPostOrderDFSTraversal:
1603 {
1604 int numReachableBlocks = cUnit->numReachableBlocks;
1605 int idx;
1606 const GrowableList *blockList = &cUnit->blockList;
1607
1608 for (idx = numReachableBlocks - 1; idx >= 0; idx--) {
1609 int dfsIdx = cUnit->dfsOrder.elemList[idx];
1610 BasicBlock* bb = (BasicBlock *)
1611 oatGrowableListGetElement(blockList, dfsIdx);
1612 change |= (*func)(cUnit, bb);
1613 }
1614 }
1615 break;
1616 /* Scan reachable post-order dom tree and invoke func on each. */
1617 case kPostOrderDOMTraversal:
1618 {
1619 int numReachableBlocks = cUnit->numReachableBlocks;
1620 int idx;
1621 const GrowableList *blockList = &cUnit->blockList;
1622
1623 for (idx = 0; idx < numReachableBlocks; idx++) {
1624 int domIdx = cUnit->domPostOrderTraversal.elemList[idx];
1625 BasicBlock* bb = (BasicBlock *)
1626 oatGrowableListGetElement(blockList, domIdx);
1627 change |= (*func)(cUnit, bb);
1628 }
1629 }
1630 break;
1631 /* Scan reachable blocks reverse post-order dfs, invoke func on each */
1632 case kReversePostOrderTraversal:
1633 {
1634 int numReachableBlocks = cUnit->numReachableBlocks;
1635 int idx;
1636 const GrowableList *blockList = &cUnit->blockList;
1637
1638 for (idx = numReachableBlocks - 1; idx >= 0; idx--) {
1639 int revIdx = cUnit->dfsPostOrder.elemList[idx];
1640 BasicBlock* bb = (BasicBlock *)
1641 oatGrowableListGetElement(blockList, revIdx);
1642 change |= (*func)(cUnit, bb);
1643 }
1644 }
1645 break;
1646 default:
1647 LOG(FATAL) << "Unknown traversal mode " << (int)dfaMode;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1648 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1649 /* If isIterative is false, exit the loop after the first iteration */
1650 change &= isIterative;
1651 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1652}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1653
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1654/* Advance to next strictly dominated MIR node in an extended basic block */
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1655MIR* advanceMIR(CompilationUnit* cUnit, BasicBlock** pBb, MIR* mir,
1656 ArenaBitVector* bv, bool clearMark) {
1657 BasicBlock* bb = *pBb;
1658 if (mir != NULL) {
1659 mir = mir->next;
1660 if (mir == NULL) {
1661 bb = bb->fallThrough;
1662 if ((bb == NULL) || bb->predecessors->numUsed != 1) {
1663 mir = NULL;
1664 } else {
1665 if (bv) {
1666 oatSetBit(cUnit, bv, bb->id);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1667 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1668 *pBb = bb;
1669 mir = bb->firstMIRInsn;
1670 }
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1671 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1672 }
1673 if (mir && clearMark) {
1674 mir->optimizationFlags &= ~MIR_MARK;
1675 }
1676 return mir;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1677}
1678
buzbeefc9e6fa2012-03-23 15:14:29 -0700[diff] [blame]1679/*
1680 * To be used at an invoke mir. If the logically next mir node represents
1681 * a move-result, return it. Else, return NULL. If a move-result exists,
1682 * it is required to immediately follow the invoke with no intervening
1683 * opcodes or incoming arcs. However, if the result of the invoke is not
1684 * used, a move-result may not be present.
1685 */
buzbee15bf9802012-06-12 17:49:27 -0700[diff] [blame^]1686MIR* oatFindMoveResult(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir)
buzbeefc9e6fa2012-03-23 15:14:29 -0700[diff] [blame]1687{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1688 BasicBlock* tbb = bb;
1689 mir = advanceMIR(cUnit, &tbb, mir, NULL, false);
1690 while (mir != NULL) {
buzbee15bf9802012-06-12 17:49:27 -0700[diff] [blame^]1691 if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) ||
1692 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE)) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1693 break;
1694 }
1695 // Keep going if pseudo op, otherwise terminate
1696 if (mir->dalvikInsn.opcode <
1697 static_cast<Instruction::Code>(kNumPackedOpcodes)) {
1698 mir = NULL;
1699 } else {
1700 mir = advanceMIR(cUnit, &tbb, mir, NULL, false);
1701 }
1702 }
1703 return mir;
buzbeefc9e6fa2012-03-23 15:14:29 -0700[diff] [blame]1704}
1705
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]1706void squashDupRangeChecks(CompilationUnit* cUnit, BasicBlock** pBp, MIR* mir,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1707 int arraySreg, int indexSreg)
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]1708{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1709 while (true) {
1710 mir = advanceMIR(cUnit, pBp, mir, NULL, false);
1711 if (!mir) {
1712 break;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]1713 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1714 if ((mir->ssaRep == NULL) ||
1715 (mir->optimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
1716 continue;
1717 }
1718 int checkArray = INVALID_SREG;
1719 int checkIndex = INVALID_SREG;
1720 switch (mir->dalvikInsn.opcode) {
1721 case Instruction::AGET:
1722 case Instruction::AGET_OBJECT:
1723 case Instruction::AGET_BOOLEAN:
1724 case Instruction::AGET_BYTE:
1725 case Instruction::AGET_CHAR:
1726 case Instruction::AGET_SHORT:
1727 case Instruction::AGET_WIDE:
1728 checkArray = mir->ssaRep->uses[0];
1729 checkIndex = mir->ssaRep->uses[1];
1730 break;
1731 case Instruction::APUT:
1732 case Instruction::APUT_OBJECT:
1733 case Instruction::APUT_SHORT:
1734 case Instruction::APUT_CHAR:
1735 case Instruction::APUT_BYTE:
1736 case Instruction::APUT_BOOLEAN:
1737 checkArray = mir->ssaRep->uses[1];
1738 checkIndex = mir->ssaRep->uses[2];
1739 break;
1740 case Instruction::APUT_WIDE:
1741 checkArray = mir->ssaRep->uses[2];
1742 checkIndex = mir->ssaRep->uses[3];
1743 default:
1744 break;
1745 }
1746 if (checkArray == INVALID_SREG) {
1747 continue;
1748 }
1749 if ((arraySreg == checkArray) && (indexSreg == checkIndex)) {
1750 if (cUnit->printMe) {
1751 LOG(INFO) << "Squashing range check @ 0x" << std::hex << mir->offset;
1752 }
1753 mir->optimizationFlags |= MIR_IGNORE_RANGE_CHECK;
1754 }
1755 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]1756}
1757
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1758/* Allocate a compiler temp, return Sreg. Reuse existing if no conflict */
1759int allocCompilerTempSreg(CompilationUnit* cUnit, ArenaBitVector* bv)
1760{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1761 for (int i = 0; i < cUnit->numCompilerTemps; i++) {
1762 CompilerTemp* ct = (CompilerTemp*)cUnit->compilerTemps.elemList[i];
1763 ArenaBitVector* tBv = ct->bv;
1764 if (!oatTestBitVectors(bv, tBv)) {
1765 // Combine live maps and reuse existing temp
1766 oatUnifyBitVectors(tBv, tBv, bv);
1767 return ct->sReg;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1768 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1769 }
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1770
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1771 // Create a new compiler temp & associated live bitmap
1772 CompilerTemp* ct = (CompilerTemp*)oatNew(cUnit, sizeof(CompilerTemp),
1773 true, kAllocMisc);
1774 ArenaBitVector *nBv = oatAllocBitVector(cUnit, cUnit->numBlocks, true,
1775 kBitMapMisc);
1776 oatCopyBitVector(nBv, bv);
1777 ct->bv = nBv;
1778 ct->sReg = addNewSReg(cUnit, SSA_CTEMP_BASEREG - cUnit->numCompilerTemps);
1779 cUnit->numCompilerTemps++;
1780 oatInsertGrowableList(cUnit, &cUnit->compilerTemps, (intptr_t)ct);
1781 DCHECK_EQ(cUnit->numCompilerTemps, (int)cUnit->compilerTemps.numUsed);
1782 return ct->sReg;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1783}
1784
1785/* Creata a new MIR node for a new pseudo op. */
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1786MIR* rawMIR(CompilationUnit* cUnit, Instruction::Code opcode, int defs,
1787 int uses)
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1788{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1789 MIR* res = (MIR*)oatNew( cUnit, sizeof(MIR), true, kAllocMIR);
1790 res->ssaRep =(struct SSARepresentation *)
1791 oatNew(cUnit, sizeof(SSARepresentation), true, kAllocDFInfo);
1792 if (uses) {
1793 res->ssaRep->numUses = uses;
1794 res->ssaRep->uses = (int*)oatNew(cUnit, sizeof(int) * uses, false,
1795 kAllocDFInfo);
1796 }
1797 if (defs) {
1798 res->ssaRep->numDefs = defs;
1799 res->ssaRep->defs = (int*)oatNew(cUnit, sizeof(int) * defs, false,
1800 kAllocDFInfo);
1801 res->ssaRep->fpDef = (bool*)oatNew(cUnit, sizeof(bool) * defs, true,
1802 kAllocDFInfo);
1803 }
1804 res->dalvikInsn.opcode = opcode;
1805 return res;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1806}
1807
1808/* Do some MIR-level basic block optimizations */
1809bool basicBlockOpt(CompilationUnit* cUnit, BasicBlock* bb)
1810{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1811 int numTemps = 0;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1812
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1813 for (MIR* mir = bb->firstMIRInsn; mir; mir = mir->next) {
1814 // Look for interesting opcodes, skip otherwise
1815 Instruction::Code opcode = mir->dalvikInsn.opcode;
1816 switch (opcode) {
1817 case Instruction::AGET:
1818 case Instruction::AGET_OBJECT:
1819 case Instruction::AGET_BOOLEAN:
1820 case Instruction::AGET_BYTE:
1821 case Instruction::AGET_CHAR:
1822 case Instruction::AGET_SHORT:
1823 case Instruction::AGET_WIDE:
1824 if (!(mir->optimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
1825 int arrSreg = mir->ssaRep->uses[0];
1826 int idxSreg = mir->ssaRep->uses[1];
1827 BasicBlock* tbb = bb;
1828 squashDupRangeChecks(cUnit, &tbb, mir, arrSreg, idxSreg);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1829 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1830 break;
1831 case Instruction::APUT:
1832 case Instruction::APUT_OBJECT:
1833 case Instruction::APUT_SHORT:
1834 case Instruction::APUT_CHAR:
1835 case Instruction::APUT_BYTE:
1836 case Instruction::APUT_BOOLEAN:
1837 case Instruction::APUT_WIDE:
1838 if (!(mir->optimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
1839 int start = (opcode == Instruction::APUT_WIDE) ? 2 : 1;
1840 int arrSreg = mir->ssaRep->uses[start];
1841 int idxSreg = mir->ssaRep->uses[start + 1];
1842 BasicBlock* tbb = bb;
1843 squashDupRangeChecks(cUnit, &tbb, mir, arrSreg, idxSreg);
1844 }
1845 break;
1846 case Instruction::CMPL_FLOAT:
1847 case Instruction::CMPL_DOUBLE:
1848 case Instruction::CMPG_FLOAT:
1849 case Instruction::CMPG_DOUBLE:
1850 case Instruction::CMP_LONG:
1851 if (mir->next != NULL) {
1852 MIR* mirNext = mir->next;
1853 Instruction::Code brOpcode = mirNext->dalvikInsn.opcode;
1854 ConditionCode ccode = kCondNv;
1855 switch(brOpcode) {
1856 case Instruction::IF_EQZ:
1857 ccode = kCondEq;
1858 break;
1859 case Instruction::IF_NEZ:
1860 ccode = kCondNe;
1861 break;
1862 case Instruction::IF_LTZ:
1863 ccode = kCondLt;
1864 break;
1865 case Instruction::IF_GEZ:
1866 ccode = kCondGe;
1867 break;
1868 case Instruction::IF_GTZ:
1869 ccode = kCondGt;
1870 break;
1871 case Instruction::IF_LEZ:
1872 ccode = kCondLe;
1873 break;
1874 default:
1875 break;
1876 }
1877 // Make sure result of cmp is used by next insn and nowhere else
1878 if ((ccode != kCondNv) &&
1879 (mir->ssaRep->defs[0] == mirNext->ssaRep->uses[0]) &&
1880 (getSSAUseCount(cUnit, mir->ssaRep->defs[0]) == 1)) {
1881 mirNext->dalvikInsn.arg[0] = ccode;
1882 switch(opcode) {
1883 case Instruction::CMPL_FLOAT:
1884 mirNext->dalvikInsn.opcode =
1885 static_cast<Instruction::Code>(kMirOpFusedCmplFloat);
1886 break;
1887 case Instruction::CMPL_DOUBLE:
1888 mirNext->dalvikInsn.opcode =
1889 static_cast<Instruction::Code>(kMirOpFusedCmplDouble);
1890 break;
1891 case Instruction::CMPG_FLOAT:
1892 mirNext->dalvikInsn.opcode =
1893 static_cast<Instruction::Code>(kMirOpFusedCmpgFloat);
1894 break;
1895 case Instruction::CMPG_DOUBLE:
1896 mirNext->dalvikInsn.opcode =
1897 static_cast<Instruction::Code>(kMirOpFusedCmpgDouble);
1898 break;
1899 case Instruction::CMP_LONG:
1900 mirNext->dalvikInsn.opcode =
1901 static_cast<Instruction::Code>(kMirOpFusedCmpLong);
1902 break;
1903 default: LOG(ERROR) << "Unexpected opcode: " << (int)opcode;
1904 }
1905 mir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
1906 mirNext->ssaRep->numUses = mir->ssaRep->numUses;
1907 mirNext->ssaRep->uses = mir->ssaRep->uses;
1908 mirNext->ssaRep->fpUse = mir->ssaRep->fpUse;
1909 mirNext->ssaRep->numDefs = 0;
1910 mir->ssaRep->numUses = 0;
1911 mir->ssaRep->numDefs = 0;
1912 }
1913 }
1914 break;
1915 default:
1916 break;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1917 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1918 }
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1919
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1920 if (numTemps > cUnit->numCompilerTemps) {
1921 cUnit->numCompilerTemps = numTemps;
1922 }
1923 return true;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1924}
1925
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1926bool nullCheckEliminationInit(struct CompilationUnit* cUnit,
1927 struct BasicBlock* bb)
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1928{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1929 if (bb->dataFlowInfo == NULL) return false;
1930 bb->dataFlowInfo->endingNullCheckV =
1931 oatAllocBitVector(cUnit, cUnit->numSSARegs, false, kBitMapNullCheck);
1932 oatClearAllBits(bb->dataFlowInfo->endingNullCheckV);
1933 return true;
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1934}
1935
1936/* Eliminate unnecessary null checks for a basic block. */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1937bool eliminateNullChecks( struct CompilationUnit* cUnit, struct BasicBlock* bb)
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1938{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1939 if (bb->dataFlowInfo == NULL) return false;
1940
1941 /*
1942 * Set initial state. Be conservative with catch
1943 * blocks and start with no assumptions about null check
1944 * status (except for "this").
1945 */
1946 if ((bb->blockType == kEntryBlock) | bb->catchEntry) {
1947 oatClearAllBits(cUnit->tempSSARegisterV);
1948 if ((cUnit->access_flags & kAccStatic) == 0) {
1949 // If non-static method, mark "this" as non-null
1950 int thisReg = cUnit->numDalvikRegisters - cUnit->numIns;
1951 oatSetBit(cUnit, cUnit->tempSSARegisterV, thisReg);
1952 }
1953 } else {
1954 // Starting state is intesection of all incoming arcs
1955 GrowableListIterator iter;
1956 oatGrowableListIteratorInit(bb->predecessors, &iter);
1957 BasicBlock* predBB = (BasicBlock*)oatGrowableListIteratorNext(&iter);
1958 DCHECK(predBB != NULL);
1959 oatCopyBitVector(cUnit->tempSSARegisterV,
1960 predBB->dataFlowInfo->endingNullCheckV);
1961 while (true) {
1962 predBB = (BasicBlock*)oatGrowableListIteratorNext(&iter);
1963 if (!predBB) break;
1964 if ((predBB->dataFlowInfo == NULL) ||
1965 (predBB->dataFlowInfo->endingNullCheckV == NULL)) {
1966 continue;
1967 }
1968 oatIntersectBitVectors(cUnit->tempSSARegisterV,
1969 cUnit->tempSSARegisterV,
1970 predBB->dataFlowInfo->endingNullCheckV);
1971 }
1972 }
1973
1974 // Walk through the instruction in the block, updating as necessary
1975 for (MIR* mir = bb->firstMIRInsn; mir; mir = mir->next) {
1976 if (mir->ssaRep == NULL) {
1977 continue;
1978 }
1979 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
1980
1981 // Mark target of NEW* as non-null
1982 if (dfAttributes & DF_NON_NULL_DST) {
1983 oatSetBit(cUnit, cUnit->tempSSARegisterV, mir->ssaRep->defs[0]);
1984 }
1985
1986 // Mark non-null returns from invoke-style NEW*
1987 if (dfAttributes & DF_NON_NULL_RET) {
1988 MIR* nextMir = mir->next;
1989 // Next should be an MOVE_RESULT_OBJECT
1990 if (nextMir &&
1991 nextMir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) {
1992 // Mark as null checked
1993 oatSetBit(cUnit, cUnit->tempSSARegisterV, nextMir->ssaRep->defs[0]);
1994 } else {
1995 if (nextMir) {
1996 LOG(WARNING) << "Unexpected opcode following new: "
1997 << (int)nextMir->dalvikInsn.opcode;
1998 } else if (bb->fallThrough) {
1999 // Look in next basic block
2000 struct BasicBlock* nextBB = bb->fallThrough;
2001 for (MIR* tmir = nextBB->firstMIRInsn; tmir;
2002 tmir =tmir->next) {
2003 if ((int)tmir->dalvikInsn.opcode >= (int)kMirOpFirst) {
2004 continue;
2005 }
2006 // First non-pseudo should be MOVE_RESULT_OBJECT
2007 if (tmir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) {
2008 // Mark as null checked
2009 oatSetBit(cUnit, cUnit->tempSSARegisterV, tmir->ssaRep->defs[0]);
2010 } else {
2011 LOG(WARNING) << "Unexpected op after new: "
2012 << (int)tmir->dalvikInsn.opcode;
2013 }
2014 break;
2015 }
2016 }
2017 }
2018 }
buzbee5abfa3e2012-01-31 17:01:43 -0800[diff] [blame]2019
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2020 /*
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2021 * Propagate nullcheck state on register copies (including
2022 * Phi pseudo copies. For the latter, nullcheck state is
2023 * the "and" of all the Phi's operands.
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2024 */
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2025 if (dfAttributes & (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N)) {
2026 int tgtSreg = mir->ssaRep->defs[0];
2027 int operands = (dfAttributes & DF_NULL_TRANSFER_0) ? 1 :
2028 mir->ssaRep->numUses;
2029 bool nullChecked = true;
2030 for (int i = 0; i < operands; i++) {
2031 nullChecked &= oatIsBitSet(cUnit->tempSSARegisterV,
2032 mir->ssaRep->uses[i]);
2033 }
2034 if (nullChecked) {
2035 oatSetBit(cUnit, cUnit->tempSSARegisterV, tgtSreg);
2036 }
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2037 }
2038
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2039 // Already nullchecked?
2040 if (dfAttributes & DF_HAS_NULL_CHKS) {
2041 int srcIdx;
2042 if (dfAttributes & DF_NULL_CHK_1) {
2043 srcIdx = 1;
2044 } else if (dfAttributes & DF_NULL_CHK_2) {
2045 srcIdx = 2;
2046 } else {
2047 srcIdx = 0;
2048 }
2049 int srcSreg = mir->ssaRep->uses[srcIdx];
2050 if (oatIsBitSet(cUnit->tempSSARegisterV, srcSreg)) {
2051 // Eliminate the null check
2052 mir->optimizationFlags |= MIR_IGNORE_NULL_CHECK;
2053 } else {
2054 // Mark sReg as null-checked
2055 oatSetBit(cUnit, cUnit->tempSSARegisterV, srcSreg);
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2056 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2057 }
2058 }
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2059
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2060 // Did anything change?
2061 bool res = oatCompareBitVectors(bb->dataFlowInfo->endingNullCheckV,
2062 cUnit->tempSSARegisterV);
2063 if (res) {
2064 oatCopyBitVector(bb->dataFlowInfo->endingNullCheckV,
2065 cUnit->tempSSARegisterV);
2066 }
2067 return res;
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2068}
2069
2070void oatMethodNullCheckElimination(CompilationUnit *cUnit)
2071{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2072 if (!(cUnit->disableOpt & (1 << kNullCheckElimination))) {
2073 DCHECK(cUnit->tempSSARegisterV != NULL);
2074 oatDataFlowAnalysisDispatcher(cUnit, nullCheckEliminationInit, kAllNodes,
2075 false /* isIterative */);
2076 oatDataFlowAnalysisDispatcher(cUnit, eliminateNullChecks,
2077 kPreOrderDFSTraversal,
2078 true /* isIterative */);
2079 }
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2080}
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]2081
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]2082void oatMethodBasicBlockOptimization(CompilationUnit *cUnit)
2083{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2084 if (!(cUnit->disableOpt & (1 << kBBOpt))) {
2085 oatInitGrowableList(cUnit, &cUnit->compilerTemps, 6, kListMisc);
2086 DCHECK_EQ(cUnit->numCompilerTemps, 0);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]2087 if (!(cUnit->disableOpt & (1 << kBBOpt))) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2088 oatDataFlowAnalysisDispatcher(cUnit, basicBlockOpt,
2089 kAllNodes, false /* isIterative */);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]2090 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2091 }
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]2092}
2093
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2094void addLoopHeader(CompilationUnit* cUnit, BasicBlock* header,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2095 BasicBlock* backEdge)
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2096{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2097 GrowableListIterator iter;
2098 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2099 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2100 (loop != NULL); loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2101 if (loop->header == header) {
2102 oatInsertGrowableList(cUnit, &loop->incomingBackEdges,
2103 (intptr_t)backEdge);
2104 return;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2105 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2106 }
2107 LoopInfo* info = (LoopInfo*)oatNew(cUnit, sizeof(LoopInfo), true,
2108 kAllocDFInfo);
2109 info->header = header;
2110 oatInitGrowableList(cUnit, &info->incomingBackEdges, 2, kListMisc);
2111 oatInsertGrowableList(cUnit, &info->incomingBackEdges, (intptr_t)backEdge);
2112 oatInsertGrowableList(cUnit, &cUnit->loopHeaders, (intptr_t)info);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2113}
2114
2115bool findBackEdges(struct CompilationUnit* cUnit, struct BasicBlock* bb)
2116{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2117 if ((bb->dataFlowInfo == NULL) || (bb->lastMIRInsn == NULL)) {
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2118 return false;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2119 }
2120 Instruction::Code opcode = bb->lastMIRInsn->dalvikInsn.opcode;
2121 if (Instruction::Flags(opcode) & Instruction::kBranch) {
2122 if (bb->taken && (bb->taken->startOffset <= bb->startOffset)) {
2123 DCHECK(bb->dominators != NULL);
2124 if (oatIsBitSet(bb->dominators, bb->taken->id)) {
2125 if (cUnit->printMe) {
2126 LOG(INFO) << "Loop backedge from 0x"
2127 << std::hex << bb->lastMIRInsn->offset
2128 << " to 0x" << std::hex << bb->taken->startOffset;
2129 }
2130 addLoopHeader(cUnit, bb->taken, bb);
2131 }
2132 }
2133 }
2134 return false;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2135}
2136
2137void addBlocksToLoop(CompilationUnit* cUnit, ArenaBitVector* blocks,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2138 BasicBlock* bb, int headId)
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2139{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2140 if (!oatIsBitSet(bb->dominators, headId) ||
2141 oatIsBitSet(blocks, bb->id)) {
2142 return;
2143 }
2144 oatSetBit(cUnit, blocks, bb->id);
2145 GrowableListIterator iter;
2146 oatGrowableListIteratorInit(bb->predecessors, &iter);
2147 BasicBlock* predBB;
2148 for (predBB = (BasicBlock*)oatGrowableListIteratorNext(&iter); predBB;
2149 predBB = (BasicBlock*)oatGrowableListIteratorNext(&iter)) {
2150 addBlocksToLoop(cUnit, blocks, predBB, headId);
2151 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2152}
2153
2154void oatDumpLoops(CompilationUnit *cUnit)
2155{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2156 GrowableListIterator iter;
2157 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2158 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2159 (loop != NULL); loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2160 LOG(INFO) << "Loop head block id " << loop->header->id
2161 << ", offset 0x" << std::hex << loop->header->startOffset
2162 << ", Depth: " << loop->header->nestingDepth;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2163 GrowableListIterator iter;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2164 oatGrowableListIteratorInit(&loop->incomingBackEdges, &iter);
2165 BasicBlock* edgeBB;
2166 for (edgeBB = (BasicBlock*)oatGrowableListIteratorNext(&iter); edgeBB;
2167 edgeBB = (BasicBlock*)oatGrowableListIteratorNext(&iter)) {
2168 LOG(INFO) << " Backedge block id " << edgeBB->id
2169 << ", offset 0x" << std::hex << edgeBB->startOffset;
2170 ArenaBitVectorIterator bIter;
2171 oatBitVectorIteratorInit(loop->blocks, &bIter);
2172 for (int bbId = oatBitVectorIteratorNext(&bIter); bbId != -1;
2173 bbId = oatBitVectorIteratorNext(&bIter)) {
2174 BasicBlock *bb;
2175 bb = (BasicBlock*)
2176 oatGrowableListGetElement(&cUnit->blockList, bbId);
2177 LOG(INFO) << " (" << bb->id << ", 0x" << std::hex
2178 << bb->startOffset << ")";
2179 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2180 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2181 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2182}
2183
2184void oatMethodLoopDetection(CompilationUnit *cUnit)
2185{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2186 if (cUnit->disableOpt & (1 << kPromoteRegs)) {
2187 return;
2188 }
2189 oatInitGrowableList(cUnit, &cUnit->loopHeaders, 6, kListMisc);
2190 // Find the loop headers
2191 oatDataFlowAnalysisDispatcher(cUnit, findBackEdges,
2192 kAllNodes, false /* isIterative */);
2193 GrowableListIterator iter;
2194 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2195 // Add blocks to each header
2196 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2197 loop; loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2198 loop->blocks = oatAllocBitVector(cUnit, cUnit->numBlocks, true,
2199 kBitMapMisc);
2200 oatSetBit(cUnit, loop->blocks, loop->header->id);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2201 GrowableListIterator iter;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2202 oatGrowableListIteratorInit(&loop->incomingBackEdges, &iter);
2203 BasicBlock* edgeBB;
2204 for (edgeBB = (BasicBlock*)oatGrowableListIteratorNext(&iter); edgeBB;
2205 edgeBB = (BasicBlock*)oatGrowableListIteratorNext(&iter)) {
2206 addBlocksToLoop(cUnit, loop->blocks, edgeBB, loop->header->id);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2207 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2208 }
2209 // Compute the nesting depth of each header
2210 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2211 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2212 loop; loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2213 GrowableListIterator iter2;
2214 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter2);
2215 LoopInfo* loop2;
2216 for (loop2 = (LoopInfo*)oatGrowableListIteratorNext(&iter2);
2217 loop2; loop2 = (LoopInfo*)oatGrowableListIteratorNext(&iter2)) {
2218 if (oatIsBitSet(loop2->blocks, loop->header->id)) {
2219 loop->header->nestingDepth++;
2220 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2221 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2222 }
2223 // Assign nesting depth to each block in all loops
2224 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2225 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2226 (loop != NULL); loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2227 ArenaBitVectorIterator bIter;
2228 oatBitVectorIteratorInit(loop->blocks, &bIter);
2229 for (int bbId = oatBitVectorIteratorNext(&bIter); bbId != -1;
2230 bbId = oatBitVectorIteratorNext(&bIter)) {
2231 BasicBlock *bb;
2232 bb = (BasicBlock*) oatGrowableListGetElement(&cUnit->blockList, bbId);
2233 bb->nestingDepth = std::max(bb->nestingDepth,
2234 loop->header->nestingDepth);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2235 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2236 }
2237 if (cUnit->printMe) {
2238 oatDumpLoops(cUnit);
2239 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2240}
2241
2242/*
buzbee9c044ce2012-03-18 13:24:07 -0700[diff] [blame]2243 * This function will make a best guess at whether the invoke will
2244 * end up using Method*. It isn't critical to get it exactly right,
2245 * and attempting to do would involve more complexity than it's
2246 * worth.
2247 */
2248bool invokeUsesMethodStar(CompilationUnit* cUnit, MIR* mir)
2249{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2250 InvokeType type;
2251 Instruction::Code opcode = mir->dalvikInsn.opcode;
2252 switch (opcode) {
2253 case Instruction::INVOKE_STATIC:
2254 case Instruction::INVOKE_STATIC_RANGE:
2255 type = kStatic;
2256 break;
2257 case Instruction::INVOKE_DIRECT:
2258 case Instruction::INVOKE_DIRECT_RANGE:
2259 type = kDirect;
2260 break;
2261 case Instruction::INVOKE_VIRTUAL:
2262 case Instruction::INVOKE_VIRTUAL_RANGE:
2263 type = kVirtual;
2264 break;
2265 case Instruction::INVOKE_INTERFACE:
2266 case Instruction::INVOKE_INTERFACE_RANGE:
2267 return false;
2268 case Instruction::INVOKE_SUPER_RANGE:
2269 case Instruction::INVOKE_SUPER:
2270 type = kSuper;
2271 break;
2272 default:
2273 LOG(WARNING) << "Unexpected invoke op: " << (int)opcode;
2274 return false;
2275 }
2276 OatCompilationUnit mUnit(cUnit->class_loader, cUnit->class_linker,
2277 *cUnit->dex_file, *cUnit->dex_cache,
2278 cUnit->code_item, cUnit->method_idx,
2279 cUnit->access_flags);
2280 // TODO: add a flag so we don't counts the stats for this twice
2281 uint32_t dexMethodIdx = mir->dalvikInsn.vB;
2282 int vtableIdx;
2283 uintptr_t directCode;
2284 uintptr_t directMethod;
2285 bool fastPath =
2286 cUnit->compiler->ComputeInvokeInfo(dexMethodIdx, &mUnit, type,
2287 vtableIdx, directCode,
2288 directMethod) &&
2289 !SLOW_INVOKE_PATH;
2290 return (((type == kDirect) || (type == kStatic)) &&
2291 fastPath && ((directCode == 0) || (directMethod == 0)));
buzbee9c044ce2012-03-18 13:24:07 -0700[diff] [blame]2292}
2293
2294/*
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2295 * Count uses, weighting by loop nesting depth. This code only
2296 * counts explicitly used sRegs. A later phase will add implicit
2297 * counts for things such as Method*, null-checked references, etc.
2298 */
2299bool countUses(struct CompilationUnit* cUnit, struct BasicBlock* bb)
2300{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2301 if (bb->blockType != kDalvikByteCode) {
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2302 return false;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2303 }
2304 for (MIR* mir = bb->firstMIRInsn; (mir != NULL); mir = mir->next) {
2305 if (mir->ssaRep == NULL) {
2306 continue;
2307 }
2308 uint32_t weight = std::min(16U, (uint32_t)bb->nestingDepth);
2309 for (int i = 0; i < mir->ssaRep->numUses; i++) {
2310 int sReg = mir->ssaRep->uses[i];
2311 DCHECK_LT(sReg, (int)cUnit->useCounts.numUsed);
2312 cUnit->rawUseCounts.elemList[sReg]++;
2313 cUnit->useCounts.elemList[sReg] += (1 << weight);
2314 }
2315 if (!(cUnit->disableOpt & (1 << kPromoteCompilerTemps))) {
2316 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
2317 // Implicit use of Method* ? */
2318 if (dfAttributes & DF_UMS) {
2319 /*
2320 * Some invokes will not use Method* - need to perform test similar
2321 * to that found in genInvoke() to decide whether to count refs
2322 * for Method* on invoke-class opcodes.
2323 * TODO: refactor for common test here, save results for genInvoke
2324 */
2325 int usesMethodStar = true;
2326 if ((dfAttributes & (DF_FORMAT_35C | DF_FORMAT_3RC)) &&
2327 !(dfAttributes & DF_NON_NULL_RET)) {
2328 usesMethodStar &= invokeUsesMethodStar(cUnit, mir);
2329 }
2330 if (usesMethodStar) {
2331 cUnit->rawUseCounts.elemList[cUnit->methodSReg]++;
2332 cUnit->useCounts.elemList[cUnit->methodSReg] += (1 << weight);
2333 }
2334 }
2335 }
2336 }
2337 return false;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2338}
2339
2340void oatMethodUseCount(CompilationUnit *cUnit)
2341{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2342 oatInitGrowableList(cUnit, &cUnit->useCounts, cUnit->numSSARegs + 32,
2343 kListMisc);
2344 oatInitGrowableList(cUnit, &cUnit->rawUseCounts, cUnit->numSSARegs + 32,
2345 kListMisc);
2346 // Initialize list
2347 for (int i = 0; i < cUnit->numSSARegs; i++) {
2348 oatInsertGrowableList(cUnit, &cUnit->useCounts, 0);
2349 oatInsertGrowableList(cUnit, &cUnit->rawUseCounts, 0);
2350 }
2351 if (cUnit->disableOpt & (1 << kPromoteRegs)) {
2352 return;
2353 }
2354 oatDataFlowAnalysisDispatcher(cUnit, countUses,
2355 kAllNodes, false /* isIterative */);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2356}
2357
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]2358} // namespace art