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buzbeeefc63692012-11-14 16:31:52 -08001/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/* This file contains codegen for the X86 ISA */
18
buzbee1bc37c62012-11-20 13:35:41 -080019#include "x86_lir.h"
buzbee02031b12012-11-23 09:41:35 -080020#include "codegen_x86.h"
buzbee1bc37c62012-11-20 13:35:41 -080021#include "../codegen_util.h"
22#include "../ralloc_util.h"
23
buzbeeefc63692012-11-14 16:31:52 -080024namespace art {
25
buzbee02031b12012-11-23 09:41:35 -080026void X86Codegen::GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
27 SpecialCaseHandler special_case)
buzbeeefc63692012-11-14 16:31:52 -080028{
29 // TODO
30}
31
32/*
33 * The sparse table in the literal pool is an array of <key,displacement>
34 * pairs.
35 */
buzbee02031b12012-11-23 09:41:35 -080036void X86Codegen::GenSparseSwitch(CompilationUnit* cu, uint32_t table_offset, RegLocation rl_src)
buzbeeefc63692012-11-14 16:31:52 -080037{
buzbeefa57c472012-11-21 12:06:18 -080038 const uint16_t* table = cu->insns + cu->current_dalvik_offset + table_offset;
39 if (cu->verbose) {
buzbee52a77fc2012-11-20 19:50:46 -080040 DumpSparseSwitchTable(table);
buzbeeefc63692012-11-14 16:31:52 -080041 }
42 int entries = table[1];
buzbeecbd6d442012-11-17 14:11:25 -080043 const int* keys = reinterpret_cast<const int*>(&table[2]);
44 const int* targets = &keys[entries];
buzbeefa57c472012-11-21 12:06:18 -080045 rl_src = LoadValue(cu, rl_src, kCoreReg);
buzbeeefc63692012-11-14 16:31:52 -080046 for (int i = 0; i < entries; i++) {
47 int key = keys[i];
buzbee02031b12012-11-23 09:41:35 -080048 BasicBlock* case_block = FindBlock(cu, cu->current_dalvik_offset + targets[i]);
buzbeefa57c472012-11-21 12:06:18 -080049 LIR* label_list = cu->block_label_list;
50 OpCmpImmBranch(cu, kCondEq, rl_src.low_reg, key,
51 &label_list[case_block->id]);
buzbeeefc63692012-11-14 16:31:52 -080052 }
53}
54
55/*
56 * Code pattern will look something like:
57 *
buzbeefa57c472012-11-21 12:06:18 -080058 * mov r_val, ..
buzbeeefc63692012-11-14 16:31:52 -080059 * call 0
buzbeefa57c472012-11-21 12:06:18 -080060 * pop r_start_of_method
61 * sub r_start_of_method, ..
62 * mov r_key_reg, r_val
63 * sub r_key_reg, low_key
64 * cmp r_key_reg, size-1 ; bound check
buzbeeefc63692012-11-14 16:31:52 -080065 * ja done
buzbeefa57c472012-11-21 12:06:18 -080066 * mov r_disp, [r_start_of_method + r_key_reg * 4 + table_offset]
67 * add r_start_of_method, r_disp
68 * jmp r_start_of_method
buzbeeefc63692012-11-14 16:31:52 -080069 * done:
70 */
buzbee02031b12012-11-23 09:41:35 -080071void X86Codegen::GenPackedSwitch(CompilationUnit* cu, uint32_t table_offset, RegLocation rl_src)
buzbeeefc63692012-11-14 16:31:52 -080072{
buzbeefa57c472012-11-21 12:06:18 -080073 const uint16_t* table = cu->insns + cu->current_dalvik_offset + table_offset;
74 if (cu->verbose) {
buzbee52a77fc2012-11-20 19:50:46 -080075 DumpPackedSwitchTable(table);
buzbeeefc63692012-11-14 16:31:52 -080076 }
77 // Add the table to the list - we'll process it later
buzbeefa57c472012-11-21 12:06:18 -080078 SwitchTable *tab_rec =
79 static_cast<SwitchTable *>(NewMem(cu, sizeof(SwitchTable), true, kAllocData));
80 tab_rec->table = table;
81 tab_rec->vaddr = cu->current_dalvik_offset;
buzbeeefc63692012-11-14 16:31:52 -080082 int size = table[1];
buzbeefa57c472012-11-21 12:06:18 -080083 tab_rec->targets = static_cast<LIR**>(NewMem(cu, size * sizeof(LIR*), true, kAllocLIR));
84 InsertGrowableList(cu, &cu->switch_tables, reinterpret_cast<uintptr_t>(tab_rec));
buzbeeefc63692012-11-14 16:31:52 -080085
86 // Get the switch value
buzbeefa57c472012-11-21 12:06:18 -080087 rl_src = LoadValue(cu, rl_src, kCoreReg);
88 int start_of_method_reg = AllocTemp(cu);
buzbeeefc63692012-11-14 16:31:52 -080089 // Materialize a pointer to the switch table
buzbeefa57c472012-11-21 12:06:18 -080090 //NewLIR0(cu, kX86Bkpt);
91 NewLIR1(cu, kX86StartOfMethod, start_of_method_reg);
92 int low_key = s4FromSwitchData(&table[2]);
buzbeeefc63692012-11-14 16:31:52 -080093 int keyReg;
94 // Remove the bias, if necessary
buzbeefa57c472012-11-21 12:06:18 -080095 if (low_key == 0) {
96 keyReg = rl_src.low_reg;
buzbeeefc63692012-11-14 16:31:52 -080097 } else {
buzbeefa57c472012-11-21 12:06:18 -080098 keyReg = AllocTemp(cu);
99 OpRegRegImm(cu, kOpSub, keyReg, rl_src.low_reg, low_key);
buzbeeefc63692012-11-14 16:31:52 -0800100 }
101 // Bounds check - if < 0 or >= size continue following switch
buzbeefa57c472012-11-21 12:06:18 -0800102 OpRegImm(cu, kOpCmp, keyReg, size-1);
103 LIR* branch_over = OpCondBranch(cu, kCondHi, NULL);
buzbeeefc63692012-11-14 16:31:52 -0800104
105 // Load the displacement from the switch table
buzbeefa57c472012-11-21 12:06:18 -0800106 int disp_reg = AllocTemp(cu);
107 NewLIR5(cu, kX86PcRelLoadRA, disp_reg, start_of_method_reg, keyReg, 2,
108 reinterpret_cast<uintptr_t>(tab_rec));
buzbeeefc63692012-11-14 16:31:52 -0800109 // Add displacement to start of method
buzbeefa57c472012-11-21 12:06:18 -0800110 OpRegReg(cu, kOpAdd, start_of_method_reg, disp_reg);
buzbeeefc63692012-11-14 16:31:52 -0800111 // ..and go!
buzbeefa57c472012-11-21 12:06:18 -0800112 LIR* switch_branch = NewLIR1(cu, kX86JmpR, start_of_method_reg);
113 tab_rec->anchor = switch_branch;
buzbeeefc63692012-11-14 16:31:52 -0800114
buzbeefa57c472012-11-21 12:06:18 -0800115 /* branch_over target here */
116 LIR* target = NewLIR0(cu, kPseudoTargetLabel);
117 branch_over->target = target;
buzbeeefc63692012-11-14 16:31:52 -0800118}
119
buzbeeefc63692012-11-14 16:31:52 -0800120/*
121 * Array data table format:
122 * ushort ident = 0x0300 magic value
123 * ushort width width of each element in the table
124 * uint size number of elements in the table
125 * ubyte data[size*width] table of data values (may contain a single-byte
126 * padding at the end)
127 *
128 * Total size is 4+(width * size + 1)/2 16-bit code units.
129 */
buzbee02031b12012-11-23 09:41:35 -0800130void X86Codegen::GenFillArrayData(CompilationUnit* cu, uint32_t table_offset, RegLocation rl_src)
buzbeeefc63692012-11-14 16:31:52 -0800131{
buzbeefa57c472012-11-21 12:06:18 -0800132 const uint16_t* table = cu->insns + cu->current_dalvik_offset + table_offset;
buzbeeefc63692012-11-14 16:31:52 -0800133 // Add the table to the list - we'll process it later
buzbeefa57c472012-11-21 12:06:18 -0800134 FillArrayData *tab_rec =
135 static_cast<FillArrayData*>(NewMem(cu, sizeof(FillArrayData), true, kAllocData));
136 tab_rec->table = table;
137 tab_rec->vaddr = cu->current_dalvik_offset;
138 uint16_t width = tab_rec->table[1];
139 uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16);
140 tab_rec->size = (size * width) + 8;
buzbeeefc63692012-11-14 16:31:52 -0800141
buzbeefa57c472012-11-21 12:06:18 -0800142 InsertGrowableList(cu, &cu->fill_array_data, reinterpret_cast<uintptr_t>(tab_rec));
buzbeeefc63692012-11-14 16:31:52 -0800143
144 // Making a call - use explicit registers
buzbeefa57c472012-11-21 12:06:18 -0800145 FlushAllRegs(cu); /* Everything to home location */
146 LoadValueDirectFixed(cu, rl_src, rX86_ARG0);
buzbeeefc63692012-11-14 16:31:52 -0800147 // Materialize a pointer to the fill data image
buzbeefa57c472012-11-21 12:06:18 -0800148 NewLIR1(cu, kX86StartOfMethod, rX86_ARG2);
149 NewLIR2(cu, kX86PcRelAdr, rX86_ARG1, reinterpret_cast<uintptr_t>(tab_rec));
150 NewLIR2(cu, kX86Add32RR, rX86_ARG1, rX86_ARG2);
151 CallRuntimeHelperRegReg(cu, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode), rX86_ARG0,
buzbeecbd6d442012-11-17 14:11:25 -0800152 rX86_ARG1, true);
buzbeeefc63692012-11-14 16:31:52 -0800153}
154
buzbee02031b12012-11-23 09:41:35 -0800155void X86Codegen::GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src)
buzbeeefc63692012-11-14 16:31:52 -0800156{
buzbeefa57c472012-11-21 12:06:18 -0800157 FlushAllRegs(cu);
158 LoadValueDirectFixed(cu, rl_src, rCX); // Get obj
159 LockCallTemps(cu); // Prepare for explicit register usage
160 GenNullCheck(cu, rl_src.s_reg_low, rCX, opt_flags);
buzbeeefc63692012-11-14 16:31:52 -0800161 // If lock is unheld, try to grab it quickly with compare and exchange
162 // TODO: copy and clear hash state?
buzbeefa57c472012-11-21 12:06:18 -0800163 NewLIR2(cu, kX86Mov32RT, rDX, Thread::ThinLockIdOffset().Int32Value());
164 NewLIR2(cu, kX86Sal32RI, rDX, LW_LOCK_OWNER_SHIFT);
165 NewLIR2(cu, kX86Xor32RR, rAX, rAX);
Ian Rogers2dd0e2c2013-01-24 12:42:14 -0800166 NewLIR3(cu, kX86LockCmpxchgMR, rCX, mirror::Object::MonitorOffset().Int32Value(), rDX);
buzbeefa57c472012-11-21 12:06:18 -0800167 LIR* branch = NewLIR2(cu, kX86Jcc8, 0, kX86CondEq);
buzbeeefc63692012-11-14 16:31:52 -0800168 // If lock is held, go the expensive route - artLockObjectFromCode(self, obj);
buzbeefa57c472012-11-21 12:06:18 -0800169 CallRuntimeHelperReg(cu, ENTRYPOINT_OFFSET(pLockObjectFromCode), rCX, true);
170 branch->target = NewLIR0(cu, kPseudoTargetLabel);
buzbeeefc63692012-11-14 16:31:52 -0800171}
172
buzbee02031b12012-11-23 09:41:35 -0800173void X86Codegen::GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src)
buzbeeefc63692012-11-14 16:31:52 -0800174{
buzbeefa57c472012-11-21 12:06:18 -0800175 FlushAllRegs(cu);
176 LoadValueDirectFixed(cu, rl_src, rAX); // Get obj
177 LockCallTemps(cu); // Prepare for explicit register usage
178 GenNullCheck(cu, rl_src.s_reg_low, rAX, opt_flags);
buzbeeefc63692012-11-14 16:31:52 -0800179 // If lock is held by the current thread, clear it to quickly release it
180 // TODO: clear hash state?
buzbeefa57c472012-11-21 12:06:18 -0800181 NewLIR2(cu, kX86Mov32RT, rDX, Thread::ThinLockIdOffset().Int32Value());
182 NewLIR2(cu, kX86Sal32RI, rDX, LW_LOCK_OWNER_SHIFT);
Ian Rogers2dd0e2c2013-01-24 12:42:14 -0800183 NewLIR3(cu, kX86Mov32RM, rCX, rAX, mirror::Object::MonitorOffset().Int32Value());
buzbeefa57c472012-11-21 12:06:18 -0800184 OpRegReg(cu, kOpSub, rCX, rDX);
185 LIR* branch = NewLIR2(cu, kX86Jcc8, 0, kX86CondNe);
Ian Rogers2dd0e2c2013-01-24 12:42:14 -0800186 NewLIR3(cu, kX86Mov32MR, rAX, mirror::Object::MonitorOffset().Int32Value(), rCX);
buzbeefa57c472012-11-21 12:06:18 -0800187 LIR* branch2 = NewLIR1(cu, kX86Jmp8, 0);
188 branch->target = NewLIR0(cu, kPseudoTargetLabel);
buzbeeefc63692012-11-14 16:31:52 -0800189 // Otherwise, go the expensive route - UnlockObjectFromCode(obj);
buzbeefa57c472012-11-21 12:06:18 -0800190 CallRuntimeHelperReg(cu, ENTRYPOINT_OFFSET(pUnlockObjectFromCode), rAX, true);
191 branch2->target = NewLIR0(cu, kPseudoTargetLabel);
buzbeeefc63692012-11-14 16:31:52 -0800192}
193
jeffhao1eab9582013-01-22 13:33:52 -0800194void X86Codegen::GenMoveException(CompilationUnit* cu, RegLocation rl_dest)
195{
196 int ex_offset = Thread::ExceptionOffset().Int32Value();
197 RegLocation rl_result = EvalLoc(cu, rl_dest, kCoreReg, true);
198 NewLIR2(cu, kX86Mov32RT, rl_result.low_reg, ex_offset);
199 NewLIR2(cu, kX86Mov32TI, ex_offset, 0);
200 StoreValue(cu, rl_dest, rl_result);
201}
202
buzbeeefc63692012-11-14 16:31:52 -0800203/*
204 * Mark garbage collection card. Skip if the value we're storing is null.
205 */
buzbee02031b12012-11-23 09:41:35 -0800206void X86Codegen::MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg)
buzbeeefc63692012-11-14 16:31:52 -0800207{
buzbeefa57c472012-11-21 12:06:18 -0800208 int reg_card_base = AllocTemp(cu);
209 int reg_card_no = AllocTemp(cu);
210 LIR* branch_over = OpCmpImmBranch(cu, kCondEq, val_reg, 0, NULL);
211 NewLIR2(cu, kX86Mov32RT, reg_card_base, Thread::CardTableOffset().Int32Value());
212 OpRegRegImm(cu, kOpLsr, reg_card_no, tgt_addr_reg, CardTable::kCardShift);
213 StoreBaseIndexed(cu, reg_card_base, reg_card_no, reg_card_base, 0,
buzbeeefc63692012-11-14 16:31:52 -0800214 kUnsignedByte);
buzbeefa57c472012-11-21 12:06:18 -0800215 LIR* target = NewLIR0(cu, kPseudoTargetLabel);
216 branch_over->target = target;
217 FreeTemp(cu, reg_card_base);
218 FreeTemp(cu, reg_card_no);
buzbeeefc63692012-11-14 16:31:52 -0800219}
220
buzbee02031b12012-11-23 09:41:35 -0800221void X86Codegen::GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs, RegLocation rl_method)
buzbeeefc63692012-11-14 16:31:52 -0800222{
223 /*
224 * On entry, rX86_ARG0, rX86_ARG1, rX86_ARG2 are live. Let the register
225 * allocation mechanism know so it doesn't try to use any of them when
226 * expanding the frame or flushing. This leaves the utility
227 * code with no spare temps.
228 */
buzbeefa57c472012-11-21 12:06:18 -0800229 LockTemp(cu, rX86_ARG0);
230 LockTemp(cu, rX86_ARG1);
231 LockTemp(cu, rX86_ARG2);
buzbeeefc63692012-11-14 16:31:52 -0800232
233 /* Build frame, return address already on stack */
buzbeefa57c472012-11-21 12:06:18 -0800234 OpRegImm(cu, kOpSub, rX86_SP, cu->frame_size - 4);
buzbeeefc63692012-11-14 16:31:52 -0800235
236 /*
237 * We can safely skip the stack overflow check if we're
238 * a leaf *and* our frame size < fudge factor.
239 */
buzbeefa57c472012-11-21 12:06:18 -0800240 bool skip_overflow_check = ((cu->attrs & METHOD_IS_LEAF) &&
241 (static_cast<size_t>(cu->frame_size) <
buzbeeefc63692012-11-14 16:31:52 -0800242 Thread::kStackOverflowReservedBytes));
buzbeefa57c472012-11-21 12:06:18 -0800243 NewLIR0(cu, kPseudoMethodEntry);
buzbeeefc63692012-11-14 16:31:52 -0800244 /* Spill core callee saves */
buzbeefa57c472012-11-21 12:06:18 -0800245 SpillCoreRegs(cu);
buzbeeefc63692012-11-14 16:31:52 -0800246 /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
buzbeefa57c472012-11-21 12:06:18 -0800247 DCHECK_EQ(cu->num_fp_spills, 0);
248 if (!skip_overflow_check) {
buzbeeefc63692012-11-14 16:31:52 -0800249 // cmp rX86_SP, fs:[stack_end_]; jcc throw_launchpad
buzbeefa57c472012-11-21 12:06:18 -0800250 LIR* tgt = RawLIR(cu, 0, kPseudoThrowTarget, kThrowStackOverflow, 0, 0, 0, 0);
251 OpRegThreadMem(cu, kOpCmp, rX86_SP, Thread::StackEndOffset().Int32Value());
252 OpCondBranch(cu, kCondUlt, tgt);
buzbeeefc63692012-11-14 16:31:52 -0800253 // Remember branch target - will process later
buzbeefa57c472012-11-21 12:06:18 -0800254 InsertGrowableList(cu, &cu->throw_launchpads, reinterpret_cast<uintptr_t>(tgt));
buzbeeefc63692012-11-14 16:31:52 -0800255 }
256
buzbeefa57c472012-11-21 12:06:18 -0800257 FlushIns(cu, ArgLocs, rl_method);
buzbeeefc63692012-11-14 16:31:52 -0800258
buzbeefa57c472012-11-21 12:06:18 -0800259 FreeTemp(cu, rX86_ARG0);
260 FreeTemp(cu, rX86_ARG1);
261 FreeTemp(cu, rX86_ARG2);
buzbeeefc63692012-11-14 16:31:52 -0800262}
263
buzbee02031b12012-11-23 09:41:35 -0800264void X86Codegen::GenExitSequence(CompilationUnit* cu) {
buzbeeefc63692012-11-14 16:31:52 -0800265 /*
266 * In the exit path, rX86_RET0/rX86_RET1 are live - make sure they aren't
267 * allocated by the register utilities as temps.
268 */
buzbeefa57c472012-11-21 12:06:18 -0800269 LockTemp(cu, rX86_RET0);
270 LockTemp(cu, rX86_RET1);
buzbeeefc63692012-11-14 16:31:52 -0800271
buzbeefa57c472012-11-21 12:06:18 -0800272 NewLIR0(cu, kPseudoMethodExit);
273 UnSpillCoreRegs(cu);
buzbeeefc63692012-11-14 16:31:52 -0800274 /* Remove frame except for return address */
buzbeefa57c472012-11-21 12:06:18 -0800275 OpRegImm(cu, kOpAdd, rX86_SP, cu->frame_size - 4);
276 NewLIR0(cu, kX86Ret);
buzbeeefc63692012-11-14 16:31:52 -0800277}
278
279} // namespace art