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Brian Carlstrom7940e442013-07-12 13:46:57 -07001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/* This file contains codegen for the Thumb2 ISA. */
18
19#include "arm_lir.h"
20#include "codegen_arm.h"
21#include "dex/quick/mir_to_lir-inl.h"
Ian Rogers166db042013-07-26 12:05:57 -070022#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom7940e442013-07-12 13:46:57 -070023#include "mirror/array.h"
Brian Carlstrom7940e442013-07-12 13:46:57 -070024
25namespace art {
26
buzbee2700f7e2014-03-07 09:46:20 -080027LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070028 OpRegReg(kOpCmp, src1, src2);
29 return OpCondBranch(cond, target);
30}
31
32/*
33 * Generate a Thumb2 IT instruction, which can nullify up to
34 * four subsequent instructions based on a condition and its
35 * inverse. The condition applies to the first instruction, which
36 * is executed if the condition is met. The string "guide" consists
37 * of 0 to 3 chars, and applies to the 2nd through 4th instruction.
38 * A "T" means the instruction is executed if the condition is
39 * met, and an "E" means the instruction is executed if the condition
40 * is not met.
41 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -070042LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070043 int mask;
44 int mask3 = 0;
45 int mask2 = 0;
46 int mask1 = 0;
47 ArmConditionCode code = ArmConditionEncoding(ccode);
48 int cond_bit = code & 1;
49 int alt_bit = cond_bit ^ 1;
50
Brian Carlstrom7934ac22013-07-26 10:54:15 -070051 // Note: case fallthroughs intentional
Brian Carlstrom7940e442013-07-12 13:46:57 -070052 switch (strlen(guide)) {
53 case 3:
54 mask1 = (guide[2] == 'T') ? cond_bit : alt_bit;
55 case 2:
56 mask2 = (guide[1] == 'T') ? cond_bit : alt_bit;
57 case 1:
58 mask3 = (guide[0] == 'T') ? cond_bit : alt_bit;
59 break;
60 case 0:
61 break;
62 default:
63 LOG(FATAL) << "OAT: bad case in OpIT";
64 }
65 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) |
66 (1 << (3 - strlen(guide)));
67 return NewLIR2(kThumb2It, code, mask);
68}
69
70/*
71 * 64-bit 3way compare function.
72 * mov rX, #-1
73 * cmp op1hi, op2hi
74 * blt done
75 * bgt flip
76 * sub rX, op1lo, op2lo (treat as unsigned)
77 * beq done
78 * ite hi
79 * mov(hi) rX, #-1
80 * mov(!hi) rX, #1
81 * flip:
82 * neg rX
83 * done:
84 */
85void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -070086 RegLocation rl_src2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070087 LIR* target1;
88 LIR* target2;
89 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
90 rl_src2 = LoadValueWide(rl_src2, kCoreReg);
buzbee2700f7e2014-03-07 09:46:20 -080091 RegStorage t_reg = AllocTemp();
Brian Carlstrom7940e442013-07-12 13:46:57 -070092 LoadConstant(t_reg, -1);
buzbee2700f7e2014-03-07 09:46:20 -080093 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh());
Brian Carlstrom7940e442013-07-12 13:46:57 -070094 LIR* branch1 = OpCondBranch(kCondLt, NULL);
95 LIR* branch2 = OpCondBranch(kCondGt, NULL);
buzbee2700f7e2014-03-07 09:46:20 -080096 OpRegRegReg(kOpSub, t_reg, rl_src1.reg, rl_src2.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -070097 LIR* branch3 = OpCondBranch(kCondEq, NULL);
98
99 OpIT(kCondHi, "E");
buzbee2700f7e2014-03-07 09:46:20 -0800100 NewLIR2(kThumb2MovI8M, t_reg.GetReg(), ModifiedImmediate(-1));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700101 LoadConstant(t_reg, 1);
102 GenBarrier();
103
104 target2 = NewLIR0(kPseudoTargetLabel);
105 OpRegReg(kOpNeg, t_reg, t_reg);
106
107 target1 = NewLIR0(kPseudoTargetLabel);
108
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700109 RegLocation rl_temp = LocCReturn(); // Just using as template, will change
buzbee2700f7e2014-03-07 09:46:20 -0800110 rl_temp.reg.SetReg(t_reg.GetReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700111 StoreValue(rl_dest, rl_temp);
112 FreeTemp(t_reg);
113
114 branch1->target = target1;
115 branch2->target = target2;
116 branch3->target = branch1->target;
117}
118
119void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700120 int64_t val, ConditionCode ccode) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700121 int32_t val_lo = Low32Bits(val);
122 int32_t val_hi = High32Bits(val);
Brian Carlstrom42748892013-07-18 18:04:08 -0700123 DCHECK_GE(ModifiedImmediate(val_lo), 0);
124 DCHECK_GE(ModifiedImmediate(val_hi), 0);
buzbee0d829482013-10-11 15:24:55 -0700125 LIR* taken = &block_label_list_[bb->taken];
126 LIR* not_taken = &block_label_list_[bb->fall_through];
Brian Carlstrom7940e442013-07-12 13:46:57 -0700127 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
buzbee2700f7e2014-03-07 09:46:20 -0800128 RegStorage low_reg = rl_src1.reg.GetLow();
129 RegStorage high_reg = rl_src1.reg.GetHigh();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700130
Vladimir Marko58af1f92013-12-19 13:31:15 +0000131 if (val == 0 && (ccode == kCondEq || ccode == kCondNe)) {
buzbee2700f7e2014-03-07 09:46:20 -0800132 RegStorage t_reg = AllocTemp();
133 NewLIR4(kThumb2OrrRRRs, t_reg.GetReg(), low_reg.GetReg(), high_reg.GetReg(), 0);
Vladimir Marko58af1f92013-12-19 13:31:15 +0000134 FreeTemp(t_reg);
135 OpCondBranch(ccode, taken);
136 return;
137 }
138
Brian Carlstromdf629502013-07-17 22:39:56 -0700139 switch (ccode) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700140 case kCondEq:
141 case kCondNe:
Vladimir Marko58af1f92013-12-19 13:31:15 +0000142 OpCmpImmBranch(kCondNe, high_reg, val_hi, (ccode == kCondEq) ? not_taken : taken);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700143 break;
144 case kCondLt:
145 OpCmpImmBranch(kCondLt, high_reg, val_hi, taken);
146 OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken);
Vladimir Marko58af1f92013-12-19 13:31:15 +0000147 ccode = kCondUlt;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700148 break;
149 case kCondLe:
150 OpCmpImmBranch(kCondLt, high_reg, val_hi, taken);
151 OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken);
152 ccode = kCondLs;
153 break;
154 case kCondGt:
155 OpCmpImmBranch(kCondGt, high_reg, val_hi, taken);
156 OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken);
157 ccode = kCondHi;
158 break;
159 case kCondGe:
160 OpCmpImmBranch(kCondGt, high_reg, val_hi, taken);
161 OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken);
Vladimir Marko58af1f92013-12-19 13:31:15 +0000162 ccode = kCondUge;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700163 break;
164 default:
165 LOG(FATAL) << "Unexpected ccode: " << ccode;
166 }
167 OpCmpImmBranch(ccode, low_reg, val_lo, taken);
168}
169
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700170void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700171 RegLocation rl_result;
172 RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700173 RegLocation rl_dest = mir_graph_->GetDest(mir);
174 rl_src = LoadValue(rl_src, kCoreReg);
Vladimir Markoa1a70742014-03-03 10:28:05 +0000175 ConditionCode ccode = mir->meta.ccode;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700176 if (mir->ssa_rep->num_uses == 1) {
177 // CONST case
178 int true_val = mir->dalvikInsn.vB;
179 int false_val = mir->dalvikInsn.vC;
180 rl_result = EvalLoc(rl_dest, kCoreReg, true);
Vladimir Markoa1a70742014-03-03 10:28:05 +0000181 // Change kCondNe to kCondEq for the special cases below.
182 if (ccode == kCondNe) {
183 ccode = kCondEq;
184 std::swap(true_val, false_val);
185 }
186 bool cheap_false_val = InexpensiveConstantInt(false_val);
187 if (cheap_false_val && ccode == kCondEq && (true_val == 0 || true_val == -1)) {
buzbee2700f7e2014-03-07 09:46:20 -0800188 OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val);
Vladimir Markoa1a70742014-03-03 10:28:05 +0000189 DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
190 OpIT(true_val == 0 ? kCondNe : kCondUge, "");
buzbee2700f7e2014-03-07 09:46:20 -0800191 LoadConstant(rl_result.reg, false_val);
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700192 GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact
Vladimir Markoa1a70742014-03-03 10:28:05 +0000193 } else if (cheap_false_val && ccode == kCondEq && true_val == 1) {
buzbee2700f7e2014-03-07 09:46:20 -0800194 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, 1);
Vladimir Markoa1a70742014-03-03 10:28:05 +0000195 DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
196 OpIT(kCondLs, "");
buzbee2700f7e2014-03-07 09:46:20 -0800197 LoadConstant(rl_result.reg, false_val);
Vladimir Markoa1a70742014-03-03 10:28:05 +0000198 GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact
199 } else if (cheap_false_val && InexpensiveConstantInt(true_val)) {
buzbee2700f7e2014-03-07 09:46:20 -0800200 OpRegImm(kOpCmp, rl_src.reg, 0);
Vladimir Markoa1a70742014-03-03 10:28:05 +0000201 OpIT(ccode, "E");
buzbee2700f7e2014-03-07 09:46:20 -0800202 LoadConstant(rl_result.reg, true_val);
203 LoadConstant(rl_result.reg, false_val);
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700204 GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact
Brian Carlstrom7940e442013-07-12 13:46:57 -0700205 } else {
206 // Unlikely case - could be tuned.
buzbee2700f7e2014-03-07 09:46:20 -0800207 RegStorage t_reg1 = AllocTemp();
208 RegStorage t_reg2 = AllocTemp();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700209 LoadConstant(t_reg1, true_val);
210 LoadConstant(t_reg2, false_val);
buzbee2700f7e2014-03-07 09:46:20 -0800211 OpRegImm(kOpCmp, rl_src.reg, 0);
Vladimir Markoa1a70742014-03-03 10:28:05 +0000212 OpIT(ccode, "E");
buzbee2700f7e2014-03-07 09:46:20 -0800213 OpRegCopy(rl_result.reg, t_reg1);
214 OpRegCopy(rl_result.reg, t_reg2);
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700215 GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact
Brian Carlstrom7940e442013-07-12 13:46:57 -0700216 }
217 } else {
218 // MOVE case
219 RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]];
220 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]];
221 rl_true = LoadValue(rl_true, kCoreReg);
222 rl_false = LoadValue(rl_false, kCoreReg);
223 rl_result = EvalLoc(rl_dest, kCoreReg, true);
buzbee2700f7e2014-03-07 09:46:20 -0800224 OpRegImm(kOpCmp, rl_src.reg, 0);
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000225 if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { // Is the "true" case already in place?
Vladimir Markoa1a70742014-03-03 10:28:05 +0000226 OpIT(NegateComparison(ccode), "");
buzbee2700f7e2014-03-07 09:46:20 -0800227 OpRegCopy(rl_result.reg, rl_false.reg);
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000228 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { // False case in place?
Vladimir Markoa1a70742014-03-03 10:28:05 +0000229 OpIT(ccode, "");
buzbee2700f7e2014-03-07 09:46:20 -0800230 OpRegCopy(rl_result.reg, rl_true.reg);
buzbee252254b2013-09-08 16:20:53 -0700231 } else { // Normal - select between the two.
Vladimir Markoa1a70742014-03-03 10:28:05 +0000232 OpIT(ccode, "E");
buzbee2700f7e2014-03-07 09:46:20 -0800233 OpRegCopy(rl_result.reg, rl_true.reg);
234 OpRegCopy(rl_result.reg, rl_false.reg);
buzbee252254b2013-09-08 16:20:53 -0700235 }
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700236 GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact
Brian Carlstrom7940e442013-07-12 13:46:57 -0700237 }
238 StoreValue(rl_dest, rl_result);
239}
240
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700241void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700242 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0);
243 RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2);
244 // Normalize such that if either operand is constant, src2 will be constant.
Vladimir Markoa8946072014-01-22 10:30:44 +0000245 ConditionCode ccode = mir->meta.ccode;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700246 if (rl_src1.is_const) {
Vladimir Marko58af1f92013-12-19 13:31:15 +0000247 std::swap(rl_src1, rl_src2);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700248 ccode = FlipComparisonOrder(ccode);
249 }
250 if (rl_src2.is_const) {
251 RegLocation rl_temp = UpdateLocWide(rl_src2);
252 // Do special compare/branch against simple const operand if not already in registers.
253 int64_t val = mir_graph_->ConstantValueWide(rl_src2);
254 if ((rl_temp.location != kLocPhysReg) &&
255 ((ModifiedImmediate(Low32Bits(val)) >= 0) && (ModifiedImmediate(High32Bits(val)) >= 0))) {
256 GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode);
257 return;
258 }
259 }
buzbee0d829482013-10-11 15:24:55 -0700260 LIR* taken = &block_label_list_[bb->taken];
261 LIR* not_taken = &block_label_list_[bb->fall_through];
Brian Carlstrom7940e442013-07-12 13:46:57 -0700262 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
263 rl_src2 = LoadValueWide(rl_src2, kCoreReg);
buzbee2700f7e2014-03-07 09:46:20 -0800264 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh());
Brian Carlstromdf629502013-07-17 22:39:56 -0700265 switch (ccode) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700266 case kCondEq:
267 OpCondBranch(kCondNe, not_taken);
268 break;
269 case kCondNe:
270 OpCondBranch(kCondNe, taken);
271 break;
272 case kCondLt:
273 OpCondBranch(kCondLt, taken);
274 OpCondBranch(kCondGt, not_taken);
Vladimir Marko58af1f92013-12-19 13:31:15 +0000275 ccode = kCondUlt;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700276 break;
277 case kCondLe:
278 OpCondBranch(kCondLt, taken);
279 OpCondBranch(kCondGt, not_taken);
280 ccode = kCondLs;
281 break;
282 case kCondGt:
283 OpCondBranch(kCondGt, taken);
284 OpCondBranch(kCondLt, not_taken);
285 ccode = kCondHi;
286 break;
287 case kCondGe:
288 OpCondBranch(kCondGt, taken);
289 OpCondBranch(kCondLt, not_taken);
Vladimir Marko58af1f92013-12-19 13:31:15 +0000290 ccode = kCondUge;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700291 break;
292 default:
293 LOG(FATAL) << "Unexpected ccode: " << ccode;
294 }
buzbee2700f7e2014-03-07 09:46:20 -0800295 OpRegReg(kOpCmp, rl_src1.reg.GetLow(), rl_src2.reg.GetLow());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700296 OpCondBranch(ccode, taken);
297}
298
299/*
300 * Generate a register comparison to an immediate and branch. Caller
301 * is responsible for setting branch target field.
302 */
buzbee2700f7e2014-03-07 09:46:20 -0800303LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700304 LIR* branch;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700305 ArmConditionCode arm_cond = ArmConditionEncoding(cond);
buzbeeb48819d2013-09-14 16:15:25 -0700306 /*
307 * A common use of OpCmpImmBranch is for null checks, and using the Thumb 16-bit
308 * compare-and-branch if zero is ideal if it will reach. However, because null checks
309 * branch forward to a launch pad, they will frequently not reach - and thus have to
310 * be converted to a long form during assembly (which will trigger another assembly
311 * pass). Here we estimate the branch distance for checks, and if large directly
312 * generate the long form in an attempt to avoid an extra assembly pass.
313 * TODO: consider interspersing launchpads in code following unconditional branches.
314 */
315 bool skip = ((target != NULL) && (target->opcode == kPseudoThrowTarget));
316 skip &= ((cu_->code_item->insns_size_in_code_units_ - current_dalvik_offset_) > 64);
buzbee2700f7e2014-03-07 09:46:20 -0800317 if (!skip && (ARM_LOWREG(reg.GetReg())) && (check_value == 0) &&
Brian Carlstrom7940e442013-07-12 13:46:57 -0700318 ((arm_cond == kArmCondEq) || (arm_cond == kArmCondNe))) {
319 branch = NewLIR2((arm_cond == kArmCondEq) ? kThumb2Cbz : kThumb2Cbnz,
buzbee2700f7e2014-03-07 09:46:20 -0800320 reg.GetReg(), 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700321 } else {
Vladimir Marko22479842013-11-19 17:04:50 +0000322 OpRegImm(kOpCmp, reg, check_value);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700323 branch = NewLIR2(kThumbBCond, 0, arm_cond);
324 }
325 branch->target = target;
326 return branch;
327}
328
buzbee2700f7e2014-03-07 09:46:20 -0800329LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700330 LIR* res;
331 int opcode;
buzbee2700f7e2014-03-07 09:46:20 -0800332 // If src or dest is a pair, we'll be using low reg.
333 if (r_dest.IsPair()) {
334 r_dest = r_dest.GetLow();
335 }
336 if (r_src.IsPair()) {
337 r_src = r_src.GetLow();
338 }
339 if (ARM_FPREG(r_dest.GetReg()) || ARM_FPREG(r_src.GetReg()))
Brian Carlstrom7940e442013-07-12 13:46:57 -0700340 return OpFpRegCopy(r_dest, r_src);
buzbee2700f7e2014-03-07 09:46:20 -0800341 if (ARM_LOWREG(r_dest.GetReg()) && ARM_LOWREG(r_src.GetReg()))
Brian Carlstrom7940e442013-07-12 13:46:57 -0700342 opcode = kThumbMovRR;
buzbee2700f7e2014-03-07 09:46:20 -0800343 else if (!ARM_LOWREG(r_dest.GetReg()) && !ARM_LOWREG(r_src.GetReg()))
Brian Carlstrom7940e442013-07-12 13:46:57 -0700344 opcode = kThumbMovRR_H2H;
buzbee2700f7e2014-03-07 09:46:20 -0800345 else if (ARM_LOWREG(r_dest.GetReg()))
Brian Carlstrom7940e442013-07-12 13:46:57 -0700346 opcode = kThumbMovRR_H2L;
347 else
348 opcode = kThumbMovRR_L2H;
buzbee2700f7e2014-03-07 09:46:20 -0800349 res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700350 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
351 res->flags.is_nop = true;
352 }
353 return res;
354}
355
buzbee2700f7e2014-03-07 09:46:20 -0800356LIR* ArmMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700357 LIR* res = OpRegCopyNoInsert(r_dest, r_src);
358 AppendLIR(res);
359 return res;
360}
361
buzbee2700f7e2014-03-07 09:46:20 -0800362void ArmMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) {
363 bool dest_fp = ARM_FPREG(r_dest.GetLowReg());
364 bool src_fp = ARM_FPREG(r_src.GetLowReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700365 if (dest_fp) {
366 if (src_fp) {
buzbee2700f7e2014-03-07 09:46:20 -0800367 // FIXME: handle 64-bit solo's here.
368 OpRegCopy(RegStorage::Solo64(S2d(r_dest.GetLowReg(), r_dest.GetHighReg())),
369 RegStorage::Solo64(S2d(r_src.GetLowReg(), r_src.GetHighReg())));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700370 } else {
buzbee2700f7e2014-03-07 09:46:20 -0800371 NewLIR3(kThumb2Fmdrr, S2d(r_dest.GetLowReg(), r_dest.GetHighReg()),
372 r_src.GetLowReg(), r_src.GetHighReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700373 }
374 } else {
375 if (src_fp) {
buzbee2700f7e2014-03-07 09:46:20 -0800376 NewLIR3(kThumb2Fmrrd, r_dest.GetLowReg(), r_dest.GetHighReg(), S2d(r_src.GetLowReg(),
377 r_src.GetHighReg()));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700378 } else {
379 // Handle overlap
buzbee2700f7e2014-03-07 09:46:20 -0800380 if (r_src.GetHighReg() == r_dest.GetLowReg()) {
381 DCHECK_NE(r_src.GetLowReg(), r_dest.GetHighReg());
382 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh());
383 OpRegCopy(r_dest.GetLow(), r_src.GetLow());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700384 } else {
buzbee2700f7e2014-03-07 09:46:20 -0800385 OpRegCopy(r_dest.GetLow(), r_src.GetLow());
386 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700387 }
388 }
389 }
390}
391
392// Table of magic divisors
393struct MagicTable {
394 uint32_t magic;
395 uint32_t shift;
396 DividePattern pattern;
397};
398
399static const MagicTable magic_table[] = {
400 {0, 0, DivideNone}, // 0
401 {0, 0, DivideNone}, // 1
402 {0, 0, DivideNone}, // 2
403 {0x55555556, 0, Divide3}, // 3
404 {0, 0, DivideNone}, // 4
405 {0x66666667, 1, Divide5}, // 5
406 {0x2AAAAAAB, 0, Divide3}, // 6
407 {0x92492493, 2, Divide7}, // 7
408 {0, 0, DivideNone}, // 8
409 {0x38E38E39, 1, Divide5}, // 9
410 {0x66666667, 2, Divide5}, // 10
411 {0x2E8BA2E9, 1, Divide5}, // 11
412 {0x2AAAAAAB, 1, Divide5}, // 12
413 {0x4EC4EC4F, 2, Divide5}, // 13
414 {0x92492493, 3, Divide7}, // 14
415 {0x88888889, 3, Divide7}, // 15
416};
417
418// Integer division by constant via reciprocal multiply (Hacker's Delight, 10-4)
buzbee11b63d12013-08-27 07:34:17 -0700419bool ArmMir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700420 RegLocation rl_src, RegLocation rl_dest, int lit) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700421 if ((lit < 0) || (lit >= static_cast<int>(sizeof(magic_table)/sizeof(magic_table[0])))) {
422 return false;
423 }
424 DividePattern pattern = magic_table[lit].pattern;
425 if (pattern == DivideNone) {
426 return false;
427 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700428
buzbee2700f7e2014-03-07 09:46:20 -0800429 RegStorage r_magic = AllocTemp();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700430 LoadConstant(r_magic, magic_table[lit].magic);
431 rl_src = LoadValue(rl_src, kCoreReg);
432 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
buzbee2700f7e2014-03-07 09:46:20 -0800433 RegStorage r_hi = AllocTemp();
434 RegStorage r_lo = AllocTemp();
435 NewLIR4(kThumb2Smull, r_lo.GetReg(), r_hi.GetReg(), r_magic.GetReg(), rl_src.reg.GetReg());
Brian Carlstromdf629502013-07-17 22:39:56 -0700436 switch (pattern) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700437 case Divide3:
Zheng Xu08df4b32014-03-25 14:25:52 +0000438 OpRegRegRegShift(kOpSub, rl_result.reg, r_hi, rl_src.reg, EncodeShift(kArmAsr, 31));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700439 break;
440 case Divide5:
buzbee2700f7e2014-03-07 09:46:20 -0800441 OpRegRegImm(kOpAsr, r_lo, rl_src.reg, 31);
Zheng Xu08df4b32014-03-25 14:25:52 +0000442 OpRegRegRegShift(kOpRsub, rl_result.reg, r_lo, r_hi,
443 EncodeShift(kArmAsr, magic_table[lit].shift));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700444 break;
445 case Divide7:
buzbee2700f7e2014-03-07 09:46:20 -0800446 OpRegReg(kOpAdd, r_hi, rl_src.reg);
447 OpRegRegImm(kOpAsr, r_lo, rl_src.reg, 31);
Zheng Xu08df4b32014-03-25 14:25:52 +0000448 OpRegRegRegShift(kOpRsub, rl_result.reg, r_lo, r_hi,
449 EncodeShift(kArmAsr, magic_table[lit].shift));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700450 break;
451 default:
452 LOG(FATAL) << "Unexpected pattern: " << pattern;
453 }
Zheng Xu08df4b32014-03-25 14:25:52 +0000454
455 if (!is_div) {
456 RegStorage tmp1 = r_lo;
457 EasyMultiplyOp ops[2];
458
459 bool canEasyMultiply = GetEasyMultiplyTwoOps(lit, ops);
460 DCHECK_NE(canEasyMultiply, false);
461
462 GenEasyMultiplyTwoOps(tmp1, rl_result.reg, ops);
463 OpRegRegReg(kOpSub, rl_result.reg, rl_src.reg, tmp1);
464 }
465
466 StoreValue(rl_dest, rl_result);
467 return true;
468}
469
470// Try to convert *lit to 1 RegRegRegShift/RegRegShift form.
471bool ArmMir2Lir::GetEasyMultiplyOp(int lit, ArmMir2Lir::EasyMultiplyOp* op) {
472 if (IsPowerOfTwo(lit)) {
473 op->op = kOpLsl;
474 op->shift = LowestSetBit(lit);
475 return true;
476 }
477
478 if (IsPowerOfTwo(lit - 1)) {
479 op->op = kOpAdd;
480 op->shift = LowestSetBit(lit - 1);
481 return true;
482 }
483
484 if (IsPowerOfTwo(lit + 1)) {
485 op->op = kOpRsub;
486 op->shift = LowestSetBit(lit + 1);
487 return true;
488 }
489
490 op->op = kOpInvalid;
491 return false;
492}
493
494// Try to convert *lit to 1~2 RegRegRegShift/RegRegShift forms.
495bool ArmMir2Lir::GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops) {
496 GetEasyMultiplyOp(lit, &ops[0]);
497 if (GetEasyMultiplyOp(lit, &ops[0])) {
498 ops[1].op = kOpInvalid;
499 return true;
500 }
501
502 int lit1 = lit;
503 uint32_t shift = LowestSetBit(lit1);
504 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) {
505 ops[1].op = kOpLsl;
506 ops[1].shift = shift;
507 return true;
508 }
509
510 lit1 = lit - 1;
511 shift = LowestSetBit(lit1);
512 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) {
513 ops[1].op = kOpAdd;
514 ops[1].shift = shift;
515 return true;
516 }
517
518 lit1 = lit + 1;
519 shift = LowestSetBit(lit1);
520 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) {
521 ops[1].op = kOpRsub;
522 ops[1].shift = shift;
523 return true;
524 }
525
526 return false;
527}
528
529void ArmMir2Lir::GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops) {
530 // dest = ( src << shift1) + [ src | -src | 0 ]
531 // dest = (dest << shift2) + [ src | -src | 0 ]
532 for (int i = 0; i < 2; i++) {
533 RegStorage r_src2;
534 if (i == 0) {
535 r_src2 = r_src;
536 } else {
537 r_src2 = r_dest;
538 }
539 switch (ops[i].op) {
540 case kOpLsl:
541 OpRegRegImm(kOpLsl, r_dest, r_src2, ops[i].shift);
542 break;
543 case kOpAdd:
544 OpRegRegRegShift(kOpAdd, r_dest, r_src, r_src2, EncodeShift(kArmLsl, ops[i].shift));
545 break;
546 case kOpRsub:
547 OpRegRegRegShift(kOpRsub, r_dest, r_src, r_src2, EncodeShift(kArmLsl, ops[i].shift));
548 break;
549 default:
550 DCHECK_NE(i, 0);
551 DCHECK_EQ(ops[i].op, kOpInvalid);
552 break;
553 }
554 }
555}
556
557bool ArmMir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) {
558 EasyMultiplyOp ops[2];
559
560 if (!GetEasyMultiplyTwoOps(lit, ops)) {
561 return false;
562 }
563
564 rl_src = LoadValue(rl_src, kCoreReg);
565 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
566
567 GenEasyMultiplyTwoOps(rl_result.reg, rl_src.reg, ops);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700568 StoreValue(rl_dest, rl_result);
569 return true;
570}
571
buzbee2700f7e2014-03-07 09:46:20 -0800572LIR* ArmMir2Lir::GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base,
573 int offset, ThrowKind kind) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700574 LOG(FATAL) << "Unexpected use of GenRegMemCheck for Arm";
575 return NULL;
576}
577
Mark Mendell2bf31e62014-01-23 12:13:40 -0800578RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
579 RegLocation rl_src2, bool is_div, bool check_zero) {
580 LOG(FATAL) << "Unexpected use of GenDivRem for Arm";
581 return rl_dest;
582}
583
584RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) {
585 LOG(FATAL) << "Unexpected use of GenDivRemLit for Arm";
586 return rl_dest;
587}
588
buzbee2700f7e2014-03-07 09:46:20 -0800589RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) {
Dave Allison70202782013-10-22 17:52:19 -0700590 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
591
592 // Put the literal in a temp.
buzbee2700f7e2014-03-07 09:46:20 -0800593 RegStorage lit_temp = AllocTemp();
Dave Allison70202782013-10-22 17:52:19 -0700594 LoadConstant(lit_temp, lit);
595 // Use the generic case for div/rem with arg2 in a register.
596 // TODO: The literal temp can be freed earlier during a modulus to reduce reg pressure.
597 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div);
598 FreeTemp(lit_temp);
599
600 return rl_result;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700601}
602
buzbee2700f7e2014-03-07 09:46:20 -0800603RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700604 bool is_div) {
Dave Allison70202782013-10-22 17:52:19 -0700605 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
606 if (is_div) {
607 // Simple case, use sdiv instruction.
buzbee2700f7e2014-03-07 09:46:20 -0800608 OpRegRegReg(kOpDiv, rl_result.reg, reg1, reg2);
Dave Allison70202782013-10-22 17:52:19 -0700609 } else {
610 // Remainder case, use the following code:
611 // temp = reg1 / reg2 - integer division
612 // temp = temp * reg2
613 // dest = reg1 - temp
614
buzbee2700f7e2014-03-07 09:46:20 -0800615 RegStorage temp = AllocTemp();
Dave Allison70202782013-10-22 17:52:19 -0700616 OpRegRegReg(kOpDiv, temp, reg1, reg2);
617 OpRegReg(kOpMul, temp, reg2);
buzbee2700f7e2014-03-07 09:46:20 -0800618 OpRegRegReg(kOpSub, rl_result.reg, reg1, temp);
Dave Allison70202782013-10-22 17:52:19 -0700619 FreeTemp(temp);
620 }
621
622 return rl_result;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700623}
624
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700625bool ArmMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700626 DCHECK_EQ(cu_->instruction_set, kThumb2);
627 RegLocation rl_src1 = info->args[0];
628 RegLocation rl_src2 = info->args[1];
629 rl_src1 = LoadValue(rl_src1, kCoreReg);
630 rl_src2 = LoadValue(rl_src2, kCoreReg);
631 RegLocation rl_dest = InlineTarget(info);
632 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
buzbee2700f7e2014-03-07 09:46:20 -0800633 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700634 OpIT((is_min) ? kCondGt : kCondLt, "E");
buzbee2700f7e2014-03-07 09:46:20 -0800635 OpRegReg(kOpMov, rl_result.reg, rl_src2.reg);
636 OpRegReg(kOpMov, rl_result.reg, rl_src1.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700637 GenBarrier();
638 StoreValue(rl_dest, rl_result);
639 return true;
640}
641
Vladimir Markoe508a202013-11-04 15:24:22 +0000642bool ArmMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) {
643 RegLocation rl_src_address = info->args[0]; // long address
buzbee2700f7e2014-03-07 09:46:20 -0800644 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1]
Vladimir Markoe508a202013-11-04 15:24:22 +0000645 RegLocation rl_dest = InlineTarget(info);
646 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg);
647 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
648 if (size == kLong) {
649 // Fake unaligned LDRD by two unaligned LDR instructions on ARMv7 with SCTLR.A set to 0.
buzbee2700f7e2014-03-07 09:46:20 -0800650 if (rl_address.reg.GetReg() != rl_result.reg.GetLowReg()) {
651 LoadWordDisp(rl_address.reg, 0, rl_result.reg.GetLow());
652 LoadWordDisp(rl_address.reg, 4, rl_result.reg.GetHigh());
Vladimir Markoe508a202013-11-04 15:24:22 +0000653 } else {
buzbee2700f7e2014-03-07 09:46:20 -0800654 LoadWordDisp(rl_address.reg, 4, rl_result.reg.GetHigh());
655 LoadWordDisp(rl_address.reg, 0, rl_result.reg.GetLow());
Vladimir Markoe508a202013-11-04 15:24:22 +0000656 }
657 StoreValueWide(rl_dest, rl_result);
658 } else {
659 DCHECK(size == kSignedByte || size == kSignedHalf || size == kWord);
660 // Unaligned load with LDR and LDRSH is allowed on ARMv7 with SCTLR.A set to 0.
buzbee2700f7e2014-03-07 09:46:20 -0800661 LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, INVALID_SREG);
Vladimir Markoe508a202013-11-04 15:24:22 +0000662 StoreValue(rl_dest, rl_result);
663 }
664 return true;
665}
666
667bool ArmMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) {
668 RegLocation rl_src_address = info->args[0]; // long address
buzbee2700f7e2014-03-07 09:46:20 -0800669 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1]
Vladimir Markoe508a202013-11-04 15:24:22 +0000670 RegLocation rl_src_value = info->args[2]; // [size] value
671 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg);
672 if (size == kLong) {
673 // Fake unaligned STRD by two unaligned STR instructions on ARMv7 with SCTLR.A set to 0.
674 RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg);
buzbee2700f7e2014-03-07 09:46:20 -0800675 StoreBaseDisp(rl_address.reg, 0, rl_value.reg.GetLow(), kWord);
676 StoreBaseDisp(rl_address.reg, 4, rl_value.reg.GetHigh(), kWord);
Vladimir Markoe508a202013-11-04 15:24:22 +0000677 } else {
678 DCHECK(size == kSignedByte || size == kSignedHalf || size == kWord);
679 // Unaligned store with STR and STRSH is allowed on ARMv7 with SCTLR.A set to 0.
680 RegLocation rl_value = LoadValue(rl_src_value, kCoreReg);
buzbee2700f7e2014-03-07 09:46:20 -0800681 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size);
Vladimir Markoe508a202013-11-04 15:24:22 +0000682 }
683 return true;
684}
685
buzbee2700f7e2014-03-07 09:46:20 -0800686void ArmMir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700687 LOG(FATAL) << "Unexpected use of OpLea for Arm";
688}
689
Ian Rogers468532e2013-08-05 10:56:33 -0700690void ArmMir2Lir::OpTlsCmp(ThreadOffset offset, int val) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700691 LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
692}
693
Vladimir Marko1c282e22013-11-21 14:49:47 +0000694bool ArmMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700695 DCHECK_EQ(cu_->instruction_set, kThumb2);
696 // Unused - RegLocation rl_src_unsafe = info->args[0];
Vladimir Marko1c282e22013-11-21 14:49:47 +0000697 RegLocation rl_src_obj = info->args[1]; // Object - known non-null
698 RegLocation rl_src_offset = info->args[2]; // long low
buzbee2700f7e2014-03-07 09:46:20 -0800699 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3]
Vladimir Marko1c282e22013-11-21 14:49:47 +0000700 RegLocation rl_src_expected = info->args[4]; // int, long or Object
Vladimir Marko3e5af822013-11-21 15:01:20 +0000701 // If is_long, high half is in info->args[5]
702 RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object
703 // If is_long, high half is in info->args[7]
Brian Carlstrom7940e442013-07-12 13:46:57 -0700704 RegLocation rl_dest = InlineTarget(info); // boolean place for result
705
Vladimir Marko3e5af822013-11-21 15:01:20 +0000706 // We have only 5 temporary registers available and actually only 4 if the InlineTarget
707 // above locked one of the temps. For a straightforward CAS64 we need 7 registers:
708 // r_ptr (1), new_value (2), expected(2) and ldrexd result (2). If neither expected nor
709 // new_value is in a non-temp core register we shall reload them in the ldrex/strex loop
710 // into the same temps, reducing the number of required temps down to 5. We shall work
711 // around the potentially locked temp by using LR for r_ptr, unconditionally.
712 // TODO: Pass information about the need for more temps to the stack frame generation
713 // code so that we can rely on being able to allocate enough temps.
714 DCHECK(!reg_pool_->core_regs[rARM_LR].is_temp);
715 MarkTemp(rARM_LR);
716 FreeTemp(rARM_LR);
717 LockTemp(rARM_LR);
718 bool load_early = true;
719 if (is_long) {
buzbee2700f7e2014-03-07 09:46:20 -0800720 int expected_reg = is_long ? rl_src_expected.reg.GetLowReg() : rl_src_expected.reg.GetReg();
721 int new_val_reg = is_long ? rl_src_new_value.reg.GetLowReg() : rl_src_new_value.reg.GetReg();
722 bool expected_is_core_reg = rl_src_expected.location == kLocPhysReg && !IsFpReg(expected_reg);
723 bool new_value_is_core_reg = rl_src_new_value.location == kLocPhysReg && !IsFpReg(new_val_reg);
724 bool expected_is_good_reg = expected_is_core_reg && !IsTemp(expected_reg);
725 bool new_value_is_good_reg = new_value_is_core_reg && !IsTemp(new_val_reg);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000726
727 if (!expected_is_good_reg && !new_value_is_good_reg) {
728 // None of expected/new_value is non-temp reg, need to load both late
729 load_early = false;
730 // Make sure they are not in the temp regs and the load will not be skipped.
731 if (expected_is_core_reg) {
buzbee2700f7e2014-03-07 09:46:20 -0800732 FlushRegWide(rl_src_expected.reg);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000733 ClobberSReg(rl_src_expected.s_reg_low);
734 ClobberSReg(GetSRegHi(rl_src_expected.s_reg_low));
735 rl_src_expected.location = kLocDalvikFrame;
736 }
737 if (new_value_is_core_reg) {
buzbee2700f7e2014-03-07 09:46:20 -0800738 FlushRegWide(rl_src_new_value.reg);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000739 ClobberSReg(rl_src_new_value.s_reg_low);
740 ClobberSReg(GetSRegHi(rl_src_new_value.s_reg_low));
741 rl_src_new_value.location = kLocDalvikFrame;
742 }
743 }
744 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700745
746 // Release store semantics, get the barrier out of the way. TODO: revisit
747 GenMemBarrier(kStoreLoad);
748
749 RegLocation rl_object = LoadValue(rl_src_obj, kCoreReg);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000750 RegLocation rl_new_value;
751 if (!is_long) {
752 rl_new_value = LoadValue(rl_src_new_value, kCoreReg);
753 } else if (load_early) {
754 rl_new_value = LoadValueWide(rl_src_new_value, kCoreReg);
755 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700756
Vladimir Marko1c282e22013-11-21 14:49:47 +0000757 if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700758 // Mark card for object assuming new value is stored.
buzbee2700f7e2014-03-07 09:46:20 -0800759 MarkGCCard(rl_new_value.reg, rl_object.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700760 }
761
762 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg);
763
buzbee2700f7e2014-03-07 09:46:20 -0800764 RegStorage r_ptr = rs_rARM_LR;
765 OpRegRegReg(kOpAdd, r_ptr, rl_object.reg, rl_offset.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700766
767 // Free now unneeded rl_object and rl_offset to give more temps.
768 ClobberSReg(rl_object.s_reg_low);
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000769 FreeTemp(rl_object.reg.GetReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700770 ClobberSReg(rl_offset.s_reg_low);
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000771 FreeTemp(rl_offset.reg.GetReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700772
Vladimir Marko3e5af822013-11-21 15:01:20 +0000773 RegLocation rl_expected;
774 if (!is_long) {
775 rl_expected = LoadValue(rl_src_expected, kCoreReg);
776 } else if (load_early) {
777 rl_expected = LoadValueWide(rl_src_expected, kCoreReg);
778 } else {
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000779 // NOTE: partially defined rl_expected & rl_new_value - but we just want the regs.
buzbee2700f7e2014-03-07 09:46:20 -0800780 int low_reg = AllocTemp().GetReg();
781 int high_reg = AllocTemp().GetReg();
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000782 rl_new_value.reg = RegStorage(RegStorage::k64BitPair, low_reg, high_reg);
783 rl_expected = rl_new_value;
Vladimir Marko3e5af822013-11-21 15:01:20 +0000784 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700785
Vladimir Marko3e5af822013-11-21 15:01:20 +0000786 // do {
787 // tmp = [r_ptr] - expected;
788 // } while (tmp == 0 && failure([r_ptr] <- r_new_value));
789 // result = tmp != 0;
790
buzbee2700f7e2014-03-07 09:46:20 -0800791 RegStorage r_tmp = AllocTemp();
Jeff Hao2de2aa12013-09-12 17:20:31 -0700792 LIR* target = NewLIR0(kPseudoTargetLabel);
Jeff Hao2de2aa12013-09-12 17:20:31 -0700793
Vladimir Marko3e5af822013-11-21 15:01:20 +0000794 if (is_long) {
buzbee2700f7e2014-03-07 09:46:20 -0800795 RegStorage r_tmp_high = AllocTemp();
Vladimir Marko3e5af822013-11-21 15:01:20 +0000796 if (!load_early) {
buzbee2700f7e2014-03-07 09:46:20 -0800797 LoadValueDirectWide(rl_src_expected, rl_expected.reg);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000798 }
buzbee2700f7e2014-03-07 09:46:20 -0800799 NewLIR3(kThumb2Ldrexd, r_tmp.GetReg(), r_tmp_high.GetReg(), r_ptr.GetReg());
800 OpRegReg(kOpSub, r_tmp, rl_expected.reg.GetLow());
801 OpRegReg(kOpSub, r_tmp_high, rl_expected.reg.GetHigh());
Vladimir Marko3e5af822013-11-21 15:01:20 +0000802 if (!load_early) {
buzbee2700f7e2014-03-07 09:46:20 -0800803 LoadValueDirectWide(rl_src_new_value, rl_new_value.reg);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000804 }
805 // Make sure we use ORR that sets the ccode
buzbee2700f7e2014-03-07 09:46:20 -0800806 if (ARM_LOWREG(r_tmp.GetReg()) && ARM_LOWREG(r_tmp_high.GetReg())) {
807 NewLIR2(kThumbOrr, r_tmp.GetReg(), r_tmp_high.GetReg());
Vladimir Marko3e5af822013-11-21 15:01:20 +0000808 } else {
buzbee2700f7e2014-03-07 09:46:20 -0800809 NewLIR4(kThumb2OrrRRRs, r_tmp.GetReg(), r_tmp.GetReg(), r_tmp_high.GetReg(), 0);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000810 }
811 FreeTemp(r_tmp_high); // Now unneeded
812
813 DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
814 OpIT(kCondEq, "T");
buzbee2700f7e2014-03-07 09:46:20 -0800815 NewLIR4(kThumb2Strexd /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetLowReg(), rl_new_value.reg.GetHighReg(), r_ptr.GetReg());
Vladimir Marko3e5af822013-11-21 15:01:20 +0000816
817 } else {
buzbee2700f7e2014-03-07 09:46:20 -0800818 NewLIR3(kThumb2Ldrex, r_tmp.GetReg(), r_ptr.GetReg(), 0);
819 OpRegReg(kOpSub, r_tmp, rl_expected.reg);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000820 DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
821 OpIT(kCondEq, "T");
buzbee2700f7e2014-03-07 09:46:20 -0800822 NewLIR4(kThumb2Strex /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetReg(), r_ptr.GetReg(), 0);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000823 }
824
825 // Still one conditional left from OpIT(kCondEq, "T") from either branch
826 OpRegImm(kOpCmp /* eq */, r_tmp, 1);
Jeff Hao2de2aa12013-09-12 17:20:31 -0700827 OpCondBranch(kCondEq, target);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700828
Vladimir Marko3e5af822013-11-21 15:01:20 +0000829 if (!load_early) {
buzbee2700f7e2014-03-07 09:46:20 -0800830 FreeTemp(rl_expected.reg); // Now unneeded.
Vladimir Marko3e5af822013-11-21 15:01:20 +0000831 }
832
833 // result := (tmp1 != 0) ? 0 : 1;
834 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
buzbee2700f7e2014-03-07 09:46:20 -0800835 OpRegRegImm(kOpRsub, rl_result.reg, r_tmp, 1);
Vladimir Marko3e5af822013-11-21 15:01:20 +0000836 DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
Vladimir Marko58af1f92013-12-19 13:31:15 +0000837 OpIT(kCondUlt, "");
buzbee2700f7e2014-03-07 09:46:20 -0800838 LoadConstant(rl_result.reg, 0); /* cc */
Vladimir Marko3e5af822013-11-21 15:01:20 +0000839 FreeTemp(r_tmp); // Now unneeded.
840
Brian Carlstrom7940e442013-07-12 13:46:57 -0700841 StoreValue(rl_dest, rl_result);
842
Vladimir Marko3e5af822013-11-21 15:01:20 +0000843 // Now, restore lr to its non-temp status.
844 Clobber(rARM_LR);
845 UnmarkTemp(rARM_LR);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700846 return true;
847}
848
buzbee2700f7e2014-03-07 09:46:20 -0800849LIR* ArmMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) {
850 return RawLIR(current_dalvik_offset_, kThumb2LdrPcRel12, reg.GetReg(), 0, 0, 0, 0, target);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700851}
852
buzbee2700f7e2014-03-07 09:46:20 -0800853LIR* ArmMir2Lir::OpVldm(RegStorage r_base, int count) {
854 return NewLIR3(kThumb2Vldms, r_base.GetReg(), fr0, count);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700855}
856
buzbee2700f7e2014-03-07 09:46:20 -0800857LIR* ArmMir2Lir::OpVstm(RegStorage r_base, int count) {
858 return NewLIR3(kThumb2Vstms, r_base.GetReg(), fr0, count);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700859}
860
861void ArmMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
862 RegLocation rl_result, int lit,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700863 int first_bit, int second_bit) {
Zheng Xu08df4b32014-03-25 14:25:52 +0000864 OpRegRegRegShift(kOpAdd, rl_result.reg, rl_src.reg, rl_src.reg,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700865 EncodeShift(kArmLsl, second_bit - first_bit));
866 if (first_bit != 0) {
buzbee2700f7e2014-03-07 09:46:20 -0800867 OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700868 }
869}
870
buzbee2700f7e2014-03-07 09:46:20 -0800871void ArmMir2Lir::GenDivZeroCheck(RegStorage reg) {
872 DCHECK(reg.IsPair()); // TODO: support k64BitSolo.
873 RegStorage t_reg = AllocTemp();
874 NewLIR4(kThumb2OrrRRRs, t_reg.GetReg(), reg.GetLowReg(), reg.GetHighReg(), 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700875 FreeTemp(t_reg);
876 GenCheck(kCondEq, kThrowDivZero);
877}
878
879// Test suspend flag, return target of taken suspend branch
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700880LIR* ArmMir2Lir::OpTestSuspend(LIR* target) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700881 NewLIR2(kThumbSubRI8, rARM_SUSPEND, 1);
882 return OpCondBranch((target == NULL) ? kCondEq : kCondNe, target);
883}
884
885// Decrement register and branch on condition
buzbee2700f7e2014-03-07 09:46:20 -0800886LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700887 // Combine sub & test using sub setflags encoding here
Vladimir Markodbb8c492014-02-28 17:36:39 +0000888 OpRegRegImm(kOpSub, reg, reg, 1); // For value == 1, this should set flags.
889 DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700890 return OpCondBranch(c_code, target);
891}
892
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700893void ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700894#if ANDROID_SMP != 0
Razvan A Lupusoru99ad7232014-02-25 17:41:08 -0800895 // Start off with using the last LIR as the barrier. If it is not enough, then we will generate one.
896 LIR* barrier = last_lir_insn_;
897
Brian Carlstrom7940e442013-07-12 13:46:57 -0700898 int dmb_flavor;
899 // TODO: revisit Arm barrier kinds
900 switch (barrier_kind) {
Ian Rogersb122a4b2013-11-19 18:00:50 -0800901 case kLoadStore: dmb_flavor = kISH; break;
902 case kLoadLoad: dmb_flavor = kISH; break;
903 case kStoreStore: dmb_flavor = kISHST; break;
904 case kStoreLoad: dmb_flavor = kISH; break;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700905 default:
906 LOG(FATAL) << "Unexpected MemBarrierKind: " << barrier_kind;
907 dmb_flavor = kSY; // quiet gcc.
908 break;
909 }
Razvan A Lupusoru99ad7232014-02-25 17:41:08 -0800910
911 // If the same barrier already exists, don't generate another.
912 if (barrier == nullptr
913 || (barrier != nullptr && (barrier->opcode != kThumb2Dmb || barrier->operands[0] != dmb_flavor))) {
914 barrier = NewLIR1(kThumb2Dmb, dmb_flavor);
915 }
916
917 // At this point we must have a memory barrier. Mark it as a scheduling barrier as well.
918 DCHECK(!barrier->flags.use_def_invalid);
919 barrier->u.m.def_mask = ENCODE_ALL;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700920#endif
921}
922
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700923void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700924 rl_src = LoadValueWide(rl_src, kCoreReg);
925 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
buzbee2700f7e2014-03-07 09:46:20 -0800926 RegStorage z_reg = AllocTemp();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700927 LoadConstantNoClobber(z_reg, 0);
928 // Check for destructive overlap
buzbee2700f7e2014-03-07 09:46:20 -0800929 if (rl_result.reg.GetLowReg() == rl_src.reg.GetHighReg()) {
930 RegStorage t_reg = AllocTemp();
931 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow());
932 OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, t_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700933 FreeTemp(t_reg);
934 } else {
buzbee2700f7e2014-03-07 09:46:20 -0800935 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow());
936 OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, rl_src.reg.GetHigh());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700937 }
938 FreeTemp(z_reg);
939 StoreValueWide(rl_dest, rl_result);
940}
941
Mark Mendelle02d48f2014-01-15 11:19:23 -0800942void ArmMir2Lir::GenMulLong(Instruction::Code opcode, RegLocation rl_dest,
943 RegLocation rl_src1, RegLocation rl_src2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700944 /*
Zheng Xud7f8e022014-03-13 13:40:30 +0000945 * tmp1 = src1.hi * src2.lo; // src1.hi is no longer needed
946 * dest = src1.lo * src2.lo;
947 * tmp1 += src1.lo * src2.hi;
948 * dest.hi += tmp1;
949 *
950 * To pull off inline multiply, we have a worst-case requirement of 7 temporary
Brian Carlstrom7940e442013-07-12 13:46:57 -0700951 * registers. Normally for Arm, we get 5. We can get to 6 by including
952 * lr in the temp set. The only problematic case is all operands and result are
953 * distinct, and none have been promoted. In that case, we can succeed by aggressively
954 * freeing operand temp registers after they are no longer needed. All other cases
955 * can proceed normally. We'll just punt on the case of the result having a misaligned
956 * overlap with either operand and send that case to a runtime handler.
957 */
958 RegLocation rl_result;
959 if (BadOverlap(rl_src1, rl_dest) || (BadOverlap(rl_src2, rl_dest))) {
Ian Rogers468532e2013-08-05 10:56:33 -0700960 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pLmul);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700961 FlushAllRegs();
962 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false);
963 rl_result = GetReturnWide(false);
964 StoreValueWide(rl_dest, rl_result);
965 return;
966 }
Zheng Xud7f8e022014-03-13 13:40:30 +0000967
968 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
969 rl_src2 = LoadValueWide(rl_src2, kCoreReg);
970
971 int reg_status = 0;
buzbee2700f7e2014-03-07 09:46:20 -0800972 RegStorage res_lo;
973 RegStorage res_hi;
974 bool dest_promoted = rl_dest.location == kLocPhysReg && rl_dest.reg.Valid() &&
975 !IsTemp(rl_dest.reg.GetLowReg()) && !IsTemp(rl_dest.reg.GetHighReg());
976 bool src1_promoted = !IsTemp(rl_src1.reg.GetLowReg()) && !IsTemp(rl_src1.reg.GetHighReg());
977 bool src2_promoted = !IsTemp(rl_src2.reg.GetLowReg()) && !IsTemp(rl_src2.reg.GetHighReg());
Zheng Xud7f8e022014-03-13 13:40:30 +0000978 // Check if rl_dest is *not* either operand and we have enough temp registers.
979 if ((rl_dest.s_reg_low != rl_src1.s_reg_low && rl_dest.s_reg_low != rl_src2.s_reg_low) &&
980 (dest_promoted || src1_promoted || src2_promoted)) {
981 // In this case, we do not need to manually allocate temp registers for result.
982 rl_result = EvalLoc(rl_dest, kCoreReg, true);
buzbee2700f7e2014-03-07 09:46:20 -0800983 res_lo = rl_result.reg.GetLow();
984 res_hi = rl_result.reg.GetHigh();
Zheng Xud7f8e022014-03-13 13:40:30 +0000985 } else {
986 res_lo = AllocTemp();
987 if ((rl_src1.s_reg_low == rl_src2.s_reg_low) || src1_promoted || src2_promoted) {
988 // In this case, we have enough temp registers to be allocated for result.
989 res_hi = AllocTemp();
990 reg_status = 1;
991 } else {
992 // In this case, all temps are now allocated.
993 // res_hi will be allocated after we can free src1_hi.
994 reg_status = 2;
995 }
996 }
997
Brian Carlstrom7940e442013-07-12 13:46:57 -0700998 // Temporarily add LR to the temp pool, and assign it to tmp1
999 MarkTemp(rARM_LR);
1000 FreeTemp(rARM_LR);
buzbee2700f7e2014-03-07 09:46:20 -08001001 RegStorage tmp1 = rs_rARM_LR;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001002 LockTemp(rARM_LR);
1003
buzbee2700f7e2014-03-07 09:46:20 -08001004 if (rl_src1.reg == rl_src2.reg) {
1005 DCHECK(res_hi.Valid());
1006 DCHECK(res_lo.Valid());
1007 NewLIR3(kThumb2MulRRR, tmp1.GetReg(), rl_src1.reg.GetLowReg(), rl_src1.reg.GetHighReg());
1008 NewLIR4(kThumb2Umull, res_lo.GetReg(), res_hi.GetReg(), rl_src1.reg.GetLowReg(),
1009 rl_src1.reg.GetLowReg());
Zheng Xu08df4b32014-03-25 14:25:52 +00001010 OpRegRegRegShift(kOpAdd, res_hi, res_hi, tmp1, EncodeShift(kArmLsl, 1));
Brian Carlstrom7940e442013-07-12 13:46:57 -07001011 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001012 NewLIR3(kThumb2MulRRR, tmp1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg.GetHighReg());
Zheng Xud7f8e022014-03-13 13:40:30 +00001013 if (reg_status == 2) {
buzbee2700f7e2014-03-07 09:46:20 -08001014 DCHECK(!res_hi.Valid());
1015 DCHECK_NE(rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg());
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001016 DCHECK_NE(rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg());
1017 FreeTemp(rl_src1.reg.GetHighReg());
Zheng Xud7f8e022014-03-13 13:40:30 +00001018 res_hi = AllocTemp();
Brian Carlstrom7940e442013-07-12 13:46:57 -07001019 }
buzbee2700f7e2014-03-07 09:46:20 -08001020 DCHECK(res_hi.Valid());
1021 DCHECK(res_lo.Valid());
1022 NewLIR4(kThumb2Umull, res_lo.GetReg(), res_hi.GetReg(), rl_src2.reg.GetLowReg(),
1023 rl_src1.reg.GetLowReg());
1024 NewLIR4(kThumb2Mla, tmp1.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetHighReg(),
1025 tmp1.GetReg());
1026 NewLIR4(kThumb2AddRRR, res_hi.GetReg(), tmp1.GetReg(), res_hi.GetReg(), 0);
Zheng Xud7f8e022014-03-13 13:40:30 +00001027 if (reg_status == 2) {
1028 // Clobber rl_src1 since it was corrupted.
buzbee2700f7e2014-03-07 09:46:20 -08001029 FreeTemp(rl_src1.reg);
1030 Clobber(rl_src1.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001031 }
1032 }
Zheng Xud7f8e022014-03-13 13:40:30 +00001033
Brian Carlstrom7940e442013-07-12 13:46:57 -07001034 // Now, restore lr to its non-temp status.
Zheng Xud7f8e022014-03-13 13:40:30 +00001035 FreeTemp(tmp1);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001036 Clobber(rARM_LR);
1037 UnmarkTemp(rARM_LR);
Zheng Xud7f8e022014-03-13 13:40:30 +00001038
1039 if (reg_status != 0) {
1040 // We had manually allocated registers for rl_result.
1041 // Now construct a RegLocation.
1042 rl_result = GetReturnWide(false); // Just using as a template.
buzbee2700f7e2014-03-07 09:46:20 -08001043 rl_result.reg = RegStorage::MakeRegPair(res_lo, res_hi);
Zheng Xud7f8e022014-03-13 13:40:30 +00001044 }
1045
1046 StoreValueWide(rl_dest, rl_result);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001047}
1048
Mark Mendelle02d48f2014-01-15 11:19:23 -08001049void ArmMir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001050 RegLocation rl_src2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001051 LOG(FATAL) << "Unexpected use of GenAddLong for Arm";
1052}
1053
Mark Mendelle02d48f2014-01-15 11:19:23 -08001054void ArmMir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001055 RegLocation rl_src2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001056 LOG(FATAL) << "Unexpected use of GenSubLong for Arm";
1057}
1058
Mark Mendelle02d48f2014-01-15 11:19:23 -08001059void ArmMir2Lir::GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001060 RegLocation rl_src2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001061 LOG(FATAL) << "Unexpected use of GenAndLong for Arm";
1062}
1063
Mark Mendelle02d48f2014-01-15 11:19:23 -08001064void ArmMir2Lir::GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001065 RegLocation rl_src2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001066 LOG(FATAL) << "Unexpected use of GenOrLong for Arm";
1067}
1068
Mark Mendelle02d48f2014-01-15 11:19:23 -08001069void ArmMir2Lir::GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001070 RegLocation rl_src2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001071 LOG(FATAL) << "Unexpected use of genXoLong for Arm";
1072}
1073
1074/*
1075 * Generate array load
1076 */
1077void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
Ian Rogersa9a82542013-10-04 11:17:26 -07001078 RegLocation rl_index, RegLocation rl_dest, int scale) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001079 RegisterClass reg_class = oat_reg_class_by_size(size);
1080 int len_offset = mirror::Array::LengthOffset().Int32Value();
1081 int data_offset;
1082 RegLocation rl_result;
1083 bool constant_index = rl_index.is_const;
1084 rl_array = LoadValue(rl_array, kCoreReg);
1085 if (!constant_index) {
1086 rl_index = LoadValue(rl_index, kCoreReg);
1087 }
1088
1089 if (rl_dest.wide) {
1090 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value();
1091 } else {
1092 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value();
1093 }
1094
1095 // If index is constant, just fold it into the data offset
1096 if (constant_index) {
1097 data_offset += mir_graph_->ConstantValue(rl_index) << scale;
1098 }
1099
1100 /* null object? */
buzbee2700f7e2014-03-07 09:46:20 -08001101 GenNullCheck(rl_array.reg, opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001102
1103 bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK));
buzbee2700f7e2014-03-07 09:46:20 -08001104 RegStorage reg_len;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001105 if (needs_range_check) {
1106 reg_len = AllocTemp();
1107 /* Get len */
buzbee2700f7e2014-03-07 09:46:20 -08001108 LoadWordDisp(rl_array.reg, len_offset, reg_len);
Dave Allisonb373e092014-02-20 16:06:36 -08001109 MarkPossibleNullPointerException(opt_flags);
1110 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001111 ForceImplicitNullCheck(rl_array.reg, opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001112 }
1113 if (rl_dest.wide || rl_dest.fp || constant_index) {
buzbee2700f7e2014-03-07 09:46:20 -08001114 RegStorage reg_ptr;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001115 if (constant_index) {
buzbee2700f7e2014-03-07 09:46:20 -08001116 reg_ptr = rl_array.reg; // NOTE: must not alter reg_ptr in constant case.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001117 } else {
1118 // No special indexed operation, lea + load w/ displacement
1119 reg_ptr = AllocTemp();
Zheng Xu08df4b32014-03-25 14:25:52 +00001120 OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale));
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001121 FreeTemp(rl_index.reg.GetReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -07001122 }
1123 rl_result = EvalLoc(rl_dest, reg_class, true);
1124
1125 if (needs_range_check) {
1126 if (constant_index) {
1127 GenImmedCheck(kCondLs, reg_len, mir_graph_->ConstantValue(rl_index), kThrowConstantArrayBounds);
1128 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001129 GenRegRegCheck(kCondLs, reg_len, rl_index.reg, kThrowArrayBounds);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001130 }
1131 FreeTemp(reg_len);
1132 }
1133 if (rl_dest.wide) {
buzbee2700f7e2014-03-07 09:46:20 -08001134 LoadBaseDispWide(reg_ptr, data_offset, rl_result.reg, INVALID_SREG);
Dave Allisonb373e092014-02-20 16:06:36 -08001135 MarkPossibleNullPointerException(opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001136 if (!constant_index) {
1137 FreeTemp(reg_ptr);
1138 }
1139 StoreValueWide(rl_dest, rl_result);
1140 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001141 LoadBaseDisp(reg_ptr, data_offset, rl_result.reg, size, INVALID_SREG);
Dave Allisonb373e092014-02-20 16:06:36 -08001142 MarkPossibleNullPointerException(opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001143 if (!constant_index) {
1144 FreeTemp(reg_ptr);
1145 }
1146 StoreValue(rl_dest, rl_result);
1147 }
1148 } else {
1149 // Offset base, then use indexed load
buzbee2700f7e2014-03-07 09:46:20 -08001150 RegStorage reg_ptr = AllocTemp();
1151 OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset);
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001152 FreeTemp(rl_array.reg.GetReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -07001153 rl_result = EvalLoc(rl_dest, reg_class, true);
1154
1155 if (needs_range_check) {
buzbee2700f7e2014-03-07 09:46:20 -08001156 GenRegRegCheck(kCondUge, rl_index.reg, reg_len, kThrowArrayBounds);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001157 FreeTemp(reg_len);
1158 }
buzbee2700f7e2014-03-07 09:46:20 -08001159 LoadBaseIndexed(reg_ptr, rl_index.reg, rl_result.reg, scale, size);
Dave Allisonb373e092014-02-20 16:06:36 -08001160 MarkPossibleNullPointerException(opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001161 FreeTemp(reg_ptr);
1162 StoreValue(rl_dest, rl_result);
1163 }
1164}
1165
1166/*
1167 * Generate array store
1168 *
1169 */
1170void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
Ian Rogersa9a82542013-10-04 11:17:26 -07001171 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001172 RegisterClass reg_class = oat_reg_class_by_size(size);
1173 int len_offset = mirror::Array::LengthOffset().Int32Value();
Brian Carlstrom7940e442013-07-12 13:46:57 -07001174 bool constant_index = rl_index.is_const;
1175
Ian Rogersa9a82542013-10-04 11:17:26 -07001176 int data_offset;
1177 if (size == kLong || size == kDouble) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001178 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value();
1179 } else {
1180 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value();
1181 }
1182
1183 // If index is constant, just fold it into the data offset.
1184 if (constant_index) {
1185 data_offset += mir_graph_->ConstantValue(rl_index) << scale;
1186 }
1187
1188 rl_array = LoadValue(rl_array, kCoreReg);
1189 if (!constant_index) {
1190 rl_index = LoadValue(rl_index, kCoreReg);
1191 }
1192
buzbee2700f7e2014-03-07 09:46:20 -08001193 RegStorage reg_ptr;
Ian Rogers773aab12013-10-14 13:50:10 -07001194 bool allocated_reg_ptr_temp = false;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001195 if (constant_index) {
buzbee2700f7e2014-03-07 09:46:20 -08001196 reg_ptr = rl_array.reg;
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001197 } else if (IsTemp(rl_array.reg.GetReg()) && !card_mark) {
1198 Clobber(rl_array.reg.GetReg());
buzbee2700f7e2014-03-07 09:46:20 -08001199 reg_ptr = rl_array.reg;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001200 } else {
Ian Rogers773aab12013-10-14 13:50:10 -07001201 allocated_reg_ptr_temp = true;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001202 reg_ptr = AllocTemp();
1203 }
1204
1205 /* null object? */
buzbee2700f7e2014-03-07 09:46:20 -08001206 GenNullCheck(rl_array.reg, opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001207
1208 bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK));
buzbee2700f7e2014-03-07 09:46:20 -08001209 RegStorage reg_len;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001210 if (needs_range_check) {
1211 reg_len = AllocTemp();
Brian Carlstrom7934ac22013-07-26 10:54:15 -07001212 // NOTE: max live temps(4) here.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001213 /* Get len */
buzbee2700f7e2014-03-07 09:46:20 -08001214 LoadWordDisp(rl_array.reg, len_offset, reg_len);
Dave Allisonb373e092014-02-20 16:06:36 -08001215 MarkPossibleNullPointerException(opt_flags);
1216 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001217 ForceImplicitNullCheck(rl_array.reg, opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001218 }
1219 /* at this point, reg_ptr points to array, 2 live temps */
1220 if (rl_src.wide || rl_src.fp || constant_index) {
1221 if (rl_src.wide) {
1222 rl_src = LoadValueWide(rl_src, reg_class);
1223 } else {
1224 rl_src = LoadValue(rl_src, reg_class);
1225 }
1226 if (!constant_index) {
Zheng Xu08df4b32014-03-25 14:25:52 +00001227 OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale));
Brian Carlstrom7940e442013-07-12 13:46:57 -07001228 }
1229 if (needs_range_check) {
1230 if (constant_index) {
1231 GenImmedCheck(kCondLs, reg_len, mir_graph_->ConstantValue(rl_index), kThrowConstantArrayBounds);
1232 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001233 GenRegRegCheck(kCondLs, reg_len, rl_index.reg, kThrowArrayBounds);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001234 }
1235 FreeTemp(reg_len);
1236 }
1237
1238 if (rl_src.wide) {
buzbee2700f7e2014-03-07 09:46:20 -08001239 StoreBaseDispWide(reg_ptr, data_offset, rl_src.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001240 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001241 StoreBaseDisp(reg_ptr, data_offset, rl_src.reg, size);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001242 }
Dave Allisonb373e092014-02-20 16:06:36 -08001243 MarkPossibleNullPointerException(opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001244 } else {
1245 /* reg_ptr -> array data */
buzbee2700f7e2014-03-07 09:46:20 -08001246 OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001247 rl_src = LoadValue(rl_src, reg_class);
1248 if (needs_range_check) {
buzbee2700f7e2014-03-07 09:46:20 -08001249 GenRegRegCheck(kCondUge, rl_index.reg, reg_len, kThrowArrayBounds);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001250 FreeTemp(reg_len);
1251 }
buzbee2700f7e2014-03-07 09:46:20 -08001252 StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size);
Dave Allisonb373e092014-02-20 16:06:36 -08001253 MarkPossibleNullPointerException(opt_flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001254 }
Ian Rogers773aab12013-10-14 13:50:10 -07001255 if (allocated_reg_ptr_temp) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001256 FreeTemp(reg_ptr);
1257 }
Ian Rogersa9a82542013-10-04 11:17:26 -07001258 if (card_mark) {
buzbee2700f7e2014-03-07 09:46:20 -08001259 MarkGCCard(rl_src.reg, rl_array.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001260 }
1261}
1262
Ian Rogersa9a82542013-10-04 11:17:26 -07001263
Brian Carlstrom7940e442013-07-12 13:46:57 -07001264void ArmMir2Lir::GenShiftImmOpLong(Instruction::Code opcode,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001265 RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001266 rl_src = LoadValueWide(rl_src, kCoreReg);
1267 // Per spec, we only care about low 6 bits of shift amount.
1268 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f;
1269 if (shift_amount == 0) {
1270 StoreValueWide(rl_dest, rl_src);
1271 return;
1272 }
1273 if (BadOverlap(rl_src, rl_dest)) {
1274 GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift);
1275 return;
1276 }
1277 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
Brian Carlstromdf629502013-07-17 22:39:56 -07001278 switch (opcode) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001279 case Instruction::SHL_LONG:
1280 case Instruction::SHL_LONG_2ADDR:
1281 if (shift_amount == 1) {
buzbee2700f7e2014-03-07 09:46:20 -08001282 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), rl_src.reg.GetLow());
1283 OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), rl_src.reg.GetHigh());
Brian Carlstrom7940e442013-07-12 13:46:57 -07001284 } else if (shift_amount == 32) {
buzbee2700f7e2014-03-07 09:46:20 -08001285 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg);
1286 LoadConstant(rl_result.reg.GetLow(), 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001287 } else if (shift_amount > 31) {
buzbee2700f7e2014-03-07 09:46:20 -08001288 OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetLow(), shift_amount - 32);
1289 LoadConstant(rl_result.reg.GetLow(), 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001290 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001291 OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount);
Zheng Xu08df4b32014-03-25 14:25:52 +00001292 OpRegRegRegShift(kOpOr, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), rl_src.reg.GetLow(),
Brian Carlstrom7940e442013-07-12 13:46:57 -07001293 EncodeShift(kArmLsr, 32 - shift_amount));
buzbee2700f7e2014-03-07 09:46:20 -08001294 OpRegRegImm(kOpLsl, rl_result.reg.GetLow(), rl_src.reg.GetLow(), shift_amount);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001295 }
1296 break;
1297 case Instruction::SHR_LONG:
1298 case Instruction::SHR_LONG_2ADDR:
1299 if (shift_amount == 32) {
buzbee2700f7e2014-03-07 09:46:20 -08001300 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
1301 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 31);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001302 } else if (shift_amount > 31) {
buzbee2700f7e2014-03-07 09:46:20 -08001303 OpRegRegImm(kOpAsr, rl_result.reg.GetLow(), rl_src.reg.GetHigh(), shift_amount - 32);
1304 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 31);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001305 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001306 RegStorage t_reg = AllocTemp();
1307 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetLow(), shift_amount);
Zheng Xu08df4b32014-03-25 14:25:52 +00001308 OpRegRegRegShift(kOpOr, rl_result.reg.GetLow(), t_reg, rl_src.reg.GetHigh(),
Brian Carlstrom7940e442013-07-12 13:46:57 -07001309 EncodeShift(kArmLsl, 32 - shift_amount));
1310 FreeTemp(t_reg);
buzbee2700f7e2014-03-07 09:46:20 -08001311 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001312 }
1313 break;
1314 case Instruction::USHR_LONG:
1315 case Instruction::USHR_LONG_2ADDR:
1316 if (shift_amount == 32) {
buzbee2700f7e2014-03-07 09:46:20 -08001317 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
1318 LoadConstant(rl_result.reg.GetHigh(), 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001319 } else if (shift_amount > 31) {
buzbee2700f7e2014-03-07 09:46:20 -08001320 OpRegRegImm(kOpLsr, rl_result.reg.GetLow(), rl_src.reg.GetHigh(), shift_amount - 32);
1321 LoadConstant(rl_result.reg.GetHigh(), 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001322 } else {
buzbee2700f7e2014-03-07 09:46:20 -08001323 RegStorage t_reg = AllocTemp();
1324 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetLow(), shift_amount);
Zheng Xu08df4b32014-03-25 14:25:52 +00001325 OpRegRegRegShift(kOpOr, rl_result.reg.GetLow(), t_reg, rl_src.reg.GetHigh(),
Brian Carlstrom7940e442013-07-12 13:46:57 -07001326 EncodeShift(kArmLsl, 32 - shift_amount));
1327 FreeTemp(t_reg);
buzbee2700f7e2014-03-07 09:46:20 -08001328 OpRegRegImm(kOpLsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001329 }
1330 break;
1331 default:
1332 LOG(FATAL) << "Unexpected case";
1333 }
1334 StoreValueWide(rl_dest, rl_result);
1335}
1336
1337void ArmMir2Lir::GenArithImmOpLong(Instruction::Code opcode,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001338 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001339 if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) {
1340 if (!rl_src2.is_const) {
1341 // Don't bother with special handling for subtract from immediate.
1342 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
1343 return;
1344 }
1345 } else {
1346 // Normalize
1347 if (!rl_src2.is_const) {
1348 DCHECK(rl_src1.is_const);
Vladimir Marko58af1f92013-12-19 13:31:15 +00001349 std::swap(rl_src1, rl_src2);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001350 }
1351 }
1352 if (BadOverlap(rl_src1, rl_dest)) {
1353 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
1354 return;
1355 }
1356 DCHECK(rl_src2.is_const);
1357 int64_t val = mir_graph_->ConstantValueWide(rl_src2);
1358 uint32_t val_lo = Low32Bits(val);
1359 uint32_t val_hi = High32Bits(val);
1360 int32_t mod_imm_lo = ModifiedImmediate(val_lo);
1361 int32_t mod_imm_hi = ModifiedImmediate(val_hi);
1362
1363 // Only a subset of add/sub immediate instructions set carry - so bail if we don't fit
Brian Carlstromdf629502013-07-17 22:39:56 -07001364 switch (opcode) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001365 case Instruction::ADD_LONG:
1366 case Instruction::ADD_LONG_2ADDR:
1367 case Instruction::SUB_LONG:
1368 case Instruction::SUB_LONG_2ADDR:
1369 if ((mod_imm_lo < 0) || (mod_imm_hi < 0)) {
1370 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
1371 return;
1372 }
1373 break;
1374 default:
1375 break;
1376 }
1377 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
1378 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
1379 // NOTE: once we've done the EvalLoc on dest, we can no longer bail.
1380 switch (opcode) {
1381 case Instruction::ADD_LONG:
1382 case Instruction::ADD_LONG_2ADDR:
buzbee2700f7e2014-03-07 09:46:20 -08001383 NewLIR3(kThumb2AddRRI8M, rl_result.reg.GetLowReg(), rl_src1.reg.GetLowReg(), mod_imm_lo);
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001384 NewLIR3(kThumb2AdcRRI8M, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), mod_imm_hi);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001385 break;
1386 case Instruction::OR_LONG:
1387 case Instruction::OR_LONG_2ADDR:
buzbee2700f7e2014-03-07 09:46:20 -08001388 if ((val_lo != 0) || (rl_result.reg.GetLowReg() != rl_src1.reg.GetLowReg())) {
1389 OpRegRegImm(kOpOr, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001390 }
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001391 if ((val_hi != 0) || (rl_result.reg.GetHighReg() != rl_src1.reg.GetHighReg())) {
buzbee2700f7e2014-03-07 09:46:20 -08001392 OpRegRegImm(kOpOr, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001393 }
1394 break;
1395 case Instruction::XOR_LONG:
1396 case Instruction::XOR_LONG_2ADDR:
buzbee2700f7e2014-03-07 09:46:20 -08001397 OpRegRegImm(kOpXor, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo);
1398 OpRegRegImm(kOpXor, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001399 break;
1400 case Instruction::AND_LONG:
1401 case Instruction::AND_LONG_2ADDR:
buzbee2700f7e2014-03-07 09:46:20 -08001402 if ((val_lo != 0xffffffff) || (rl_result.reg.GetLowReg() != rl_src1.reg.GetLowReg())) {
1403 OpRegRegImm(kOpAnd, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001404 }
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001405 if ((val_hi != 0xffffffff) || (rl_result.reg.GetHighReg() != rl_src1.reg.GetHighReg())) {
buzbee2700f7e2014-03-07 09:46:20 -08001406 OpRegRegImm(kOpAnd, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001407 }
1408 break;
1409 case Instruction::SUB_LONG_2ADDR:
1410 case Instruction::SUB_LONG:
buzbee2700f7e2014-03-07 09:46:20 -08001411 NewLIR3(kThumb2SubRRI8M, rl_result.reg.GetLowReg(), rl_src1.reg.GetLowReg(), mod_imm_lo);
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001412 NewLIR3(kThumb2SbcRRI8M, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), mod_imm_hi);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001413 break;
1414 default:
1415 LOG(FATAL) << "Unexpected opcode " << opcode;
1416 }
1417 StoreValueWide(rl_dest, rl_result);
1418}
1419
1420} // namespace art