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review.blissroms.org / platform_art / 58805e4974fcc73c3a2830608679e051f9e5f78f / . / src / compiler / dex / quick / codegen.h
blob: 272ccadfb9f3e87c2b7be0d5236119ee6d86437a [file] [log] [blame]
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
buzbee395116c2013-02-27 14:30:25 -0800[diff] [blame]17#ifndef ART_SRC_COMPILER_DEX_QUICK_CODEGEN_H_
18#define ART_SRC_COMPILER_DEX_QUICK_CODEGEN_H_
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]19
Brian Carlstrom265091e2013-01-30 14:08:26 -0800[diff] [blame]20#include "invoke_type.h"
21#include "compiler/dex/compiler_enums.h"
buzbee395116c2013-02-27 14:30:25 -0800[diff] [blame]22#include "compiler/dex/compiler_ir.h"
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]23
24namespace art {
25
26// Set to 1 to measure cost of suspend check.
27#define NO_SUSPEND 0
28
29#define IS_BINARY_OP (1ULL << kIsBinaryOp)
30#define IS_BRANCH (1ULL << kIsBranch)
31#define IS_IT (1ULL << kIsIT)
32#define IS_LOAD (1ULL << kMemLoad)
33#define IS_QUAD_OP (1ULL << kIsQuadOp)
34#define IS_QUIN_OP (1ULL << kIsQuinOp)
35#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp)
36#define IS_STORE (1ULL << kMemStore)
37#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp)
38#define IS_UNARY_OP (1ULL << kIsUnaryOp)
39#define NEEDS_FIXUP (1ULL << kPCRelFixup)
40#define NO_OPERAND (1ULL << kNoOperand)
41#define REG_DEF0 (1ULL << kRegDef0)
42#define REG_DEF1 (1ULL << kRegDef1)
43#define REG_DEFA (1ULL << kRegDefA)
44#define REG_DEFD (1ULL << kRegDefD)
45#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0)
46#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2)
47#define REG_DEF_LIST0 (1ULL << kRegDefList0)
48#define REG_DEF_LIST1 (1ULL << kRegDefList1)
49#define REG_DEF_LR (1ULL << kRegDefLR)
50#define REG_DEF_SP (1ULL << kRegDefSP)
51#define REG_USE0 (1ULL << kRegUse0)
52#define REG_USE1 (1ULL << kRegUse1)
53#define REG_USE2 (1ULL << kRegUse2)
54#define REG_USE3 (1ULL << kRegUse3)
55#define REG_USE4 (1ULL << kRegUse4)
56#define REG_USEA (1ULL << kRegUseA)
57#define REG_USEC (1ULL << kRegUseC)
58#define REG_USED (1ULL << kRegUseD)
59#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0)
60#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2)
61#define REG_USE_LIST0 (1ULL << kRegUseList0)
62#define REG_USE_LIST1 (1ULL << kRegUseList1)
63#define REG_USE_LR (1ULL << kRegUseLR)
64#define REG_USE_PC (1ULL << kRegUsePC)
65#define REG_USE_SP (1ULL << kRegUseSP)
66#define SETS_CCODES (1ULL << kSetsCCodes)
67#define USES_CCODES (1ULL << kUsesCCodes)
68
69// Common combo register usage patterns.
70#define REG_DEF01 (REG_DEF0 | REG_DEF1)
71#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
72#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01)
73#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0)
74#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
75#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
76#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2)
77#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED)
78#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD)
79#define REG_DEFA_USEA (REG_DEFA | REG_USEA)
80#define REG_USE012 (REG_USE01 | REG_USE2)
81#define REG_USE014 (REG_USE01 | REG_USE4)
82#define REG_USE01 (REG_USE0 | REG_USE1)
83#define REG_USE02 (REG_USE0 | REG_USE2)
84#define REG_USE12 (REG_USE1 | REG_USE2)
85#define REG_USE23 (REG_USE2 | REG_USE3)
86
Brian Carlstrom265091e2013-01-30 14:08:26 -0800[diff] [blame]87struct BasicBlock;
88struct CallInfo;
89struct CompilationUnit;
90struct LIR;
91struct MIR;
92struct RegLocation;
93struct RegisterInfo;
94
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]95typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, uint32_t dex_idx,
96 uint32_t method_idx, uintptr_t direct_code,
97 uintptr_t direct_method, InvokeType type);
98
99// Target-specific initialization.
100bool InitArmCodegen(CompilationUnit* cu);
101bool InitMipsCodegen(CompilationUnit* cu);
102bool InitX86Codegen(CompilationUnit* cu);
103
104class Codegen {
105
106 public:
107
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]108 struct SwitchTable {
109 int offset;
110 const uint16_t* table; // Original dex table.
111 int vaddr; // Dalvik offset of switch opcode.
112 LIR* anchor; // Reference instruction for relative offsets.
113 LIR** targets; // Array of case targets.
114 };
115
116 struct FillArrayData {
117 int offset;
118 const uint16_t* table; // Original dex table.
119 int size;
120 int vaddr; // Dalvik offset of FILL_ARRAY_DATA opcode.
121 };
122
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]123 virtual ~Codegen(){};
124
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]125 // Shared by all targets - implemented in ralloc_util.cc
126 void SimpleRegAlloc(CompilationUnit* cu);
127
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]128 // Shared by all targets - implemented in gen_common.cc.
129 void HandleSuspendLaunchPads(CompilationUnit *cu);
130 void HandleIntrinsicLaunchPads(CompilationUnit *cu);
131 void HandleThrowLaunchPads(CompilationUnit *cu);
132 void GenBarrier(CompilationUnit* cu);
133 LIR* GenCheck(CompilationUnit* cu, ConditionCode c_code, ThrowKind kind);
134 LIR* GenImmedCheck(CompilationUnit* cu, ConditionCode c_code, int reg, int imm_val,
135 ThrowKind kind);
136 LIR* GenNullCheck(CompilationUnit* cu, int s_reg, int m_reg, int opt_flags);
137 LIR* GenRegRegCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int reg2,
138 ThrowKind kind);
139 void GenCompareAndBranch(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_src1,
140 RegLocation rl_src2, LIR* taken, LIR* fall_through);
141 void GenCompareZeroAndBranch(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_src,
142 LIR* taken, LIR* fall_through);
143 void GenIntToLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
144 void GenIntNarrowing(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
145 RegLocation rl_src);
146 void GenNewArray(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest,
147 RegLocation rl_src);
148 void GenFilledNewArray(CompilationUnit* cu, CallInfo* info);
149 void GenSput(CompilationUnit* cu, uint32_t field_idx, RegLocation rl_src,
150 bool is_long_or_double, bool is_object);
151 void GenSget(CompilationUnit* cu, uint32_t field_idx, RegLocation rl_dest,
152 bool is_long_or_double, bool is_object);
153 void GenShowTarget(CompilationUnit* cu);
154 void GenIGet(CompilationUnit* cu, uint32_t field_idx, int opt_flags, OpSize size,
155 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object);
156 void GenIPut(CompilationUnit* cu, uint32_t field_idx, int opt_flags, OpSize size,
157 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object);
158 void GenConstClass(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest);
159 void GenConstString(CompilationUnit* cu, uint32_t string_idx, RegLocation rl_dest);
160 void GenNewInstance(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]161 void GenThrow(CompilationUnit* cu, RegLocation rl_src);
162 void GenInstanceof(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_dest,
163 RegLocation rl_src);
164 void GenCheckCast(CompilationUnit* cu, uint32_t type_idx, RegLocation rl_src);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]165 void GenLong3Addr(CompilationUnit* cu, OpKind first_op, OpKind second_op, RegLocation rl_dest,
166 RegLocation rl_src1, RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]167 void GenShiftOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]168 RegLocation rl_src1, RegLocation rl_shift);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]169 void GenArithOpInt(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]170 RegLocation rl_src1, RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]171 void GenArithOpIntLit(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]172 RegLocation rl_src, int lit);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]173 void GenArithOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]174 RegLocation rl_src1, RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]175 void GenConversionCall(CompilationUnit* cu, int func_offset, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]176 RegLocation rl_src);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]177 void GenSuspendTest(CompilationUnit* cu, int opt_flags);
178 void GenSuspendTestAndBranch(CompilationUnit* cu, int opt_flags, LIR* target);
179
180 // Shared by all targets - implemented in gen_invoke.cc.
181 int CallHelperSetup(CompilationUnit* cu, int helper_offset);
182 LIR* CallHelper(CompilationUnit* cu, int r_tgt, int helper_offset, bool safepoint_pc);
183 void CallRuntimeHelperImm(CompilationUnit* cu, int helper_offset, int arg0, bool safepoint_pc);
184 void CallRuntimeHelperReg(CompilationUnit* cu, int helper_offset, int arg0, bool safepoint_pc);
185 void CallRuntimeHelperRegLocation(CompilationUnit* cu, int helper_offset, RegLocation arg0,
186 bool safepoint_pc);
187 void CallRuntimeHelperImmImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
188 bool safepoint_pc);
189 void CallRuntimeHelperImmRegLocation(CompilationUnit* cu, int helper_offset, int arg0,
190 RegLocation arg1, bool safepoint_pc);
191 void CallRuntimeHelperRegLocationImm(CompilationUnit* cu, int helper_offset, RegLocation arg0,
192 int arg1, bool safepoint_pc);
193 void CallRuntimeHelperImmReg(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
194 bool safepoint_pc);
195 void CallRuntimeHelperRegImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
196 bool safepoint_pc);
197 void CallRuntimeHelperImmMethod(CompilationUnit* cu, int helper_offset, int arg0,
198 bool safepoint_pc);
199 void CallRuntimeHelperRegLocationRegLocation(CompilationUnit* cu, int helper_offset,
200 RegLocation arg0, RegLocation arg1,
201 bool safepoint_pc);
202 void CallRuntimeHelperRegReg(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
203 bool safepoint_pc);
204 void CallRuntimeHelperRegRegImm(CompilationUnit* cu, int helper_offset, int arg0, int arg1,
205 int arg2, bool safepoint_pc);
206 void CallRuntimeHelperImmMethodRegLocation(CompilationUnit* cu, int helper_offset, int arg0,
207 RegLocation arg2, bool safepoint_pc);
208 void CallRuntimeHelperImmMethodImm(CompilationUnit* cu, int helper_offset, int arg0, int arg2,
209 bool safepoint_pc);
210 void CallRuntimeHelperImmRegLocationRegLocation(CompilationUnit* cu, int helper_offset,
211 int arg0, RegLocation arg1, RegLocation arg2,
212 bool safepoint_pc);
213 void GenInvoke(CompilationUnit* cu, CallInfo* info);
214 void FlushIns(CompilationUnit* cu, RegLocation* ArgLocs, RegLocation rl_method);
215 int GenDalvikArgsNoRange(CompilationUnit* cu, CallInfo* info, int call_state, LIR** pcrLabel,
216 NextCallInsn next_call_insn, uint32_t dex_idx, uint32_t method_idx,
217 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
218 bool skip_this);
219 int GenDalvikArgsRange(CompilationUnit* cu, CallInfo* info, int call_state, LIR** pcrLabel,
220 NextCallInsn next_call_insn, uint32_t dex_idx, uint32_t method_idx,
221 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
222 bool skip_this);
223 RegLocation InlineTarget(CompilationUnit* cu, CallInfo* info);
224 RegLocation InlineTargetWide(CompilationUnit* cu, CallInfo* info);
225 CallInfo* NewMemCallInfo(CompilationUnit* cu, BasicBlock* bb, MIR* mir, InvokeType type,
226 bool is_range);
227 bool GenInlinedCharAt(CompilationUnit* cu, CallInfo* info);
228 bool GenInlinedStringIsEmptyOrLength(CompilationUnit* cu, CallInfo* info, bool is_empty);
229 bool GenInlinedAbsInt(CompilationUnit *cu, CallInfo* info);
230 bool GenInlinedAbsLong(CompilationUnit *cu, CallInfo* info);
231 bool GenInlinedFloatCvt(CompilationUnit *cu, CallInfo* info);
232 bool GenInlinedDoubleCvt(CompilationUnit *cu, CallInfo* info);
233 bool GenInlinedIndexOf(CompilationUnit* cu, CallInfo* info, bool zero_based);
234 bool GenInlinedStringCompareTo(CompilationUnit* cu, CallInfo* info);
Ian Rogers07ec8e12012-12-01 01:26:51 -0800[diff] [blame]235 bool GenInlinedCurrentThread(CompilationUnit* cu, CallInfo* info);
Jeff Hao5a70fe82013-02-07 15:02:10 -0800[diff] [blame]236 bool GenInlinedUnsafeGet(CompilationUnit* cu, CallInfo* info, bool is_long, bool is_volatile);
237 bool GenInlinedUnsafePut(CompilationUnit* cu, CallInfo* info, bool is_long, bool is_object,
238 bool is_volatile, bool is_ordered);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]239 bool GenIntrinsic(CompilationUnit* cu, CallInfo* info);
240
241 // Shared by all targets - implemented in gen_loadstore.cc.
242 RegLocation LoadCurrMethod(CompilationUnit *cu);
243 void LoadCurrMethodDirect(CompilationUnit *cu, int r_tgt);
244 LIR* LoadConstant(CompilationUnit* cu, int r_dest, int value);
245 LIR* LoadWordDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest);
246 RegLocation LoadValue(CompilationUnit* cu, RegLocation rl_src, RegisterClass op_kind);
247 RegLocation LoadValueWide(CompilationUnit* cu, RegLocation rl_src, RegisterClass op_kind);
248 void LoadValueDirect(CompilationUnit* cu, RegLocation rl_src, int r_dest);
249 void LoadValueDirectFixed(CompilationUnit* cu, RegLocation rl_src, int r_dest);
250 void LoadValueDirectWide(CompilationUnit* cu, RegLocation rl_src, int reg_lo, int reg_hi);
251 void LoadValueDirectWideFixed(CompilationUnit* cu, RegLocation rl_src, int reg_lo, int reg_hi);
252 LIR* StoreWordDisp(CompilationUnit* cu, int rBase, int displacement, int r_src);
253 void StoreValue(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
254 void StoreValueWide(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
255
256 // Required for target - codegen helpers.
257 virtual bool SmallLiteralDivide(CompilationUnit* cu, Instruction::Code dalvik_opcode,
258 RegLocation rl_src, RegLocation rl_dest, int lit) = 0;
259 virtual int LoadHelper(CompilationUnit* cu, int offset) = 0;
260 virtual LIR* LoadBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest,
261 OpSize size, int s_reg) = 0;
262 virtual LIR* LoadBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_dest_lo,
263 int r_dest_hi, int s_reg) = 0;
264 virtual LIR* LoadBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_dest, int scale,
265 OpSize size) = 0;
266 virtual LIR* LoadBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
267 int displacement, int r_dest, int r_dest_hi, OpSize size,
268 int s_reg) = 0;
269 virtual LIR* LoadConstantNoClobber(CompilationUnit* cu, int r_dest, int value) = 0;
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]270 virtual LIR* LoadConstantWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi,
271 int64_t value) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]272 virtual LIR* StoreBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_src,
273 OpSize size) = 0;
274 virtual LIR* StoreBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_src_lo,
275 int r_src_hi) = 0;
276 virtual LIR* StoreBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_src, int scale,
277 OpSize size) = 0;
278 virtual LIR* StoreBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
279 int displacement, int r_src, int r_src_hi, OpSize size,
280 int s_reg) = 0;
281 virtual void MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg) = 0;
282
283 // Required for target - register utilities.
284 virtual bool IsFpReg(int reg) = 0;
285 virtual bool SameRegType(int reg1, int reg2) = 0;
286 virtual int AllocTypedTemp(CompilationUnit* cu, bool fp_hint, int reg_class) = 0;
287 virtual int AllocTypedTempPair(CompilationUnit* cu, bool fp_hint, int reg_class) = 0;
288 virtual int S2d(int low_reg, int high_reg) = 0;
289 virtual int TargetReg(SpecialTargetRegister reg) = 0;
290 virtual RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg) = 0;
291 virtual RegLocation GetReturnAlt(CompilationUnit* cu) = 0;
292 virtual RegLocation GetReturnWideAlt(CompilationUnit* cu) = 0;
293 virtual RegLocation LocCReturn() = 0;
294 virtual RegLocation LocCReturnDouble() = 0;
295 virtual RegLocation LocCReturnFloat() = 0;
296 virtual RegLocation LocCReturnWide() = 0;
297 virtual uint32_t FpRegMask() = 0;
298 virtual uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg) = 0;
299 virtual void AdjustSpillMask(CompilationUnit* cu) = 0;
300 virtual void ClobberCalleeSave(CompilationUnit *cu) = 0;
301 virtual void FlushReg(CompilationUnit* cu, int reg) = 0;
302 virtual void FlushRegWide(CompilationUnit* cu, int reg1, int reg2) = 0;
303 virtual void FreeCallTemps(CompilationUnit* cu) = 0;
304 virtual void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free) = 0;
305 virtual void LockCallTemps(CompilationUnit* cu) = 0;
306 virtual void MarkPreservedSingle(CompilationUnit* cu, int v_reg, int reg) = 0;
307 virtual void CompilerInitializeRegAlloc(CompilationUnit* cu) = 0;
308
309 // Required for target - miscellaneous.
310 virtual AssemblerStatus AssembleInstructions(CompilationUnit* cu, uintptr_t start_addr) = 0;
311 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0;
312 virtual void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir) = 0;
313 virtual const char* GetTargetInstFmt(int opcode) = 0;
314 virtual const char* GetTargetInstName(int opcode) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]315 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0;
316 virtual uint64_t GetPCUseDefEncoding() = 0;
317 virtual uint64_t GetTargetInstFlags(int opcode) = 0;
318 virtual int GetInsnSize(LIR* lir) = 0;
319 virtual bool IsUnconditionalBranch(LIR* lir) = 0;
320
321 // Required for target - Dalvik-level generators.
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]322 virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]323 RegLocation rl_src1, RegLocation rl_src2) = 0;
324 virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
325 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]326 virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]327 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]328 virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]329 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]330 virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]331 RegLocation rl_dest, RegLocation rl_src1,
332 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]333 virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]334 RegLocation rl_src1, RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]335 virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]336 RegLocation rl_src1, RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]337 virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]338 RegLocation rl_src) = 0;
339 virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier) = 0;
340 virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min) = 0;
341 virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]342 virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
343 virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]344 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]345 virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]346 RegLocation rl_src2) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]347 virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]348 RegLocation rl_src2) = 0;
349 virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
350 int offset, ThrowKind kind) = 0;
351 virtual RegLocation GenDivRem(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int reg_hi,
352 bool is_div) = 0;
353 virtual RegLocation GenDivRemLit(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int lit,
354 bool is_div) = 0;
355 virtual void GenCmpLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
356 RegLocation rl_src2) = 0;
357 virtual void GenDivZeroCheck(CompilationUnit* cu, int reg_lo, int reg_hi) = 0;
358 virtual void GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs,
359 RegLocation rl_method) = 0;
360 virtual void GenExitSequence(CompilationUnit* cu) = 0;
361 virtual void GenFillArrayData(CompilationUnit* cu, uint32_t table_offset,
362 RegLocation rl_src) = 0;
363 virtual void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
364 bool is_double) = 0;
365 virtual void GenFusedLongCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir) = 0;
buzbeef662a7c2013-02-12 16:19:43 -0800[diff] [blame]366 virtual void GenSelect(CompilationUnit* cu, BasicBlock* bb, MIR* mir) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]367 virtual void GenMemBarrier(CompilationUnit* cu, MemBarrierKind barrier_kind) = 0;
368 virtual void GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src) = 0;
369 virtual void GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src) = 0;
jeffhao1eab9582013-01-22 13:33:52 -0800[diff] [blame]370 virtual void GenMoveException(CompilationUnit* cu, RegLocation rl_dest) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]371 virtual void GenMultiplyByTwoBitMultiplier(CompilationUnit* cu, RegLocation rl_src,
372 RegLocation rl_result, int lit, int first_bit,
373 int second_bit) = 0;
374 virtual void GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
375 virtual void GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src) = 0;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]376 virtual void GenPackedSwitch(CompilationUnit* cu, MIR* mir, uint32_t table_offset,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]377 RegLocation rl_src) = 0;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]378 virtual void GenSparseSwitch(CompilationUnit* cu, MIR* mir, uint32_t table_offset,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]379 RegLocation rl_src) = 0;
380 virtual void GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
381 SpecialCaseHandler special_case) = 0;
buzbeee6285f92012-12-06 15:57:46 -0800[diff] [blame]382 virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
383 RegLocation rl_index, RegLocation rl_src, int scale) = 0;
384 virtual void GenArrayGet(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
385 RegLocation rl_index, RegLocation rl_dest, int scale) = 0;
386 virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
387 RegLocation rl_index, RegLocation rl_src, int scale) = 0;
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame]388 virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]389 RegLocation rl_dest, RegLocation rl_src1,
390 RegLocation rl_shift) = 0;
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]391
392 // Required for target - single operation generators.
393 virtual LIR* OpUnconditionalBranch(CompilationUnit* cu, LIR* target) = 0;
394 virtual LIR* OpCmpBranch(CompilationUnit* cu, ConditionCode cond, int src1, int src2,
395 LIR* target) = 0;
396 virtual LIR* OpCmpImmBranch(CompilationUnit* cu, ConditionCode cond, int reg, int check_value,
397 LIR* target) = 0;
398 virtual LIR* OpCondBranch(CompilationUnit* cu, ConditionCode cc, LIR* target) = 0;
399 virtual LIR* OpDecAndBranch(CompilationUnit* cu, ConditionCode c_code, int reg,
400 LIR* target) = 0;
401 virtual LIR* OpFpRegCopy(CompilationUnit* cu, int r_dest, int r_src) = 0;
402 virtual LIR* OpIT(CompilationUnit* cu, ConditionCode cond, const char* guide) = 0;
403 virtual LIR* OpMem(CompilationUnit* cu, OpKind op, int rBase, int disp) = 0;
404 virtual LIR* OpPcRelLoad(CompilationUnit* cu, int reg, LIR* target) = 0;
405 virtual LIR* OpReg(CompilationUnit* cu, OpKind op, int r_dest_src) = 0;
406 virtual LIR* OpRegCopy(CompilationUnit* cu, int r_dest, int r_src) = 0;
407 virtual LIR* OpRegCopyNoInsert(CompilationUnit* cu, int r_dest, int r_src) = 0;
408 virtual LIR* OpRegImm(CompilationUnit* cu, OpKind op, int r_dest_src1, int value) = 0;
409 virtual LIR* OpRegMem(CompilationUnit* cu, OpKind op, int r_dest, int rBase, int offset) = 0;
410 virtual LIR* OpRegReg(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2) = 0;
411 virtual LIR* OpRegRegImm(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int value) = 0;
412 virtual LIR* OpRegRegReg(CompilationUnit* cu, OpKind op, int r_dest, int r_src1,
413 int r_src2) = 0;
414 virtual LIR* OpTestSuspend(CompilationUnit* cu, LIR* target) = 0;
415 virtual LIR* OpThreadMem(CompilationUnit* cu, OpKind op, int thread_offset) = 0;
416 virtual LIR* OpVldm(CompilationUnit* cu, int rBase, int count) = 0;
417 virtual LIR* OpVstm(CompilationUnit* cu, int rBase, int count) = 0;
418 virtual void OpLea(CompilationUnit* cu, int rBase, int reg1, int reg2, int scale,
419 int offset) = 0;
420 virtual void OpRegCopyWide(CompilationUnit* cu, int dest_lo, int dest_hi, int src_lo,
421 int src_hi) = 0;
422 virtual void OpTlsCmp(CompilationUnit* cu, int offset, int val) = 0;
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]423 virtual bool InexpensiveConstantInt(int32_t value) = 0;
424 virtual bool InexpensiveConstantFloat(int32_t value) = 0;
425 virtual bool InexpensiveConstantLong(int64_t value) = 0;
426 virtual bool InexpensiveConstantDouble(int64_t value) = 0;
buzbee5f61f672012-11-28 17:22:17 -0800[diff] [blame]427
428 // Temp workaround
429 void Workaround7250540(CompilationUnit* cu, RegLocation rl_dest, int value);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]430 }; // Class Codegen
431
432} // namespace art
433
buzbee395116c2013-02-27 14:30:25 -0800[diff] [blame]434#endif // ART_SRC_COMPILER_DEX_QUICK_CODEGEN_H_