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Brian Carlstrom7940e442013-07-12 13:46:57 -07001/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/* This file contains codegen for the X86 ISA */
18
19#include "codegen_x86.h"
20#include "dex/quick/mir_to_lir-inl.h"
21#include "x86_lir.h"
22
23namespace art {
24
25void X86Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
Vladimir Marko5816ed42013-11-27 17:04:20 +000026 const InlineMethod& special) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070027 // TODO
28}
29
30/*
31 * The sparse table in the literal pool is an array of <key,displacement>
32 * pairs.
33 */
buzbee0d829482013-10-11 15:24:55 -070034void X86Mir2Lir::GenSparseSwitch(MIR* mir, DexOffset table_offset,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -070035 RegLocation rl_src) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070036 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
37 if (cu_->verbose) {
38 DumpSparseSwitchTable(table);
39 }
40 int entries = table[1];
buzbee0d829482013-10-11 15:24:55 -070041 const int32_t* keys = reinterpret_cast<const int32_t*>(&table[2]);
42 const int32_t* targets = &keys[entries];
Brian Carlstrom7940e442013-07-12 13:46:57 -070043 rl_src = LoadValue(rl_src, kCoreReg);
44 for (int i = 0; i < entries; i++) {
45 int key = keys[i];
46 BasicBlock* case_block =
47 mir_graph_->FindBlock(current_dalvik_offset_ + targets[i]);
48 OpCmpImmBranch(kCondEq, rl_src.low_reg, key,
49 &block_label_list_[case_block->id]);
50 }
51}
52
53/*
54 * Code pattern will look something like:
55 *
56 * mov r_val, ..
57 * call 0
58 * pop r_start_of_method
59 * sub r_start_of_method, ..
60 * mov r_key_reg, r_val
61 * sub r_key_reg, low_key
62 * cmp r_key_reg, size-1 ; bound check
63 * ja done
64 * mov r_disp, [r_start_of_method + r_key_reg * 4 + table_offset]
65 * add r_start_of_method, r_disp
66 * jmp r_start_of_method
67 * done:
68 */
buzbee0d829482013-10-11 15:24:55 -070069void X86Mir2Lir::GenPackedSwitch(MIR* mir, DexOffset table_offset,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -070070 RegLocation rl_src) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070071 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
72 if (cu_->verbose) {
73 DumpPackedSwitchTable(table);
74 }
75 // Add the table to the list - we'll process it later
buzbee0d829482013-10-11 15:24:55 -070076 SwitchTable* tab_rec =
77 static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), ArenaAllocator::kAllocData));
Brian Carlstrom7940e442013-07-12 13:46:57 -070078 tab_rec->table = table;
79 tab_rec->vaddr = current_dalvik_offset_;
80 int size = table[1];
Mathieu Chartierf6c4b3b2013-08-24 16:11:37 -070081 tab_rec->targets = static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*),
82 ArenaAllocator::kAllocLIR));
Brian Carlstrom7940e442013-07-12 13:46:57 -070083 switch_tables_.Insert(tab_rec);
84
85 // Get the switch value
86 rl_src = LoadValue(rl_src, kCoreReg);
Brian Carlstrom7934ac22013-07-26 10:54:15 -070087 // NewLIR0(kX86Bkpt);
Mark Mendell67c39c42014-01-31 17:28:00 -080088
89 // Materialize a pointer to the switch table
90 int start_of_method_reg;
91 if (base_of_code_ != nullptr) {
92 // We can use the saved value.
93 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low);
94 rl_method = LoadValue(rl_method, kCoreReg);
95 start_of_method_reg = rl_method.low_reg;
96 } else {
97 start_of_method_reg = AllocTemp();
98 NewLIR1(kX86StartOfMethod, start_of_method_reg);
99 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700100 int low_key = s4FromSwitchData(&table[2]);
101 int keyReg;
102 // Remove the bias, if necessary
103 if (low_key == 0) {
104 keyReg = rl_src.low_reg;
105 } else {
106 keyReg = AllocTemp();
107 OpRegRegImm(kOpSub, keyReg, rl_src.low_reg, low_key);
108 }
109 // Bounds check - if < 0 or >= size continue following switch
110 OpRegImm(kOpCmp, keyReg, size-1);
111 LIR* branch_over = OpCondBranch(kCondHi, NULL);
112
113 // Load the displacement from the switch table
114 int disp_reg = AllocTemp();
buzbee0d829482013-10-11 15:24:55 -0700115 NewLIR5(kX86PcRelLoadRA, disp_reg, start_of_method_reg, keyReg, 2, WrapPointer(tab_rec));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700116 // Add displacement to start of method
117 OpRegReg(kOpAdd, start_of_method_reg, disp_reg);
118 // ..and go!
119 LIR* switch_branch = NewLIR1(kX86JmpR, start_of_method_reg);
120 tab_rec->anchor = switch_branch;
121
122 /* branch_over target here */
123 LIR* target = NewLIR0(kPseudoTargetLabel);
124 branch_over->target = target;
125}
126
127/*
128 * Array data table format:
129 * ushort ident = 0x0300 magic value
130 * ushort width width of each element in the table
131 * uint size number of elements in the table
132 * ubyte data[size*width] table of data values (may contain a single-byte
133 * padding at the end)
134 *
135 * Total size is 4+(width * size + 1)/2 16-bit code units.
136 */
buzbee0d829482013-10-11 15:24:55 -0700137void X86Mir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700138 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
139 // Add the table to the list - we'll process it later
buzbee0d829482013-10-11 15:24:55 -0700140 FillArrayData* tab_rec =
Mathieu Chartierf6c4b3b2013-08-24 16:11:37 -0700141 static_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), ArenaAllocator::kAllocData));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700142 tab_rec->table = table;
143 tab_rec->vaddr = current_dalvik_offset_;
144 uint16_t width = tab_rec->table[1];
145 uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16);
146 tab_rec->size = (size * width) + 8;
147
148 fill_array_data_.Insert(tab_rec);
149
150 // Making a call - use explicit registers
151 FlushAllRegs(); /* Everything to home location */
152 LoadValueDirectFixed(rl_src, rX86_ARG0);
153 // Materialize a pointer to the fill data image
Mark Mendell67c39c42014-01-31 17:28:00 -0800154 if (base_of_code_ != nullptr) {
155 // We can use the saved value.
156 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low);
157 LoadValueDirect(rl_method, rX86_ARG2);
158 } else {
159 NewLIR1(kX86StartOfMethod, rX86_ARG2);
160 }
buzbee0d829482013-10-11 15:24:55 -0700161 NewLIR2(kX86PcRelAdr, rX86_ARG1, WrapPointer(tab_rec));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700162 NewLIR2(kX86Add32RR, rX86_ARG1, rX86_ARG2);
Ian Rogers468532e2013-08-05 10:56:33 -0700163 CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData), rX86_ARG0,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700164 rX86_ARG1, true);
165}
166
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700167void X86Mir2Lir::GenMoveException(RegLocation rl_dest) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700168 int ex_offset = Thread::ExceptionOffset().Int32Value();
169 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
170 NewLIR2(kX86Mov32RT, rl_result.low_reg, ex_offset);
171 NewLIR2(kX86Mov32TI, ex_offset, 0);
172 StoreValue(rl_dest, rl_result);
173}
174
175/*
176 * Mark garbage collection card. Skip if the value we're storing is null.
177 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700178void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700179 int reg_card_base = AllocTemp();
180 int reg_card_no = AllocTemp();
181 LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
182 NewLIR2(kX86Mov32RT, reg_card_base, Thread::CardTableOffset().Int32Value());
183 OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift);
184 StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0,
185 kUnsignedByte);
186 LIR* target = NewLIR0(kPseudoTargetLabel);
187 branch_over->target = target;
188 FreeTemp(reg_card_base);
189 FreeTemp(reg_card_no);
190}
191
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700192void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700193 /*
194 * On entry, rX86_ARG0, rX86_ARG1, rX86_ARG2 are live. Let the register
195 * allocation mechanism know so it doesn't try to use any of them when
196 * expanding the frame or flushing. This leaves the utility
197 * code with no spare temps.
198 */
199 LockTemp(rX86_ARG0);
200 LockTemp(rX86_ARG1);
201 LockTemp(rX86_ARG2);
202
203 /* Build frame, return address already on stack */
204 OpRegImm(kOpSub, rX86_SP, frame_size_ - 4);
205
206 /*
207 * We can safely skip the stack overflow check if we're
208 * a leaf *and* our frame size < fudge factor.
209 */
210 bool skip_overflow_check = (mir_graph_->MethodIsLeaf() &&
211 (static_cast<size_t>(frame_size_) <
212 Thread::kStackOverflowReservedBytes));
213 NewLIR0(kPseudoMethodEntry);
214 /* Spill core callee saves */
215 SpillCoreRegs();
216 /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
217 DCHECK_EQ(num_fp_spills_, 0);
218 if (!skip_overflow_check) {
219 // cmp rX86_SP, fs:[stack_end_]; jcc throw_launchpad
220 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kThrowStackOverflow, 0, 0, 0, 0);
Ian Rogers468532e2013-08-05 10:56:33 -0700221 OpRegThreadMem(kOpCmp, rX86_SP, Thread::StackEndOffset());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700222 OpCondBranch(kCondUlt, tgt);
223 // Remember branch target - will process later
224 throw_launchpads_.Insert(tgt);
225 }
226
227 FlushIns(ArgLocs, rl_method);
228
Mark Mendell67c39c42014-01-31 17:28:00 -0800229 if (base_of_code_ != nullptr) {
230 // We have been asked to save the address of the method start for later use.
231 NewLIR1(kX86StartOfMethod, rX86_ARG0);
232 int displacement = SRegOffset(base_of_code_->s_reg_low);
233 StoreBaseDisp(rX86_SP, displacement, rX86_ARG0, kWord);
234 }
235
Brian Carlstrom7940e442013-07-12 13:46:57 -0700236 FreeTemp(rX86_ARG0);
237 FreeTemp(rX86_ARG1);
238 FreeTemp(rX86_ARG2);
239}
240
241void X86Mir2Lir::GenExitSequence() {
242 /*
243 * In the exit path, rX86_RET0/rX86_RET1 are live - make sure they aren't
244 * allocated by the register utilities as temps.
245 */
246 LockTemp(rX86_RET0);
247 LockTemp(rX86_RET1);
248
249 NewLIR0(kPseudoMethodExit);
250 UnSpillCoreRegs();
251 /* Remove frame except for return address */
252 OpRegImm(kOpAdd, rX86_SP, frame_size_ - 4);
253 NewLIR0(kX86Ret);
254}
255
256} // namespace art