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review.blissroms.org / platform_art / a0a16105423459287497a98129dcba2828ccd7f0 / . / runtime / interpreter / mterp / out / mterp_arm.S
blob: 9091b6f5bf2c80b47cd4aee0d588f4033dc3e089 [file] [log] [blame]
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1/*
2 * This file was generated automatically by gen-mterp.py for 'arm'.
3 *
4 * --> DO NOT EDIT <--
5 */
6
7/* File: arm/header.S */
8/*
9 * Copyright (C) 2016 The Android Open Source Project
10 *
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
14 *
15 * http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 */
23
24/*
25 Art assembly interpreter notes:
26
27 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't
28 handle invoke, allows higher-level code to create frame & shadow frame.
29
30 Once that's working, support direct entry code & eliminate shadow frame (and
31 excess locals allocation.
32
33 Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the
34 base of the vreg array within the shadow frame. Access the other fields,
35 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue
36 the shadow frame mechanism of double-storing object references - via rFP &
37 number_of_vregs_.
38
39 */
40
41/*
42ARM EABI general notes:
43
44r0-r3 hold first 4 args to a method; they are not preserved across method calls
45r4-r8 are available for general use
46r9 is given special treatment in some situations, but not for us
47r10 (sl) seems to be generally available
48r11 (fp) is used by gcc (unless -fomit-frame-pointer is set)
49r12 (ip) is scratch -- not preserved across method calls
50r13 (sp) should be managed carefully in case a signal arrives
51r14 (lr) must be preserved
52r15 (pc) can be tinkered with directly
53
54r0 holds returns of <= 4 bytes
55r0-r1 hold returns of 8 bytes, low word in r0
56
57Callee must save/restore r4+ (except r12) if it modifies them. If VFP
58is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved,
59s0-s15 (d0-d7, q0-a3) do not need to be.
60
61Stack is "full descending". Only the arguments that don't fit in the first 4
62registers are placed on the stack. "sp" points at the first stacked argument
63(i.e. the 5th arg).
64
65VFP: single-precision results in s0, double-precision results in d0.
66
67In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
6864-bit quantities (long long, double) must be 64-bit aligned.
69*/
70
71/*
72Mterp and ARM notes:
73
74The following registers have fixed assignments:
75
76 reg nick purpose
77 r4 rPC interpreted program counter, used for fetching instructions
78 r5 rFP interpreted frame pointer, used for accessing locals and args
79 r6 rSELF self (Thread) pointer
80 r7 rINST first 16-bit code unit of current instruction
81 r8 rIBASE interpreted instruction base pointer, used for computed goto
82 r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later).
83
84Macros are provided for common operations. Each macro MUST emit only
85one instruction to make instruction-counting easier. They MUST NOT alter
86unspecified registers or condition codes.
87*/
88
89/*
90 * This is a #include, not a %include, because we want the C pre-processor
91 * to expand the macros into assembler assignment statements.
92 */
93#include "asm_support.h"
94
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]95#define MTERP_PROFILE_BRANCHES 1
96
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]97/* During bringup, we'll use the shadow frame model instead of rFP */
98/* single-purpose registers, given names for clarity */
99#define rPC r4
100#define rFP r5
101#define rSELF r6
102#define rINST r7
103#define rIBASE r8
104#define rREFS r11
105
106/*
107 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So,
108 * to access other shadow frame fields, we need to use a backwards offset. Define those here.
109 */
110#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET)
111#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET)
112#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET)
113#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET)
114#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
115#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
116#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
117#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
118#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET)
119
120/*
121 *
122 * The reference interpreter performs explicit suspect checks, which is somewhat wasteful.
123 * Dalvik's interpreter folded suspend checks into the jump table mechanism, and eventually
124 * mterp should do so as well.
125 */
126#define MTERP_SUSPEND 0
127
128/*
129 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must
130 * be done *before* something throws.
131 *
132 * It's okay to do this more than once.
133 *
134 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped
135 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction
136 * offset into the code_items_[] array. For effiency, we will "export" the
137 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC
138 * to convert to a dex pc when needed.
139 */
140.macro EXPORT_PC
141 str rPC, [rFP, #OFF_FP_DEX_PC_PTR]
142.endm
143
144.macro EXPORT_DEX_PC tmp
145 ldr \tmp, [rFP, #OFF_FP_CODE_ITEM]
146 str rPC, [rFP, #OFF_FP_DEX_PC_PTR]
147 add \tmp, #CODEITEM_INSNS_OFFSET
148 sub \tmp, rPC, \tmp
149 asr \tmp, #1
150 str \tmp, [rFP, #OFF_FP_DEX_PC]
151.endm
152
153/*
154 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
155 */
156.macro FETCH_INST
157 ldrh rINST, [rPC]
158.endm
159
160/*
161 * Fetch the next instruction from the specified offset. Advances rPC
162 * to point to the next instruction. "_count" is in 16-bit code units.
163 *
164 * Because of the limited size of immediate constants on ARM, this is only
165 * suitable for small forward movements (i.e. don't try to implement "goto"
166 * with this).
167 *
168 * This must come AFTER anything that can throw an exception, or the
169 * exception catch may miss. (This also implies that it must come after
170 * EXPORT_PC.)
171 */
172.macro FETCH_ADVANCE_INST count
173 ldrh rINST, [rPC, #((\count)*2)]!
174.endm
175
176/*
177 * The operation performed here is similar to FETCH_ADVANCE_INST, except the
178 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
179 */
180.macro PREFETCH_ADVANCE_INST dreg, sreg, count
181 ldrh \dreg, [\sreg, #((\count)*2)]!
182.endm
183
184/*
185 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load
186 * rINST ahead of possible exception point. Be sure to manually advance rPC
187 * later.
188 */
189.macro PREFETCH_INST count
190 ldrh rINST, [rPC, #((\count)*2)]
191.endm
192
193/* Advance rPC by some number of code units. */
194.macro ADVANCE count
195 add rPC, #((\count)*2)
196.endm
197
198/*
199 * Fetch the next instruction from an offset specified by _reg. Updates
200 * rPC to point to the next instruction. "_reg" must specify the distance
201 * in bytes, *not* 16-bit code units, and may be a signed value.
202 *
203 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
204 * bits that hold the shift distance are used for the half/byte/sign flags.
205 * In some cases we can pre-double _reg for free, so we require a byte offset
206 * here.
207 */
208.macro FETCH_ADVANCE_INST_RB reg
209 ldrh rINST, [rPC, \reg]!
210.endm
211
212/*
213 * Fetch a half-word code unit from an offset past the current PC. The
214 * "_count" value is in 16-bit code units. Does not advance rPC.
215 *
216 * The "_S" variant works the same but treats the value as signed.
217 */
218.macro FETCH reg, count
219 ldrh \reg, [rPC, #((\count)*2)]
220.endm
221
222.macro FETCH_S reg, count
223 ldrsh \reg, [rPC, #((\count)*2)]
224.endm
225
226/*
227 * Fetch one byte from an offset past the current PC. Pass in the same
228 * "_count" as you would for FETCH, and an additional 0/1 indicating which
229 * byte of the halfword you want (lo/hi).
230 */
231.macro FETCH_B reg, count, byte
232 ldrb \reg, [rPC, #((\count)*2+(\byte))]
233.endm
234
235/*
236 * Put the instruction's opcode field into the specified register.
237 */
238.macro GET_INST_OPCODE reg
239 and \reg, rINST, #255
240.endm
241
242/*
243 * Put the prefetched instruction's opcode field into the specified register.
244 */
245.macro GET_PREFETCHED_OPCODE oreg, ireg
246 and \oreg, \ireg, #255
247.endm
248
249/*
250 * Begin executing the opcode in _reg. Because this only jumps within the
251 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork.
252 */
253.macro GOTO_OPCODE reg
254 add pc, rIBASE, \reg, lsl #7
255.endm
256.macro GOTO_OPCODE_BASE base,reg
257 add pc, \base, \reg, lsl #7
258.endm
259
260/*
261 * Get/set the 32-bit value from a Dalvik register.
262 */
263.macro GET_VREG reg, vreg
264 ldr \reg, [rFP, \vreg, lsl #2]
265.endm
266.macro SET_VREG reg, vreg
267 str \reg, [rFP, \vreg, lsl #2]
268 mov \reg, #0
269 str \reg, [rREFS, \vreg, lsl #2]
270.endm
271.macro SET_VREG_OBJECT reg, vreg, tmpreg
272 str \reg, [rFP, \vreg, lsl #2]
273 str \reg, [rREFS, \vreg, lsl #2]
274.endm
275
276/*
277 * Convert a virtual register index into an address.
278 */
279.macro VREG_INDEX_TO_ADDR reg, vreg
280 add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */
281.endm
282
283/*
284 * Refresh handler table.
285 */
286.macro REFRESH_IBASE
287 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET]
288.endm
289
290/* File: arm/entry.S */
291/*
292 * Copyright (C) 2016 The Android Open Source Project
293 *
294 * Licensed under the Apache License, Version 2.0 (the "License");
295 * you may not use this file except in compliance with the License.
296 * You may obtain a copy of the License at
297 *
298 * http://www.apache.org/licenses/LICENSE-2.0
299 *
300 * Unless required by applicable law or agreed to in writing, software
301 * distributed under the License is distributed on an "AS IS" BASIS,
302 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
303 * See the License for the specific language governing permissions and
304 * limitations under the License.
305 */
306/*
307 * Interpreter entry point.
308 */
309
310 .text
311 .align 2
312 .global ExecuteMterpImpl
313 .type ExecuteMterpImpl, %function
314
315/*
316 * On entry:
317 * r0 Thread* self/
318 * r1 code_item
319 * r2 ShadowFrame
320 * r3 JValue* result_register
321 *
322 */
323
324ExecuteMterpImpl:
325 .fnstart
326 .save {r4-r10,fp,lr}
327 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
328 .pad #4
329 sub sp, sp, #4 @ align 64
330
331 /* Remember the return register */
332 str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET]
333
334 /* Remember the code_item */
335 str r1, [r2, #SHADOWFRAME_CODE_ITEM_OFFSET]
336
337 /* set up "named" registers */
338 mov rSELF, r0
339 ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET]
340 add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to insns[] (i.e. - the dalivk byte code).
341 add rREFS, rFP, r0, lsl #2 @ point to reference array in shadow frame
342 ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc.
343 add rPC, r1, #CODEITEM_INSNS_OFFSET @ Point to base of insns[]
344 add rPC, rPC, r0, lsl #1 @ Create direct pointer to 1st dex opcode
345 EXPORT_PC
346
347 /* Starting ibase */
348 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET]
349
350 /* start executing the instruction at rPC */
351 FETCH_INST @ load rINST from rPC
352 GET_INST_OPCODE ip @ extract opcode from rINST
353 GOTO_OPCODE ip @ jump to next instruction
354 /* NOTE: no fallthrough */
355
356
357 .global artMterpAsmInstructionStart
358 .type artMterpAsmInstructionStart, %function
359artMterpAsmInstructionStart = .L_op_nop
360 .text
361
362/* ------------------------------ */
363 .balign 128
364.L_op_nop: /* 0x00 */
365/* File: arm/op_nop.S */
366 FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST
367 GET_INST_OPCODE ip @ ip<- opcode from rINST
368 GOTO_OPCODE ip @ execute it
369
370/* ------------------------------ */
371 .balign 128
372.L_op_move: /* 0x01 */
373/* File: arm/op_move.S */
374 /* for move, move-object, long-to-int */
375 /* op vA, vB */
376 mov r1, rINST, lsr #12 @ r1<- B from 15:12
377 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8
378 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
379 GET_VREG r2, r1 @ r2<- fp[B]
380 GET_INST_OPCODE ip @ ip<- opcode from rINST
381 .if 0
382 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2
383 .else
384 SET_VREG r2, r0 @ fp[A]<- r2
385 .endif
386 GOTO_OPCODE ip @ execute next instruction
387
388/* ------------------------------ */
389 .balign 128
390.L_op_move_from16: /* 0x02 */
391/* File: arm/op_move_from16.S */
392 /* for: move/from16, move-object/from16 */
393 /* op vAA, vBBBB */
394 FETCH r1, 1 @ r1<- BBBB
395 mov r0, rINST, lsr #8 @ r0<- AA
396 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
397 GET_VREG r2, r1 @ r2<- fp[BBBB]
398 GET_INST_OPCODE ip @ extract opcode from rINST
399 .if 0
400 SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2
401 .else
402 SET_VREG r2, r0 @ fp[AA]<- r2
403 .endif
404 GOTO_OPCODE ip @ jump to next instruction
405
406/* ------------------------------ */
407 .balign 128
408.L_op_move_16: /* 0x03 */
409/* File: arm/op_move_16.S */
410 /* for: move/16, move-object/16 */
411 /* op vAAAA, vBBBB */
412 FETCH r1, 2 @ r1<- BBBB
413 FETCH r0, 1 @ r0<- AAAA
414 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST
415 GET_VREG r2, r1 @ r2<- fp[BBBB]
416 GET_INST_OPCODE ip @ extract opcode from rINST
417 .if 0
418 SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2
419 .else
420 SET_VREG r2, r0 @ fp[AAAA]<- r2
421 .endif
422 GOTO_OPCODE ip @ jump to next instruction
423
424/* ------------------------------ */
425 .balign 128
426.L_op_move_wide: /* 0x04 */
427/* File: arm/op_move_wide.S */
428 /* move-wide vA, vB */
429 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
430 mov r3, rINST, lsr #12 @ r3<- B
431 ubfx r2, rINST, #8, #4 @ r2<- A
432 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
433 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
434 ldmia r3, {r0-r1} @ r0/r1<- fp[B]
435 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
436 GET_INST_OPCODE ip @ extract opcode from rINST
437 stmia r2, {r0-r1} @ fp[A]<- r0/r1
438 GOTO_OPCODE ip @ jump to next instruction
439
440/* ------------------------------ */
441 .balign 128
442.L_op_move_wide_from16: /* 0x05 */
443/* File: arm/op_move_wide_from16.S */
444 /* move-wide/from16 vAA, vBBBB */
445 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
446 FETCH r3, 1 @ r3<- BBBB
447 mov r2, rINST, lsr #8 @ r2<- AA
448 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
449 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
450 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
451 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
452 GET_INST_OPCODE ip @ extract opcode from rINST
453 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
454 GOTO_OPCODE ip @ jump to next instruction
455
456/* ------------------------------ */
457 .balign 128
458.L_op_move_wide_16: /* 0x06 */
459/* File: arm/op_move_wide_16.S */
460 /* move-wide/16 vAAAA, vBBBB */
461 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
462 FETCH r3, 2 @ r3<- BBBB
463 FETCH r2, 1 @ r2<- AAAA
464 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
465 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA]
466 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
467 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST
468 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1
469 GET_INST_OPCODE ip @ extract opcode from rINST
470 GOTO_OPCODE ip @ jump to next instruction
471
472/* ------------------------------ */
473 .balign 128
474.L_op_move_object: /* 0x07 */
475/* File: arm/op_move_object.S */
476/* File: arm/op_move.S */
477 /* for move, move-object, long-to-int */
478 /* op vA, vB */
479 mov r1, rINST, lsr #12 @ r1<- B from 15:12
480 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8
481 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
482 GET_VREG r2, r1 @ r2<- fp[B]
483 GET_INST_OPCODE ip @ ip<- opcode from rINST
484 .if 1
485 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2
486 .else
487 SET_VREG r2, r0 @ fp[A]<- r2
488 .endif
489 GOTO_OPCODE ip @ execute next instruction
490
491
492/* ------------------------------ */
493 .balign 128
494.L_op_move_object_from16: /* 0x08 */
495/* File: arm/op_move_object_from16.S */
496/* File: arm/op_move_from16.S */
497 /* for: move/from16, move-object/from16 */
498 /* op vAA, vBBBB */
499 FETCH r1, 1 @ r1<- BBBB
500 mov r0, rINST, lsr #8 @ r0<- AA
501 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
502 GET_VREG r2, r1 @ r2<- fp[BBBB]
503 GET_INST_OPCODE ip @ extract opcode from rINST
504 .if 1
505 SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2
506 .else
507 SET_VREG r2, r0 @ fp[AA]<- r2
508 .endif
509 GOTO_OPCODE ip @ jump to next instruction
510
511
512/* ------------------------------ */
513 .balign 128
514.L_op_move_object_16: /* 0x09 */
515/* File: arm/op_move_object_16.S */
516/* File: arm/op_move_16.S */
517 /* for: move/16, move-object/16 */
518 /* op vAAAA, vBBBB */
519 FETCH r1, 2 @ r1<- BBBB
520 FETCH r0, 1 @ r0<- AAAA
521 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST
522 GET_VREG r2, r1 @ r2<- fp[BBBB]
523 GET_INST_OPCODE ip @ extract opcode from rINST
524 .if 1
525 SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2
526 .else
527 SET_VREG r2, r0 @ fp[AAAA]<- r2
528 .endif
529 GOTO_OPCODE ip @ jump to next instruction
530
531
532/* ------------------------------ */
533 .balign 128
534.L_op_move_result: /* 0x0a */
535/* File: arm/op_move_result.S */
536 /* for: move-result, move-result-object */
537 /* op vAA */
538 mov r2, rINST, lsr #8 @ r2<- AA
539 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
540 ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType.
541 ldr r0, [r0] @ r0 <- result.i.
542 GET_INST_OPCODE ip @ extract opcode from rINST
543 .if 0
544 SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0
545 .else
546 SET_VREG r0, r2 @ fp[AA]<- r0
547 .endif
548 GOTO_OPCODE ip @ jump to next instruction
549
550/* ------------------------------ */
551 .balign 128
552.L_op_move_result_wide: /* 0x0b */
553/* File: arm/op_move_result_wide.S */
554 /* move-result-wide vAA */
555 mov r2, rINST, lsr #8 @ r2<- AA
556 ldr r3, [rFP, #OFF_FP_RESULT_REGISTER]
557 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
558 ldmia r3, {r0-r1} @ r0/r1<- retval.j
559 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
560 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
561 GET_INST_OPCODE ip @ extract opcode from rINST
562 GOTO_OPCODE ip @ jump to next instruction
563
564/* ------------------------------ */
565 .balign 128
566.L_op_move_result_object: /* 0x0c */
567/* File: arm/op_move_result_object.S */
568/* File: arm/op_move_result.S */
569 /* for: move-result, move-result-object */
570 /* op vAA */
571 mov r2, rINST, lsr #8 @ r2<- AA
572 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
573 ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType.
574 ldr r0, [r0] @ r0 <- result.i.
575 GET_INST_OPCODE ip @ extract opcode from rINST
576 .if 1
577 SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0
578 .else
579 SET_VREG r0, r2 @ fp[AA]<- r0
580 .endif
581 GOTO_OPCODE ip @ jump to next instruction
582
583
584/* ------------------------------ */
585 .balign 128
586.L_op_move_exception: /* 0x0d */
587/* File: arm/op_move_exception.S */
588 /* move-exception vAA */
589 mov r2, rINST, lsr #8 @ r2<- AA
590 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
591 mov r1, #0 @ r1<- 0
592 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
593 SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj
594 GET_INST_OPCODE ip @ extract opcode from rINST
595 str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception
596 GOTO_OPCODE ip @ jump to next instruction
597
598/* ------------------------------ */
599 .balign 128
600.L_op_return_void: /* 0x0e */
601/* File: arm/op_return_void.S */
602 .extern MterpThreadFenceForConstructor
603 bl MterpThreadFenceForConstructor
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]604 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
605 mov r0, rSELF
606 ands lr, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
607 blne MterpSuspendCheck @ (self)
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]608 mov r0, #0
609 mov r1, #0
610 b MterpReturn
611
612/* ------------------------------ */
613 .balign 128
614.L_op_return: /* 0x0f */
615/* File: arm/op_return.S */
616 /*
617 * Return a 32-bit value.
618 *
619 * for: return, return-object
620 */
621 /* op vAA */
622 .extern MterpThreadFenceForConstructor
623 bl MterpThreadFenceForConstructor
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]624 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
625 mov r0, rSELF
626 ands lr, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
627 blne MterpSuspendCheck @ (self)
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]628 mov r2, rINST, lsr #8 @ r2<- AA
629 GET_VREG r0, r2 @ r0<- vAA
630 mov r1, #0
631 b MterpReturn
632
633/* ------------------------------ */
634 .balign 128
635.L_op_return_wide: /* 0x10 */
636/* File: arm/op_return_wide.S */
637 /*
638 * Return a 64-bit value.
639 */
640 /* return-wide vAA */
641 .extern MterpThreadFenceForConstructor
642 bl MterpThreadFenceForConstructor
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]643 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
644 mov r0, rSELF
645 ands lr, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
646 blne MterpSuspendCheck @ (self)
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]647 mov r2, rINST, lsr #8 @ r2<- AA
648 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
649 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1
650 b MterpReturn
651
652/* ------------------------------ */
653 .balign 128
654.L_op_return_object: /* 0x11 */
655/* File: arm/op_return_object.S */
656/* File: arm/op_return.S */
657 /*
658 * Return a 32-bit value.
659 *
660 * for: return, return-object
661 */
662 /* op vAA */
663 .extern MterpThreadFenceForConstructor
664 bl MterpThreadFenceForConstructor
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]665 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
666 mov r0, rSELF
667 ands lr, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
668 blne MterpSuspendCheck @ (self)
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]669 mov r2, rINST, lsr #8 @ r2<- AA
670 GET_VREG r0, r2 @ r0<- vAA
671 mov r1, #0
672 b MterpReturn
673
674
675/* ------------------------------ */
676 .balign 128
677.L_op_const_4: /* 0x12 */
678/* File: arm/op_const_4.S */
679 /* const/4 vA, #+B */
680 mov r1, rINST, lsl #16 @ r1<- Bxxx0000
681 ubfx r0, rINST, #8, #4 @ r0<- A
682 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
683 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended)
684 GET_INST_OPCODE ip @ ip<- opcode from rINST
685 SET_VREG r1, r0 @ fp[A]<- r1
686 GOTO_OPCODE ip @ execute next instruction
687
688/* ------------------------------ */
689 .balign 128
690.L_op_const_16: /* 0x13 */
691/* File: arm/op_const_16.S */
692 /* const/16 vAA, #+BBBB */
693 FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended
694 mov r3, rINST, lsr #8 @ r3<- AA
695 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
696 SET_VREG r0, r3 @ vAA<- r0
697 GET_INST_OPCODE ip @ extract opcode from rINST
698 GOTO_OPCODE ip @ jump to next instruction
699
700/* ------------------------------ */
701 .balign 128
702.L_op_const: /* 0x14 */
703/* File: arm/op_const.S */
704 /* const vAA, #+BBBBbbbb */
705 mov r3, rINST, lsr #8 @ r3<- AA
706 FETCH r0, 1 @ r0<- bbbb (low
707 FETCH r1, 2 @ r1<- BBBB (high
708 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST
709 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
710 GET_INST_OPCODE ip @ extract opcode from rINST
711 SET_VREG r0, r3 @ vAA<- r0
712 GOTO_OPCODE ip @ jump to next instruction
713
714/* ------------------------------ */
715 .balign 128
716.L_op_const_high16: /* 0x15 */
717/* File: arm/op_const_high16.S */
718 /* const/high16 vAA, #+BBBB0000 */
719 FETCH r0, 1 @ r0<- 0000BBBB (zero-extended
720 mov r3, rINST, lsr #8 @ r3<- AA
721 mov r0, r0, lsl #16 @ r0<- BBBB0000
722 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
723 SET_VREG r0, r3 @ vAA<- r0
724 GET_INST_OPCODE ip @ extract opcode from rINST
725 GOTO_OPCODE ip @ jump to next instruction
726
727/* ------------------------------ */
728 .balign 128
729.L_op_const_wide_16: /* 0x16 */
730/* File: arm/op_const_wide_16.S */
731 /* const-wide/16 vAA, #+BBBB */
732 FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended
733 mov r3, rINST, lsr #8 @ r3<- AA
734 mov r1, r0, asr #31 @ r1<- ssssssss
735 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
736 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
737 GET_INST_OPCODE ip @ extract opcode from rINST
738 stmia r3, {r0-r1} @ vAA<- r0/r1
739 GOTO_OPCODE ip @ jump to next instruction
740
741/* ------------------------------ */
742 .balign 128
743.L_op_const_wide_32: /* 0x17 */
744/* File: arm/op_const_wide_32.S */
745 /* const-wide/32 vAA, #+BBBBbbbb */
746 FETCH r0, 1 @ r0<- 0000bbbb (low)
747 mov r3, rINST, lsr #8 @ r3<- AA
748 FETCH_S r2, 2 @ r2<- ssssBBBB (high)
749 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST
750 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
751 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
752 mov r1, r0, asr #31 @ r1<- ssssssss
753 GET_INST_OPCODE ip @ extract opcode from rINST
754 stmia r3, {r0-r1} @ vAA<- r0/r1
755 GOTO_OPCODE ip @ jump to next instruction
756
757/* ------------------------------ */
758 .balign 128
759.L_op_const_wide: /* 0x18 */
760/* File: arm/op_const_wide.S */
761 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
762 FETCH r0, 1 @ r0<- bbbb (low)
763 FETCH r1, 2 @ r1<- BBBB (low middle)
764 FETCH r2, 3 @ r2<- hhhh (high middle)
765 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
766 FETCH r3, 4 @ r3<- HHHH (high)
767 mov r9, rINST, lsr #8 @ r9<- AA
768 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
769 FETCH_ADVANCE_INST 5 @ advance rPC, load rINST
770 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
771 GET_INST_OPCODE ip @ extract opcode from rINST
772 stmia r9, {r0-r1} @ vAA<- r0/r1
773 GOTO_OPCODE ip @ jump to next instruction
774
775/* ------------------------------ */
776 .balign 128
777.L_op_const_wide_high16: /* 0x19 */
778/* File: arm/op_const_wide_high16.S */
779 /* const-wide/high16 vAA, #+BBBB000000000000 */
780 FETCH r1, 1 @ r1<- 0000BBBB (zero-extended)
781 mov r3, rINST, lsr #8 @ r3<- AA
782 mov r0, #0 @ r0<- 00000000
783 mov r1, r1, lsl #16 @ r1<- BBBB0000
784 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
785 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
786 GET_INST_OPCODE ip @ extract opcode from rINST
787 stmia r3, {r0-r1} @ vAA<- r0/r1
788 GOTO_OPCODE ip @ jump to next instruction
789
790/* ------------------------------ */
791 .balign 128
792.L_op_const_string: /* 0x1a */
793/* File: arm/op_const_string.S */
794 /* const/string vAA, String@BBBB */
795 EXPORT_PC
796 FETCH r0, 1 @ r0<- BBBB
797 mov r1, rINST, lsr #8 @ r1<- AA
798 add r2, rFP, #OFF_FP_SHADOWFRAME
799 mov r3, rSELF
800 bl MterpConstString @ (index, tgt_reg, shadow_frame, self)
801 PREFETCH_INST 2 @ load rINST
802 cmp r0, #0 @ fail?
803 bne MterpPossibleException @ let reference interpreter deal with it.
804 ADVANCE 2 @ advance rPC
805 GET_INST_OPCODE ip @ extract opcode from rINST
806 GOTO_OPCODE ip @ jump to next instruction
807
808/* ------------------------------ */
809 .balign 128
810.L_op_const_string_jumbo: /* 0x1b */
811/* File: arm/op_const_string_jumbo.S */
812 /* const/string vAA, String@BBBBBBBB */
813 EXPORT_PC
814 FETCH r0, 1 @ r0<- bbbb (low
815 FETCH r2, 2 @ r2<- BBBB (high
816 mov r1, rINST, lsr #8 @ r1<- AA
817 orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb
818 add r2, rFP, #OFF_FP_SHADOWFRAME
819 mov r3, rSELF
820 bl MterpConstString @ (index, tgt_reg, shadow_frame, self)
821 PREFETCH_INST 3 @ advance rPC
822 cmp r0, #0 @ fail?
823 bne MterpPossibleException @ let reference interpreter deal with it.
824 ADVANCE 3 @ advance rPC
825 GET_INST_OPCODE ip @ extract opcode from rINST
826 GOTO_OPCODE ip @ jump to next instruction
827
828/* ------------------------------ */
829 .balign 128
830.L_op_const_class: /* 0x1c */
831/* File: arm/op_const_class.S */
832 /* const/class vAA, Class@BBBB */
833 EXPORT_PC
834 FETCH r0, 1 @ r0<- BBBB
835 mov r1, rINST, lsr #8 @ r1<- AA
836 add r2, rFP, #OFF_FP_SHADOWFRAME
837 mov r3, rSELF
838 bl MterpConstClass @ (index, tgt_reg, shadow_frame, self)
839 PREFETCH_INST 2
840 cmp r0, #0
841 bne MterpPossibleException
842 ADVANCE 2
843 GET_INST_OPCODE ip @ extract opcode from rINST
844 GOTO_OPCODE ip @ jump to next instruction
845
846/* ------------------------------ */
847 .balign 128
848.L_op_monitor_enter: /* 0x1d */
849/* File: arm/op_monitor_enter.S */
850 /*
851 * Synchronize on an object.
852 */
853 /* monitor-enter vAA */
854 EXPORT_PC
855 mov r2, rINST, lsr #8 @ r2<- AA
856 GET_VREG r0, r2 @ r0<- vAA (object)
857 mov r1, rSELF @ r1<- self
858 bl artLockObjectFromCode
859 cmp r0, #0
860 bne MterpException
861 FETCH_ADVANCE_INST 1
862 GET_INST_OPCODE ip @ extract opcode from rINST
863 GOTO_OPCODE ip @ jump to next instruction
864
865/* ------------------------------ */
866 .balign 128
867.L_op_monitor_exit: /* 0x1e */
868/* File: arm/op_monitor_exit.S */
869 /*
870 * Unlock an object.
871 *
872 * Exceptions that occur when unlocking a monitor need to appear as
873 * if they happened at the following instruction. See the Dalvik
874 * instruction spec.
875 */
876 /* monitor-exit vAA */
877 EXPORT_PC
878 mov r2, rINST, lsr #8 @ r2<- AA
879 GET_VREG r0, r2 @ r0<- vAA (object)
880 mov r1, rSELF @ r0<- self
881 bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj)
882 cmp r0, #0 @ failed?
883 bne MterpException
884 FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST
885 GET_INST_OPCODE ip @ extract opcode from rINST
886 GOTO_OPCODE ip @ jump to next instruction
887
888/* ------------------------------ */
889 .balign 128
890.L_op_check_cast: /* 0x1f */
891/* File: arm/op_check_cast.S */
892 /*
893 * Check to see if a cast from one class to another is allowed.
894 */
895 /* check-cast vAA, class@BBBB */
896 EXPORT_PC
897 FETCH r0, 1 @ r0<- BBBB
898 mov r1, rINST, lsr #8 @ r1<- AA
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]899 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]900 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method
901 mov r3, rSELF @ r3<- self
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]902 bl MterpCheckCast @ (index, &obj, method, self)
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]903 PREFETCH_INST 2
904 cmp r0, #0
905 bne MterpPossibleException
906 ADVANCE 2
907 GET_INST_OPCODE ip @ extract opcode from rINST
908 GOTO_OPCODE ip @ jump to next instruction
909
910/* ------------------------------ */
911 .balign 128
912.L_op_instance_of: /* 0x20 */
913/* File: arm/op_instance_of.S */
914 /*
915 * Check to see if an object reference is an instance of a class.
916 *
917 * Most common situation is a non-null object, being compared against
918 * an already-resolved class.
919 */
920 /* instance-of vA, vB, class@CCCC */
921 EXPORT_PC
922 FETCH r0, 1 @ r0<- CCCC
923 mov r1, rINST, lsr #12 @ r1<- B
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]924 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]925 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method
926 mov r3, rSELF @ r3<- self
927 mov r9, rINST, lsr #8 @ r9<- A+
928 and r9, r9, #15 @ r9<- A
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]929 bl MterpInstanceOf @ (index, &obj, method, self)
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]930 ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET]
931 PREFETCH_INST 2
932 cmp r1, #0 @ exception pending?
933 bne MterpException
934 ADVANCE 2 @ advance rPC
935 SET_VREG r0, r9 @ vA<- r0
936 GET_INST_OPCODE ip @ extract opcode from rINST
937 GOTO_OPCODE ip @ jump to next instruction
938
939/* ------------------------------ */
940 .balign 128
941.L_op_array_length: /* 0x21 */
942/* File: arm/op_array_length.S */
943 /*
944 * Return the length of an array.
945 */
946 mov r1, rINST, lsr #12 @ r1<- B
947 ubfx r2, rINST, #8, #4 @ r2<- A
948 GET_VREG r0, r1 @ r0<- vB (object ref)
949 cmp r0, #0 @ is object null?
950 beq common_errNullObject @ yup, fail
951 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
952 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length
953 GET_INST_OPCODE ip @ extract opcode from rINST
954 SET_VREG r3, r2 @ vB<- length
955 GOTO_OPCODE ip @ jump to next instruction
956
957/* ------------------------------ */
958 .balign 128
959.L_op_new_instance: /* 0x22 */
960/* File: arm/op_new_instance.S */
961 /*
962 * Create a new instance of a class.
963 */
964 /* new-instance vAA, class@BBBB */
965 EXPORT_PC
966 add r0, rFP, #OFF_FP_SHADOWFRAME
967 mov r1, rSELF
968 mov r2, rINST
969 bl MterpNewInstance @ (shadow_frame, self, inst_data)
970 cmp r0, #0
971 beq MterpPossibleException
972 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
973 GET_INST_OPCODE ip @ extract opcode from rINST
974 GOTO_OPCODE ip @ jump to next instruction
975
976/* ------------------------------ */
977 .balign 128
978.L_op_new_array: /* 0x23 */
979/* File: arm/op_new_array.S */
980 /*
981 * Allocate an array of objects, specified with the array class
982 * and a count.
983 *
984 * The verifier guarantees that this is an array class, so we don't
985 * check for it here.
986 */
987 /* new-array vA, vB, class@CCCC */
988 EXPORT_PC
989 add r0, rFP, #OFF_FP_SHADOWFRAME
990 mov r1, rPC
991 mov r2, rINST
992 mov r3, rSELF
993 bl MterpNewArray
994 cmp r0, #0
995 beq MterpPossibleException
996 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
997 GET_INST_OPCODE ip @ extract opcode from rINST
998 GOTO_OPCODE ip @ jump to next instruction
999
1000/* ------------------------------ */
1001 .balign 128
1002.L_op_filled_new_array: /* 0x24 */
1003/* File: arm/op_filled_new_array.S */
1004 /*
1005 * Create a new array with elements filled from registers.
1006 *
1007 * for: filled-new-array, filled-new-array/range
1008 */
1009 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1010 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1011 .extern MterpFilledNewArray
1012 EXPORT_PC
1013 add r0, rFP, #OFF_FP_SHADOWFRAME
1014 mov r1, rPC
1015 mov r2, rSELF
1016 bl MterpFilledNewArray
1017 cmp r0, #0
1018 beq MterpPossibleException
1019 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST
1020 GET_INST_OPCODE ip @ extract opcode from rINST
1021 GOTO_OPCODE ip @ jump to next instruction
1022
1023/* ------------------------------ */
1024 .balign 128
1025.L_op_filled_new_array_range: /* 0x25 */
1026/* File: arm/op_filled_new_array_range.S */
1027/* File: arm/op_filled_new_array.S */
1028 /*
1029 * Create a new array with elements filled from registers.
1030 *
1031 * for: filled-new-array, filled-new-array/range
1032 */
1033 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1034 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1035 .extern MterpFilledNewArrayRange
1036 EXPORT_PC
1037 add r0, rFP, #OFF_FP_SHADOWFRAME
1038 mov r1, rPC
1039 mov r2, rSELF
1040 bl MterpFilledNewArrayRange
1041 cmp r0, #0
1042 beq MterpPossibleException
1043 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST
1044 GET_INST_OPCODE ip @ extract opcode from rINST
1045 GOTO_OPCODE ip @ jump to next instruction
1046
1047
1048/* ------------------------------ */
1049 .balign 128
1050.L_op_fill_array_data: /* 0x26 */
1051/* File: arm/op_fill_array_data.S */
1052 /* fill-array-data vAA, +BBBBBBBB */
1053 EXPORT_PC
1054 FETCH r0, 1 @ r0<- bbbb (lo)
1055 FETCH r1, 2 @ r1<- BBBB (hi)
1056 mov r3, rINST, lsr #8 @ r3<- AA
1057 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
1058 GET_VREG r0, r3 @ r0<- vAA (array object)
1059 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
1060 bl MterpFillArrayData @ (obj, payload)
1061 cmp r0, #0 @ 0 means an exception is thrown
1062 beq MterpPossibleException @ exception?
1063 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST
1064 GET_INST_OPCODE ip @ extract opcode from rINST
1065 GOTO_OPCODE ip @ jump to next instruction
1066
1067/* ------------------------------ */
1068 .balign 128
1069.L_op_throw: /* 0x27 */
1070/* File: arm/op_throw.S */
1071 /*
1072 * Throw an exception object in the current thread.
1073 */
1074 /* throw vAA */
1075 EXPORT_PC
1076 mov r2, rINST, lsr #8 @ r2<- AA
1077 GET_VREG r1, r2 @ r1<- vAA (exception object)
1078 cmp r1, #0 @ null object?
1079 beq common_errNullObject @ yes, throw an NPE instead
1080 str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj
1081 b MterpException
1082
1083/* ------------------------------ */
1084 .balign 128
1085.L_op_goto: /* 0x28 */
1086/* File: arm/op_goto.S */
1087 /*
1088 * Unconditional branch, 8-bit offset.
1089 *
1090 * The branch distance is a signed code-unit offset, which we need to
1091 * double to get a byte offset.
1092 */
1093 /* goto +AA */
1094 /* tuning: use sbfx for 6t2+ targets */
1095#if MTERP_SUSPEND
1096 mov r0, rINST, lsl #16 @ r0<- AAxx0000
1097 movs r1, r0, asr #24 @ r1<- ssssssAA (sign-extended)
1098 add r2, r1, r1 @ r2<- byte offset, set flags
1099 @ If backwards branch refresh rIBASE
1100 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh handler base
1101 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1102 GET_INST_OPCODE ip @ extract opcode from rINST
1103 GOTO_OPCODE ip @ jump to next instruction
1104#else
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1105 mov r0, rINST, lsl #16 @ r0<- AAxx0000
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1106 movs rINST, r0, asr #24 @ rINST<- ssssssAA (sign-extended)
1107#if MTERP_PROFILE_BRANCHES
1108 mov r0, rSELF
1109 add r1, rFP, #OFF_FP_SHADOWFRAME
1110 mov r2, rINST
1111 bl MterpProfileBranch @ (self, shadow_frame, offset)
1112 cmp r0, #0
1113 bne MterpOnStackReplacement @ Note: offset must be in rINST
1114#endif
1115 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
1116 add r2, rINST, rINST @ r2<- byte offset, set flags
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1117 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1118 @ If backwards branch refresh rIBASE
1119 bmi MterpCheckSuspendAndContinue
1120 GET_INST_OPCODE ip @ extract opcode from rINST
1121 GOTO_OPCODE ip @ jump to next instruction
1122#endif
1123
1124/* ------------------------------ */
1125 .balign 128
1126.L_op_goto_16: /* 0x29 */
1127/* File: arm/op_goto_16.S */
1128 /*
1129 * Unconditional branch, 16-bit offset.
1130 *
1131 * The branch distance is a signed code-unit offset, which we need to
1132 * double to get a byte offset.
1133 */
1134 /* goto/16 +AAAA */
1135#if MTERP_SUSPEND
1136 FETCH_S r0, 1 @ r0<- ssssAAAA (sign-extended)
1137 adds r1, r0, r0 @ r1<- byte offset, flags set
1138 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1139 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh handler base
1140 GET_INST_OPCODE ip @ extract opcode from rINST
1141 GOTO_OPCODE ip @ jump to next instruction
1142#else
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1143 FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended)
1144#if MTERP_PROFILE_BRANCHES
1145 mov r0, rINST
1146 add r1, rFP, #OFF_FP_SHADOWFRAME
1147 mov r2, rINST
1148 bl MterpOnStackReplacement @ (self, shadow_frame, offset)
1149 cmp r0, #0
1150 bne MterpOnStackReplacement @ Note: offset must be in rINST
1151#endif
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1152 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1153 adds r1, rINST, rINST @ r1<- byte offset, flags set
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1154 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1155 bmi MterpCheckSuspendAndContinue
1156 GET_INST_OPCODE ip @ extract opcode from rINST
1157 GOTO_OPCODE ip @ jump to next instruction
1158#endif
1159
1160/* ------------------------------ */
1161 .balign 128
1162.L_op_goto_32: /* 0x2a */
1163/* File: arm/op_goto_32.S */
1164 /*
1165 * Unconditional branch, 32-bit offset.
1166 *
1167 * The branch distance is a signed code-unit offset, which we need to
1168 * double to get a byte offset.
1169 *
1170 * Unlike most opcodes, this one is allowed to branch to itself, so
1171 * our "backward branch" test must be "<=0" instead of "<0". Because
1172 * we need the V bit set, we'll use an adds to convert from Dalvik
1173 * offset to byte offset.
1174 */
1175 /* goto/32 +AAAAAAAA */
1176#if MTERP_SUSPEND
1177 FETCH r0, 1 @ r0<- aaaa (lo)
1178 FETCH r1, 2 @ r1<- AAAA (hi)
1179 orr r0, r0, r1, lsl #16 @ r0<- AAAAaaaa
1180 adds r1, r0, r0 @ r1<- byte offset
1181 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1182 ldrle rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh handler base
1183 GET_INST_OPCODE ip @ extract opcode from rINST
1184 GOTO_OPCODE ip @ jump to next instruction
1185#else
1186 FETCH r0, 1 @ r0<- aaaa (lo)
1187 FETCH r1, 2 @ r1<- AAAA (hi)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1188 orr rINST, r0, r1, lsl #16 @ rINST<- AAAAaaaa
1189#if MTERP_PROFILE_BRANCHES
1190 mov r0, rSELF
1191 add r1, rFP, #OFF_FP_SHADOWFRAME
1192 mov r2, rINST
1193 bl MterpOnStackReplacement @ (self, shadow_frame, offset)
1194 cmp r0, #0
1195 bne MterpOnStackReplacement @ Note: offset must be in rINST
1196#endif
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1197 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1198 adds r1, rINST, rINST @ r1<- byte offset
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1199 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1200 ble MterpCheckSuspendAndContinue
1201 GET_INST_OPCODE ip @ extract opcode from rINST
1202 GOTO_OPCODE ip @ jump to next instruction
1203#endif
1204
1205/* ------------------------------ */
1206 .balign 128
1207.L_op_packed_switch: /* 0x2b */
1208/* File: arm/op_packed_switch.S */
1209 /*
1210 * Handle a packed-switch or sparse-switch instruction. In both cases
1211 * we decode it and hand it off to a helper function.
1212 *
1213 * We don't really expect backward branches in a switch statement, but
1214 * they're perfectly legal, so we check for them here.
1215 *
1216 * for: packed-switch, sparse-switch
1217 */
1218 /* op vAA, +BBBB */
1219#if MTERP_SUSPEND
1220 FETCH r0, 1 @ r0<- bbbb (lo)
1221 FETCH r1, 2 @ r1<- BBBB (hi)
1222 mov r3, rINST, lsr #8 @ r3<- AA
1223 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1224 GET_VREG r1, r3 @ r1<- vAA
1225 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1226 bl MterpDoPackedSwitch @ r0<- code-unit branch offset
1227 adds r1, r0, r0 @ r1<- byte offset; clear V
1228 ldrle rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh handler base
1229 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1230 GET_INST_OPCODE ip @ extract opcode from rINST
1231 GOTO_OPCODE ip @ jump to next instruction
1232#else
1233 FETCH r0, 1 @ r0<- bbbb (lo)
1234 FETCH r1, 2 @ r1<- BBBB (hi)
1235 mov r3, rINST, lsr #8 @ r3<- AA
1236 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1237 GET_VREG r1, r3 @ r1<- vAA
1238 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1239 bl MterpDoPackedSwitch @ r0<- code-unit branch offset
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1240 mov rINST, r0
1241#if MTERP_PROFILE_BRANCHES
1242 mov r0, rSELF
1243 add r1, rFP, #OFF_FP_SHADOWFRAME
1244 mov r2, rINST
1245 bl MterpProfileBranch @ (self, shadow_frame, offset)
1246 cmp r0, #0
1247 bne MterpOnStackReplacement @ Note: offset must be in rINST
1248#endif
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1249 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1250 adds r1, rINST, rINST @ r1<- byte offset; clear V
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1251 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1252 ble MterpCheckSuspendAndContinue
1253 GET_INST_OPCODE ip @ extract opcode from rINST
1254 GOTO_OPCODE ip @ jump to next instruction
1255#endif
1256
1257/* ------------------------------ */
1258 .balign 128
1259.L_op_sparse_switch: /* 0x2c */
1260/* File: arm/op_sparse_switch.S */
1261/* File: arm/op_packed_switch.S */
1262 /*
1263 * Handle a packed-switch or sparse-switch instruction. In both cases
1264 * we decode it and hand it off to a helper function.
1265 *
1266 * We don't really expect backward branches in a switch statement, but
1267 * they're perfectly legal, so we check for them here.
1268 *
1269 * for: packed-switch, sparse-switch
1270 */
1271 /* op vAA, +BBBB */
1272#if MTERP_SUSPEND
1273 FETCH r0, 1 @ r0<- bbbb (lo)
1274 FETCH r1, 2 @ r1<- BBBB (hi)
1275 mov r3, rINST, lsr #8 @ r3<- AA
1276 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1277 GET_VREG r1, r3 @ r1<- vAA
1278 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1279 bl MterpDoSparseSwitch @ r0<- code-unit branch offset
1280 adds r1, r0, r0 @ r1<- byte offset; clear V
1281 ldrle rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh handler base
1282 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1283 GET_INST_OPCODE ip @ extract opcode from rINST
1284 GOTO_OPCODE ip @ jump to next instruction
1285#else
1286 FETCH r0, 1 @ r0<- bbbb (lo)
1287 FETCH r1, 2 @ r1<- BBBB (hi)
1288 mov r3, rINST, lsr #8 @ r3<- AA
1289 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1290 GET_VREG r1, r3 @ r1<- vAA
1291 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1292 bl MterpDoSparseSwitch @ r0<- code-unit branch offset
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1293 mov rINST, r0
1294#if MTERP_PROFILE_BRANCHES
1295 mov r0, rSELF
1296 add r1, rFP, #OFF_FP_SHADOWFRAME
1297 mov r2, rINST
1298 bl MterpProfileBranch @ (self, shadow_frame, offset)
1299 cmp r0, #0
1300 bne MterpOnStackReplacement @ Note: offset must be in rINST
1301#endif
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1302 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1303 adds r1, rINST, rINST @ r1<- byte offset; clear V
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1304 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1305 ble MterpCheckSuspendAndContinue
1306 GET_INST_OPCODE ip @ extract opcode from rINST
1307 GOTO_OPCODE ip @ jump to next instruction
1308#endif
1309
1310
1311/* ------------------------------ */
1312 .balign 128
1313.L_op_cmpl_float: /* 0x2d */
1314/* File: arm/op_cmpl_float.S */
1315 /*
1316 * Compare two floating-point values. Puts 0, 1, or -1 into the
1317 * destination register based on the results of the comparison.
1318 *
1319 * int compare(x, y) {
1320 * if (x == y) {
1321 * return 0;
1322 * } else if (x > y) {
1323 * return 1;
1324 * } else if (x < y) {
1325 * return -1;
1326 * } else {
1327 * return -1;
1328 * }
1329 * }
1330 */
1331 /* op vAA, vBB, vCC */
1332 FETCH r0, 1 @ r0<- CCBB
1333 mov r9, rINST, lsr #8 @ r9<- AA
1334 and r2, r0, #255 @ r2<- BB
1335 mov r3, r0, lsr #8 @ r3<- CC
1336 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
1337 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
1338 flds s0, [r2] @ s0<- vBB
1339 flds s1, [r3] @ s1<- vCC
1340 fcmpes s0, s1 @ compare (vBB, vCC)
1341 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
1342 mvn r0, #0 @ r0<- -1 (default)
1343 GET_INST_OPCODE ip @ extract opcode from rINST
1344 fmstat @ export status flags
1345 movgt r0, #1 @ (greater than) r1<- 1
1346 moveq r0, #0 @ (equal) r1<- 0
1347 SET_VREG r0, r9 @ vAA<- r0
1348 GOTO_OPCODE ip @ jump to next instruction
1349
1350/* ------------------------------ */
1351 .balign 128
1352.L_op_cmpg_float: /* 0x2e */
1353/* File: arm/op_cmpg_float.S */
1354 /*
1355 * Compare two floating-point values. Puts 0, 1, or -1 into the
1356 * destination register based on the results of the comparison.
1357 *
1358 * int compare(x, y) {
1359 * if (x == y) {
1360 * return 0;
1361 * } else if (x < y) {
1362 * return -1;
1363 * } else if (x > y) {
1364 * return 1;
1365 * } else {
1366 * return 1;
1367 * }
1368 * }
1369 */
1370 /* op vAA, vBB, vCC */
1371 FETCH r0, 1 @ r0<- CCBB
1372 mov r9, rINST, lsr #8 @ r9<- AA
1373 and r2, r0, #255 @ r2<- BB
1374 mov r3, r0, lsr #8 @ r3<- CC
1375 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
1376 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
1377 flds s0, [r2] @ s0<- vBB
1378 flds s1, [r3] @ s1<- vCC
1379 fcmpes s0, s1 @ compare (vBB, vCC)
1380 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
1381 mov r0, #1 @ r0<- 1 (default)
1382 GET_INST_OPCODE ip @ extract opcode from rINST
1383 fmstat @ export status flags
1384 mvnmi r0, #0 @ (less than) r1<- -1
1385 moveq r0, #0 @ (equal) r1<- 0
1386 SET_VREG r0, r9 @ vAA<- r0
1387 GOTO_OPCODE ip @ jump to next instruction
1388
1389/* ------------------------------ */
1390 .balign 128
1391.L_op_cmpl_double: /* 0x2f */
1392/* File: arm/op_cmpl_double.S */
1393 /*
1394 * Compare two floating-point values. Puts 0, 1, or -1 into the
1395 * destination register based on the results of the comparison.
1396 *
1397 * int compare(x, y) {
1398 * if (x == y) {
1399 * return 0;
1400 * } else if (x > y) {
1401 * return 1;
1402 * } else if (x < y) {
1403 * return -1;
1404 * } else {
1405 * return -1;
1406 * }
1407 * }
1408 */
1409 /* op vAA, vBB, vCC */
1410 FETCH r0, 1 @ r0<- CCBB
1411 mov r9, rINST, lsr #8 @ r9<- AA
1412 and r2, r0, #255 @ r2<- BB
1413 mov r3, r0, lsr #8 @ r3<- CC
1414 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
1415 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
1416 fldd d0, [r2] @ d0<- vBB
1417 fldd d1, [r3] @ d1<- vCC
1418 fcmped d0, d1 @ compare (vBB, vCC)
1419 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
1420 mvn r0, #0 @ r0<- -1 (default)
1421 GET_INST_OPCODE ip @ extract opcode from rINST
1422 fmstat @ export status flags
1423 movgt r0, #1 @ (greater than) r1<- 1
1424 moveq r0, #0 @ (equal) r1<- 0
1425 SET_VREG r0, r9 @ vAA<- r0
1426 GOTO_OPCODE ip @ jump to next instruction
1427
1428/* ------------------------------ */
1429 .balign 128
1430.L_op_cmpg_double: /* 0x30 */
1431/* File: arm/op_cmpg_double.S */
1432 /*
1433 * Compare two floating-point values. Puts 0, 1, or -1 into the
1434 * destination register based on the results of the comparison.
1435 *
1436 * int compare(x, y) {
1437 * if (x == y) {
1438 * return 0;
1439 * } else if (x < y) {
1440 * return -1;
1441 * } else if (x > y) {
1442 * return 1;
1443 * } else {
1444 * return 1;
1445 * }
1446 * }
1447 */
1448 /* op vAA, vBB, vCC */
1449 FETCH r0, 1 @ r0<- CCBB
1450 mov r9, rINST, lsr #8 @ r9<- AA
1451 and r2, r0, #255 @ r2<- BB
1452 mov r3, r0, lsr #8 @ r3<- CC
1453 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
1454 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
1455 fldd d0, [r2] @ d0<- vBB
1456 fldd d1, [r3] @ d1<- vCC
1457 fcmped d0, d1 @ compare (vBB, vCC)
1458 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
1459 mov r0, #1 @ r0<- 1 (default)
1460 GET_INST_OPCODE ip @ extract opcode from rINST
1461 fmstat @ export status flags
1462 mvnmi r0, #0 @ (less than) r1<- -1
1463 moveq r0, #0 @ (equal) r1<- 0
1464 SET_VREG r0, r9 @ vAA<- r0
1465 GOTO_OPCODE ip @ jump to next instruction
1466
1467/* ------------------------------ */
1468 .balign 128
1469.L_op_cmp_long: /* 0x31 */
1470/* File: arm/op_cmp_long.S */
1471 /*
1472 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
1473 * register based on the results of the comparison.
1474 *
1475 * We load the full values with LDM, but in practice many values could
1476 * be resolved by only looking at the high word. This could be made
1477 * faster or slower by splitting the LDM into a pair of LDRs.
1478 *
1479 * If we just wanted to set condition flags, we could do this:
1480 * subs ip, r0, r2
1481 * sbcs ip, r1, r3
1482 * subeqs ip, r0, r2
1483 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific
1484 * integer value, which we can do with 2 conditional mov/mvn instructions
1485 * (set 1, set -1; if they're equal we already have 0 in ip), giving
1486 * us a constant 5-cycle path plus a branch at the end to the
1487 * instruction epilogue code. The multi-compare approach below needs
1488 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch
1489 * in the worst case (the 64-bit values are equal).
1490 */
1491 /* cmp-long vAA, vBB, vCC */
1492 FETCH r0, 1 @ r0<- CCBB
1493 mov r9, rINST, lsr #8 @ r9<- AA
1494 and r2, r0, #255 @ r2<- BB
1495 mov r3, r0, lsr #8 @ r3<- CC
1496 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
1497 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
1498 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
1499 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
1500 cmp r1, r3 @ compare (vBB+1, vCC+1)
1501 blt .Lop_cmp_long_less @ signed compare on high part
1502 bgt .Lop_cmp_long_greater
1503 subs r1, r0, r2 @ r1<- r0 - r2
1504 bhi .Lop_cmp_long_greater @ unsigned compare on low part
1505 bne .Lop_cmp_long_less
1506 b .Lop_cmp_long_finish @ equal; r1 already holds 0
1507
1508/* ------------------------------ */
1509 .balign 128
1510.L_op_if_eq: /* 0x32 */
1511/* File: arm/op_if_eq.S */
1512/* File: arm/bincmp.S */
1513 /*
1514 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1515 * fragment that specifies the *reverse* comparison to perform, e.g.
1516 * for "if-le" you would use "gt".
1517 *
1518 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1519 */
1520 /* if-cmp vA, vB, +CCCC */
1521#if MTERP_SUSPEND
1522 mov r1, rINST, lsr #12 @ r1<- B
1523 ubfx r0, rINST, #8, #4 @ r0<- A
1524 GET_VREG r3, r1 @ r3<- vB
1525 GET_VREG r2, r0 @ r2<- vA
1526 FETCH_S r1, 1 @ r1<- branch offset, in code units
1527 cmp r2, r3 @ compare (vA, vB)
1528 movne r1, #2 @ r1<- BYTE branch dist for not-taken
1529 adds r2, r1, r1 @ convert to bytes, check sign
1530 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1531 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh rIBASE
1532 GET_INST_OPCODE ip @ extract opcode from rINST
1533 GOTO_OPCODE ip @ jump to next instruction
1534#else
1535 mov r1, rINST, lsr #12 @ r1<- B
1536 ubfx r0, rINST, #8, #4 @ r0<- A
1537 GET_VREG r3, r1 @ r3<- vB
1538 GET_VREG r2, r0 @ r2<- vA
1539 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1540 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1541 cmp r2, r3 @ compare (vA, vB)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1542 movne rINST, #2 @ rINST<- BYTE branch dist for not-taken
1543#if MTERP_PROFILE_BRANCHES
1544 mov r0, rSELF
1545 add r1, rFP, #OFF_FP_SHADOWFRAME
1546 mov r2, rINST
1547 bl MterpProfileBranch @ (self, shadow_frame, offset)
1548 cmp r0, #0
1549 bne MterpOnStackReplacement @ Note: offset must be in rINST
1550#endif
1551 adds r2, rINST, rINST @ convert to bytes, check sign
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1552 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1553 bmi MterpCheckSuspendAndContinue
1554 GET_INST_OPCODE ip @ extract opcode from rINST
1555 GOTO_OPCODE ip @ jump to next instruction
1556#endif
1557
1558
1559/* ------------------------------ */
1560 .balign 128
1561.L_op_if_ne: /* 0x33 */
1562/* File: arm/op_if_ne.S */
1563/* File: arm/bincmp.S */
1564 /*
1565 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1566 * fragment that specifies the *reverse* comparison to perform, e.g.
1567 * for "if-le" you would use "gt".
1568 *
1569 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1570 */
1571 /* if-cmp vA, vB, +CCCC */
1572#if MTERP_SUSPEND
1573 mov r1, rINST, lsr #12 @ r1<- B
1574 ubfx r0, rINST, #8, #4 @ r0<- A
1575 GET_VREG r3, r1 @ r3<- vB
1576 GET_VREG r2, r0 @ r2<- vA
1577 FETCH_S r1, 1 @ r1<- branch offset, in code units
1578 cmp r2, r3 @ compare (vA, vB)
1579 moveq r1, #2 @ r1<- BYTE branch dist for not-taken
1580 adds r2, r1, r1 @ convert to bytes, check sign
1581 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1582 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh rIBASE
1583 GET_INST_OPCODE ip @ extract opcode from rINST
1584 GOTO_OPCODE ip @ jump to next instruction
1585#else
1586 mov r1, rINST, lsr #12 @ r1<- B
1587 ubfx r0, rINST, #8, #4 @ r0<- A
1588 GET_VREG r3, r1 @ r3<- vB
1589 GET_VREG r2, r0 @ r2<- vA
1590 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1591 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1592 cmp r2, r3 @ compare (vA, vB)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1593 moveq rINST, #2 @ rINST<- BYTE branch dist for not-taken
1594#if MTERP_PROFILE_BRANCHES
1595 mov r0, rSELF
1596 add r1, rFP, #OFF_FP_SHADOWFRAME
1597 mov r2, rINST
1598 bl MterpProfileBranch @ (self, shadow_frame, offset)
1599 cmp r0, #0
1600 bne MterpOnStackReplacement @ Note: offset must be in rINST
1601#endif
1602 adds r2, rINST, rINST @ convert to bytes, check sign
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1603 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1604 bmi MterpCheckSuspendAndContinue
1605 GET_INST_OPCODE ip @ extract opcode from rINST
1606 GOTO_OPCODE ip @ jump to next instruction
1607#endif
1608
1609
1610/* ------------------------------ */
1611 .balign 128
1612.L_op_if_lt: /* 0x34 */
1613/* File: arm/op_if_lt.S */
1614/* File: arm/bincmp.S */
1615 /*
1616 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1617 * fragment that specifies the *reverse* comparison to perform, e.g.
1618 * for "if-le" you would use "gt".
1619 *
1620 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1621 */
1622 /* if-cmp vA, vB, +CCCC */
1623#if MTERP_SUSPEND
1624 mov r1, rINST, lsr #12 @ r1<- B
1625 ubfx r0, rINST, #8, #4 @ r0<- A
1626 GET_VREG r3, r1 @ r3<- vB
1627 GET_VREG r2, r0 @ r2<- vA
1628 FETCH_S r1, 1 @ r1<- branch offset, in code units
1629 cmp r2, r3 @ compare (vA, vB)
1630 movge r1, #2 @ r1<- BYTE branch dist for not-taken
1631 adds r2, r1, r1 @ convert to bytes, check sign
1632 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1633 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh rIBASE
1634 GET_INST_OPCODE ip @ extract opcode from rINST
1635 GOTO_OPCODE ip @ jump to next instruction
1636#else
1637 mov r1, rINST, lsr #12 @ r1<- B
1638 ubfx r0, rINST, #8, #4 @ r0<- A
1639 GET_VREG r3, r1 @ r3<- vB
1640 GET_VREG r2, r0 @ r2<- vA
1641 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1642 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1643 cmp r2, r3 @ compare (vA, vB)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1644 movge rINST, #2 @ rINST<- BYTE branch dist for not-taken
1645#if MTERP_PROFILE_BRANCHES
1646 mov r0, rSELF
1647 add r1, rFP, #OFF_FP_SHADOWFRAME
1648 mov r2, rINST
1649 bl MterpProfileBranch @ (self, shadow_frame, offset)
1650 cmp r0, #0
1651 bne MterpOnStackReplacement @ Note: offset must be in rINST
1652#endif
1653 adds r2, rINST, rINST @ convert to bytes, check sign
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1654 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1655 bmi MterpCheckSuspendAndContinue
1656 GET_INST_OPCODE ip @ extract opcode from rINST
1657 GOTO_OPCODE ip @ jump to next instruction
1658#endif
1659
1660
1661/* ------------------------------ */
1662 .balign 128
1663.L_op_if_ge: /* 0x35 */
1664/* File: arm/op_if_ge.S */
1665/* File: arm/bincmp.S */
1666 /*
1667 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1668 * fragment that specifies the *reverse* comparison to perform, e.g.
1669 * for "if-le" you would use "gt".
1670 *
1671 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1672 */
1673 /* if-cmp vA, vB, +CCCC */
1674#if MTERP_SUSPEND
1675 mov r1, rINST, lsr #12 @ r1<- B
1676 ubfx r0, rINST, #8, #4 @ r0<- A
1677 GET_VREG r3, r1 @ r3<- vB
1678 GET_VREG r2, r0 @ r2<- vA
1679 FETCH_S r1, 1 @ r1<- branch offset, in code units
1680 cmp r2, r3 @ compare (vA, vB)
1681 movlt r1, #2 @ r1<- BYTE branch dist for not-taken
1682 adds r2, r1, r1 @ convert to bytes, check sign
1683 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1684 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh rIBASE
1685 GET_INST_OPCODE ip @ extract opcode from rINST
1686 GOTO_OPCODE ip @ jump to next instruction
1687#else
1688 mov r1, rINST, lsr #12 @ r1<- B
1689 ubfx r0, rINST, #8, #4 @ r0<- A
1690 GET_VREG r3, r1 @ r3<- vB
1691 GET_VREG r2, r0 @ r2<- vA
1692 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1693 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1694 cmp r2, r3 @ compare (vA, vB)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1695 movlt rINST, #2 @ rINST<- BYTE branch dist for not-taken
1696#if MTERP_PROFILE_BRANCHES
1697 mov r0, rSELF
1698 add r1, rFP, #OFF_FP_SHADOWFRAME
1699 mov r2, rINST
1700 bl MterpProfileBranch @ (self, shadow_frame, offset)
1701 cmp r0, #0
1702 bne MterpOnStackReplacement @ Note: offset must be in rINST
1703#endif
1704 adds r2, rINST, rINST @ convert to bytes, check sign
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1705 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1706 bmi MterpCheckSuspendAndContinue
1707 GET_INST_OPCODE ip @ extract opcode from rINST
1708 GOTO_OPCODE ip @ jump to next instruction
1709#endif
1710
1711
1712/* ------------------------------ */
1713 .balign 128
1714.L_op_if_gt: /* 0x36 */
1715/* File: arm/op_if_gt.S */
1716/* File: arm/bincmp.S */
1717 /*
1718 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1719 * fragment that specifies the *reverse* comparison to perform, e.g.
1720 * for "if-le" you would use "gt".
1721 *
1722 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1723 */
1724 /* if-cmp vA, vB, +CCCC */
1725#if MTERP_SUSPEND
1726 mov r1, rINST, lsr #12 @ r1<- B
1727 ubfx r0, rINST, #8, #4 @ r0<- A
1728 GET_VREG r3, r1 @ r3<- vB
1729 GET_VREG r2, r0 @ r2<- vA
1730 FETCH_S r1, 1 @ r1<- branch offset, in code units
1731 cmp r2, r3 @ compare (vA, vB)
1732 movle r1, #2 @ r1<- BYTE branch dist for not-taken
1733 adds r2, r1, r1 @ convert to bytes, check sign
1734 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1735 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh rIBASE
1736 GET_INST_OPCODE ip @ extract opcode from rINST
1737 GOTO_OPCODE ip @ jump to next instruction
1738#else
1739 mov r1, rINST, lsr #12 @ r1<- B
1740 ubfx r0, rINST, #8, #4 @ r0<- A
1741 GET_VREG r3, r1 @ r3<- vB
1742 GET_VREG r2, r0 @ r2<- vA
1743 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1744 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1745 cmp r2, r3 @ compare (vA, vB)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1746 movle rINST, #2 @ rINST<- BYTE branch dist for not-taken
1747#if MTERP_PROFILE_BRANCHES
1748 mov r0, rSELF
1749 add r1, rFP, #OFF_FP_SHADOWFRAME
1750 mov r2, rINST
1751 bl MterpProfileBranch @ (self, shadow_frame, offset)
1752 cmp r0, #0
1753 bne MterpOnStackReplacement @ Note: offset must be in rINST
1754#endif
1755 adds r2, rINST, rINST @ convert to bytes, check sign
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1756 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1757 bmi MterpCheckSuspendAndContinue
1758 GET_INST_OPCODE ip @ extract opcode from rINST
1759 GOTO_OPCODE ip @ jump to next instruction
1760#endif
1761
1762
1763/* ------------------------------ */
1764 .balign 128
1765.L_op_if_le: /* 0x37 */
1766/* File: arm/op_if_le.S */
1767/* File: arm/bincmp.S */
1768 /*
1769 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1770 * fragment that specifies the *reverse* comparison to perform, e.g.
1771 * for "if-le" you would use "gt".
1772 *
1773 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1774 */
1775 /* if-cmp vA, vB, +CCCC */
1776#if MTERP_SUSPEND
1777 mov r1, rINST, lsr #12 @ r1<- B
1778 ubfx r0, rINST, #8, #4 @ r0<- A
1779 GET_VREG r3, r1 @ r3<- vB
1780 GET_VREG r2, r0 @ r2<- vA
1781 FETCH_S r1, 1 @ r1<- branch offset, in code units
1782 cmp r2, r3 @ compare (vA, vB)
1783 movgt r1, #2 @ r1<- BYTE branch dist for not-taken
1784 adds r2, r1, r1 @ convert to bytes, check sign
1785 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1786 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh rIBASE
1787 GET_INST_OPCODE ip @ extract opcode from rINST
1788 GOTO_OPCODE ip @ jump to next instruction
1789#else
1790 mov r1, rINST, lsr #12 @ r1<- B
1791 ubfx r0, rINST, #8, #4 @ r0<- A
1792 GET_VREG r3, r1 @ r3<- vB
1793 GET_VREG r2, r0 @ r2<- vA
1794 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1795 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1796 cmp r2, r3 @ compare (vA, vB)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1797 movgt rINST, #2 @ rINST<- BYTE branch dist for not-taken
1798#if MTERP_PROFILE_BRANCHES
1799 mov r0, rSELF
1800 add r1, rFP, #OFF_FP_SHADOWFRAME
1801 mov r2, rINST
1802 bl MterpProfileBranch @ (self, shadow_frame, offset)
1803 cmp r0, #0
1804 bne MterpOnStackReplacement @ Note: offset must be in rINST
1805#endif
1806 adds r2, rINST, rINST @ convert to bytes, check sign
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1807 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST
1808 bmi MterpCheckSuspendAndContinue
1809 GET_INST_OPCODE ip @ extract opcode from rINST
1810 GOTO_OPCODE ip @ jump to next instruction
1811#endif
1812
1813
1814/* ------------------------------ */
1815 .balign 128
1816.L_op_if_eqz: /* 0x38 */
1817/* File: arm/op_if_eqz.S */
1818/* File: arm/zcmp.S */
1819 /*
1820 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1821 * fragment that specifies the *reverse* comparison to perform, e.g.
1822 * for "if-le" you would use "gt".
1823 *
1824 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1825 */
1826 /* if-cmp vAA, +BBBB */
1827#if MTERP_SUSPEND
1828 mov r0, rINST, lsr #8 @ r0<- AA
1829 GET_VREG r2, r0 @ r2<- vAA
1830 FETCH_S r1, 1 @ r1<- branch offset, in code units
1831 cmp r2, #0 @ compare (vA, 0)
1832 movne r1, #2 @ r1<- inst branch dist for not-taken
1833 adds r1, r1, r1 @ convert to bytes & set flags
1834 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1835 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh table base
1836 GET_INST_OPCODE ip @ extract opcode from rINST
1837 GOTO_OPCODE ip @ jump to next instruction
1838#else
1839 mov r0, rINST, lsr #8 @ r0<- AA
1840 GET_VREG r2, r0 @ r2<- vAA
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1841 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1842 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
1843 cmp r2, #0 @ compare (vA, 0)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1844 movne rINST, #2 @ rINST<- inst branch dist for not-taken
1845#if MTERP_PROFILE_BRANCHES
1846 mov r0, rSELF
1847 add r1, rFP, #OFF_FP_SHADOWFRAME
1848 mov r2, rINST
1849 bl MterpProfileBranch @ (self, shadow_frame, offset)
1850 cmp r0, #0
1851 bne MterpOnStackReplacement @ Note: offset must be in rINST
1852#endif
1853 adds r1, rINST, rINST @ convert to bytes & set flags
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1854 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1855 bmi MterpCheckSuspendAndContinue
1856 GET_INST_OPCODE ip @ extract opcode from rINST
1857 GOTO_OPCODE ip @ jump to next instruction
1858#endif
1859
1860
1861/* ------------------------------ */
1862 .balign 128
1863.L_op_if_nez: /* 0x39 */
1864/* File: arm/op_if_nez.S */
1865/* File: arm/zcmp.S */
1866 /*
1867 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1868 * fragment that specifies the *reverse* comparison to perform, e.g.
1869 * for "if-le" you would use "gt".
1870 *
1871 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1872 */
1873 /* if-cmp vAA, +BBBB */
1874#if MTERP_SUSPEND
1875 mov r0, rINST, lsr #8 @ r0<- AA
1876 GET_VREG r2, r0 @ r2<- vAA
1877 FETCH_S r1, 1 @ r1<- branch offset, in code units
1878 cmp r2, #0 @ compare (vA, 0)
1879 moveq r1, #2 @ r1<- inst branch dist for not-taken
1880 adds r1, r1, r1 @ convert to bytes & set flags
1881 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1882 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh table base
1883 GET_INST_OPCODE ip @ extract opcode from rINST
1884 GOTO_OPCODE ip @ jump to next instruction
1885#else
1886 mov r0, rINST, lsr #8 @ r0<- AA
1887 GET_VREG r2, r0 @ r2<- vAA
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1888 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1889 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
1890 cmp r2, #0 @ compare (vA, 0)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1891 moveq rINST, #2 @ rINST<- inst branch dist for not-taken
1892#if MTERP_PROFILE_BRANCHES
1893 mov r0, rSELF
1894 add r1, rFP, #OFF_FP_SHADOWFRAME
1895 mov r2, rINST
1896 bl MterpProfileBranch @ (self, shadow_frame, offset)
1897 cmp r0, #0
1898 bne MterpOnStackReplacement @ Note: offset must be in rINST
1899#endif
1900 adds r1, rINST, rINST @ convert to bytes & set flags
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1901 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1902 bmi MterpCheckSuspendAndContinue
1903 GET_INST_OPCODE ip @ extract opcode from rINST
1904 GOTO_OPCODE ip @ jump to next instruction
1905#endif
1906
1907
1908/* ------------------------------ */
1909 .balign 128
1910.L_op_if_ltz: /* 0x3a */
1911/* File: arm/op_if_ltz.S */
1912/* File: arm/zcmp.S */
1913 /*
1914 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1915 * fragment that specifies the *reverse* comparison to perform, e.g.
1916 * for "if-le" you would use "gt".
1917 *
1918 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1919 */
1920 /* if-cmp vAA, +BBBB */
1921#if MTERP_SUSPEND
1922 mov r0, rINST, lsr #8 @ r0<- AA
1923 GET_VREG r2, r0 @ r2<- vAA
1924 FETCH_S r1, 1 @ r1<- branch offset, in code units
1925 cmp r2, #0 @ compare (vA, 0)
1926 movge r1, #2 @ r1<- inst branch dist for not-taken
1927 adds r1, r1, r1 @ convert to bytes & set flags
1928 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1929 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh table base
1930 GET_INST_OPCODE ip @ extract opcode from rINST
1931 GOTO_OPCODE ip @ jump to next instruction
1932#else
1933 mov r0, rINST, lsr #8 @ r0<- AA
1934 GET_VREG r2, r0 @ r2<- vAA
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1935 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1936 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
1937 cmp r2, #0 @ compare (vA, 0)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1938 movge rINST, #2 @ rINST<- inst branch dist for not-taken
1939#if MTERP_PROFILE_BRANCHES
1940 mov r0, rSELF
1941 add r1, rFP, #OFF_FP_SHADOWFRAME
1942 mov r2, rINST
1943 bl MterpProfileBranch @ (self, shadow_frame, offset)
1944 cmp r0, #0
1945 bne MterpOnStackReplacement @ Note: offset must be in rINST
1946#endif
1947 adds r1, rINST, rINST @ convert to bytes & set flags
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1948 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1949 bmi MterpCheckSuspendAndContinue
1950 GET_INST_OPCODE ip @ extract opcode from rINST
1951 GOTO_OPCODE ip @ jump to next instruction
1952#endif
1953
1954
1955/* ------------------------------ */
1956 .balign 128
1957.L_op_if_gez: /* 0x3b */
1958/* File: arm/op_if_gez.S */
1959/* File: arm/zcmp.S */
1960 /*
1961 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1962 * fragment that specifies the *reverse* comparison to perform, e.g.
1963 * for "if-le" you would use "gt".
1964 *
1965 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1966 */
1967 /* if-cmp vAA, +BBBB */
1968#if MTERP_SUSPEND
1969 mov r0, rINST, lsr #8 @ r0<- AA
1970 GET_VREG r2, r0 @ r2<- vAA
1971 FETCH_S r1, 1 @ r1<- branch offset, in code units
1972 cmp r2, #0 @ compare (vA, 0)
1973 movlt r1, #2 @ r1<- inst branch dist for not-taken
1974 adds r1, r1, r1 @ convert to bytes & set flags
1975 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1976 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh table base
1977 GET_INST_OPCODE ip @ extract opcode from rINST
1978 GOTO_OPCODE ip @ jump to next instruction
1979#else
1980 mov r0, rINST, lsr #8 @ r0<- AA
1981 GET_VREG r2, r0 @ r2<- vAA
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1982 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1983 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
1984 cmp r2, #0 @ compare (vA, 0)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]1985 movlt rINST, #2 @ rINST<- inst branch dist for not-taken
1986#if MTERP_PROFILE_BRANCHES
1987 mov r0, rSELF
1988 add r1, rFP, #OFF_FP_SHADOWFRAME
1989 mov r2, rINST
1990 bl MterpProfileBranch @ (self, shadow_frame, offset)
1991 cmp r0, #0
1992 bne MterpOnStackReplacement @ Note: offset must be in rINST
1993#endif
1994 adds r1, rINST, rINST @ convert to bytes & set flags
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]1995 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
1996 bmi MterpCheckSuspendAndContinue
1997 GET_INST_OPCODE ip @ extract opcode from rINST
1998 GOTO_OPCODE ip @ jump to next instruction
1999#endif
2000
2001
2002/* ------------------------------ */
2003 .balign 128
2004.L_op_if_gtz: /* 0x3c */
2005/* File: arm/op_if_gtz.S */
2006/* File: arm/zcmp.S */
2007 /*
2008 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
2009 * fragment that specifies the *reverse* comparison to perform, e.g.
2010 * for "if-le" you would use "gt".
2011 *
2012 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
2013 */
2014 /* if-cmp vAA, +BBBB */
2015#if MTERP_SUSPEND
2016 mov r0, rINST, lsr #8 @ r0<- AA
2017 GET_VREG r2, r0 @ r2<- vAA
2018 FETCH_S r1, 1 @ r1<- branch offset, in code units
2019 cmp r2, #0 @ compare (vA, 0)
2020 movle r1, #2 @ r1<- inst branch dist for not-taken
2021 adds r1, r1, r1 @ convert to bytes & set flags
2022 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
2023 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh table base
2024 GET_INST_OPCODE ip @ extract opcode from rINST
2025 GOTO_OPCODE ip @ jump to next instruction
2026#else
2027 mov r0, rINST, lsr #8 @ r0<- AA
2028 GET_VREG r2, r0 @ r2<- vAA
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]2029 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2030 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
2031 cmp r2, #0 @ compare (vA, 0)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]2032 movle rINST, #2 @ rINST<- inst branch dist for not-taken
2033#if MTERP_PROFILE_BRANCHES
2034 mov r0, rSELF
2035 add r1, rFP, #OFF_FP_SHADOWFRAME
2036 mov r2, rINST
2037 bl MterpProfileBranch @ (self, shadow_frame, offset)
2038 cmp r0, #0
2039 bne MterpOnStackReplacement @ Note: offset must be in rINST
2040#endif
2041 adds r1, rINST, rINST @ convert to bytes & set flags
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2042 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
2043 bmi MterpCheckSuspendAndContinue
2044 GET_INST_OPCODE ip @ extract opcode from rINST
2045 GOTO_OPCODE ip @ jump to next instruction
2046#endif
2047
2048
2049/* ------------------------------ */
2050 .balign 128
2051.L_op_if_lez: /* 0x3d */
2052/* File: arm/op_if_lez.S */
2053/* File: arm/zcmp.S */
2054 /*
2055 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
2056 * fragment that specifies the *reverse* comparison to perform, e.g.
2057 * for "if-le" you would use "gt".
2058 *
2059 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
2060 */
2061 /* if-cmp vAA, +BBBB */
2062#if MTERP_SUSPEND
2063 mov r0, rINST, lsr #8 @ r0<- AA
2064 GET_VREG r2, r0 @ r2<- vAA
2065 FETCH_S r1, 1 @ r1<- branch offset, in code units
2066 cmp r2, #0 @ compare (vA, 0)
2067 movgt r1, #2 @ r1<- inst branch dist for not-taken
2068 adds r1, r1, r1 @ convert to bytes & set flags
2069 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
2070 ldrmi rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh table base
2071 GET_INST_OPCODE ip @ extract opcode from rINST
2072 GOTO_OPCODE ip @ jump to next instruction
2073#else
2074 mov r0, rINST, lsr #8 @ r0<- AA
2075 GET_VREG r2, r0 @ r2<- vAA
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]2076 FETCH_S rINST, 1 @ rINST<- branch offset, in code units
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2077 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
2078 cmp r2, #0 @ compare (vA, 0)
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]2079 movgt rINST, #2 @ rINST<- inst branch dist for not-taken
2080#if MTERP_PROFILE_BRANCHES
2081 mov r0, rSELF
2082 add r1, rFP, #OFF_FP_SHADOWFRAME
2083 mov r2, rINST
2084 bl MterpProfileBranch @ (self, shadow_frame, offset)
2085 cmp r0, #0
2086 bne MterpOnStackReplacement @ Note: offset must be in rINST
2087#endif
2088 adds r1, rINST, rINST @ convert to bytes & set flags
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2089 FETCH_ADVANCE_INST_RB r1 @ update rPC, load rINST
2090 bmi MterpCheckSuspendAndContinue
2091 GET_INST_OPCODE ip @ extract opcode from rINST
2092 GOTO_OPCODE ip @ jump to next instruction
2093#endif
2094
2095
2096/* ------------------------------ */
2097 .balign 128
2098.L_op_unused_3e: /* 0x3e */
2099/* File: arm/op_unused_3e.S */
2100/* File: arm/unused.S */
2101/*
2102 * Bail to reference interpreter to throw.
2103 */
2104 b MterpFallback
2105
2106
2107/* ------------------------------ */
2108 .balign 128
2109.L_op_unused_3f: /* 0x3f */
2110/* File: arm/op_unused_3f.S */
2111/* File: arm/unused.S */
2112/*
2113 * Bail to reference interpreter to throw.
2114 */
2115 b MterpFallback
2116
2117
2118/* ------------------------------ */
2119 .balign 128
2120.L_op_unused_40: /* 0x40 */
2121/* File: arm/op_unused_40.S */
2122/* File: arm/unused.S */
2123/*
2124 * Bail to reference interpreter to throw.
2125 */
2126 b MterpFallback
2127
2128
2129/* ------------------------------ */
2130 .balign 128
2131.L_op_unused_41: /* 0x41 */
2132/* File: arm/op_unused_41.S */
2133/* File: arm/unused.S */
2134/*
2135 * Bail to reference interpreter to throw.
2136 */
2137 b MterpFallback
2138
2139
2140/* ------------------------------ */
2141 .balign 128
2142.L_op_unused_42: /* 0x42 */
2143/* File: arm/op_unused_42.S */
2144/* File: arm/unused.S */
2145/*
2146 * Bail to reference interpreter to throw.
2147 */
2148 b MterpFallback
2149
2150
2151/* ------------------------------ */
2152 .balign 128
2153.L_op_unused_43: /* 0x43 */
2154/* File: arm/op_unused_43.S */
2155/* File: arm/unused.S */
2156/*
2157 * Bail to reference interpreter to throw.
2158 */
2159 b MterpFallback
2160
2161
2162/* ------------------------------ */
2163 .balign 128
2164.L_op_aget: /* 0x44 */
2165/* File: arm/op_aget.S */
2166 /*
2167 * Array get, 32 bits or less. vAA <- vBB[vCC].
2168 *
2169 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2170 * instructions. We use a pair of FETCH_Bs instead.
2171 *
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]2172 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2173 *
2174 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2175 * If this changes, specialize.
2176 */
2177 /* op vAA, vBB, vCC */
2178 FETCH_B r2, 1, 0 @ r2<- BB
2179 mov r9, rINST, lsr #8 @ r9<- AA
2180 FETCH_B r3, 1, 1 @ r3<- CC
2181 GET_VREG r0, r2 @ r0<- vBB (array object)
2182 GET_VREG r1, r3 @ r1<- vCC (requested index)
2183 cmp r0, #0 @ null array object?
2184 beq common_errNullObject @ yes, bail
2185 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2186 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2187 cmp r1, r3 @ compare unsigned index, length
2188 bcs common_errArrayIndex @ index >= length, bail
2189 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2190 ldr r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC]
2191 GET_INST_OPCODE ip @ extract opcode from rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2192 SET_VREG r2, r9 @ vAA<- r2
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2193 GOTO_OPCODE ip @ jump to next instruction
2194
2195/* ------------------------------ */
2196 .balign 128
2197.L_op_aget_wide: /* 0x45 */
2198/* File: arm/op_aget_wide.S */
2199 /*
2200 * Array get, 64 bits. vAA <- vBB[vCC].
2201 *
2202 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD.
2203 */
2204 /* aget-wide vAA, vBB, vCC */
2205 FETCH r0, 1 @ r0<- CCBB
2206 mov r9, rINST, lsr #8 @ r9<- AA
2207 and r2, r0, #255 @ r2<- BB
2208 mov r3, r0, lsr #8 @ r3<- CC
2209 GET_VREG r0, r2 @ r0<- vBB (array object)
2210 GET_VREG r1, r3 @ r1<- vCC (requested index)
2211 cmp r0, #0 @ null array object?
2212 beq common_errNullObject @ yes, bail
2213 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2214 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
2215 cmp r1, r3 @ compare unsigned index, length
2216 bcs common_errArrayIndex @ index >= length, bail
2217 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2218 ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC]
2219 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2220 GET_INST_OPCODE ip @ extract opcode from rINST
2221 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3
2222 GOTO_OPCODE ip @ jump to next instruction
2223
2224/* ------------------------------ */
2225 .balign 128
2226.L_op_aget_object: /* 0x46 */
2227/* File: arm/op_aget_object.S */
2228 /*
2229 * Array object get. vAA <- vBB[vCC].
2230 *
2231 * for: aget-object
2232 */
2233 /* op vAA, vBB, vCC */
2234 FETCH_B r2, 1, 0 @ r2<- BB
2235 mov r9, rINST, lsr #8 @ r9<- AA
2236 FETCH_B r3, 1, 1 @ r3<- CC
2237 EXPORT_PC
2238 GET_VREG r0, r2 @ r0<- vBB (array object)
2239 GET_VREG r1, r3 @ r1<- vCC (requested index)
2240 bl artAGetObjectFromMterp @ (array, index)
2241 ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET]
2242 PREFETCH_INST 2
2243 cmp r1, #0
2244 bne MterpException
2245 SET_VREG_OBJECT r0, r9
2246 ADVANCE 2
2247 GET_INST_OPCODE ip
2248 GOTO_OPCODE ip @ jump to next instruction
2249
2250/* ------------------------------ */
2251 .balign 128
2252.L_op_aget_boolean: /* 0x47 */
2253/* File: arm/op_aget_boolean.S */
2254/* File: arm/op_aget.S */
2255 /*
2256 * Array get, 32 bits or less. vAA <- vBB[vCC].
2257 *
2258 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2259 * instructions. We use a pair of FETCH_Bs instead.
2260 *
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]2261 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2262 *
2263 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2264 * If this changes, specialize.
2265 */
2266 /* op vAA, vBB, vCC */
2267 FETCH_B r2, 1, 0 @ r2<- BB
2268 mov r9, rINST, lsr #8 @ r9<- AA
2269 FETCH_B r3, 1, 1 @ r3<- CC
2270 GET_VREG r0, r2 @ r0<- vBB (array object)
2271 GET_VREG r1, r3 @ r1<- vCC (requested index)
2272 cmp r0, #0 @ null array object?
2273 beq common_errNullObject @ yes, bail
2274 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2275 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2276 cmp r1, r3 @ compare unsigned index, length
2277 bcs common_errArrayIndex @ index >= length, bail
2278 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2279 ldrb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC]
2280 GET_INST_OPCODE ip @ extract opcode from rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2281 SET_VREG r2, r9 @ vAA<- r2
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2282 GOTO_OPCODE ip @ jump to next instruction
2283
2284
2285/* ------------------------------ */
2286 .balign 128
2287.L_op_aget_byte: /* 0x48 */
2288/* File: arm/op_aget_byte.S */
2289/* File: arm/op_aget.S */
2290 /*
2291 * Array get, 32 bits or less. vAA <- vBB[vCC].
2292 *
2293 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2294 * instructions. We use a pair of FETCH_Bs instead.
2295 *
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]2296 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2297 *
2298 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2299 * If this changes, specialize.
2300 */
2301 /* op vAA, vBB, vCC */
2302 FETCH_B r2, 1, 0 @ r2<- BB
2303 mov r9, rINST, lsr #8 @ r9<- AA
2304 FETCH_B r3, 1, 1 @ r3<- CC
2305 GET_VREG r0, r2 @ r0<- vBB (array object)
2306 GET_VREG r1, r3 @ r1<- vCC (requested index)
2307 cmp r0, #0 @ null array object?
2308 beq common_errNullObject @ yes, bail
2309 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2310 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2311 cmp r1, r3 @ compare unsigned index, length
2312 bcs common_errArrayIndex @ index >= length, bail
2313 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2314 ldrsb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC]
2315 GET_INST_OPCODE ip @ extract opcode from rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2316 SET_VREG r2, r9 @ vAA<- r2
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2317 GOTO_OPCODE ip @ jump to next instruction
2318
2319
2320/* ------------------------------ */
2321 .balign 128
2322.L_op_aget_char: /* 0x49 */
2323/* File: arm/op_aget_char.S */
2324/* File: arm/op_aget.S */
2325 /*
2326 * Array get, 32 bits or less. vAA <- vBB[vCC].
2327 *
2328 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2329 * instructions. We use a pair of FETCH_Bs instead.
2330 *
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]2331 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2332 *
2333 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2334 * If this changes, specialize.
2335 */
2336 /* op vAA, vBB, vCC */
2337 FETCH_B r2, 1, 0 @ r2<- BB
2338 mov r9, rINST, lsr #8 @ r9<- AA
2339 FETCH_B r3, 1, 1 @ r3<- CC
2340 GET_VREG r0, r2 @ r0<- vBB (array object)
2341 GET_VREG r1, r3 @ r1<- vCC (requested index)
2342 cmp r0, #0 @ null array object?
2343 beq common_errNullObject @ yes, bail
2344 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2345 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2346 cmp r1, r3 @ compare unsigned index, length
2347 bcs common_errArrayIndex @ index >= length, bail
2348 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2349 ldrh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC]
2350 GET_INST_OPCODE ip @ extract opcode from rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2351 SET_VREG r2, r9 @ vAA<- r2
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2352 GOTO_OPCODE ip @ jump to next instruction
2353
2354
2355/* ------------------------------ */
2356 .balign 128
2357.L_op_aget_short: /* 0x4a */
2358/* File: arm/op_aget_short.S */
2359/* File: arm/op_aget.S */
2360 /*
2361 * Array get, 32 bits or less. vAA <- vBB[vCC].
2362 *
2363 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2364 * instructions. We use a pair of FETCH_Bs instead.
2365 *
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]2366 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2367 *
2368 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2369 * If this changes, specialize.
2370 */
2371 /* op vAA, vBB, vCC */
2372 FETCH_B r2, 1, 0 @ r2<- BB
2373 mov r9, rINST, lsr #8 @ r9<- AA
2374 FETCH_B r3, 1, 1 @ r3<- CC
2375 GET_VREG r0, r2 @ r0<- vBB (array object)
2376 GET_VREG r1, r3 @ r1<- vCC (requested index)
2377 cmp r0, #0 @ null array object?
2378 beq common_errNullObject @ yes, bail
2379 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2380 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2381 cmp r1, r3 @ compare unsigned index, length
2382 bcs common_errArrayIndex @ index >= length, bail
2383 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2384 ldrsh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC]
2385 GET_INST_OPCODE ip @ extract opcode from rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2386 SET_VREG r2, r9 @ vAA<- r2
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]2387 GOTO_OPCODE ip @ jump to next instruction
2388
2389
2390/* ------------------------------ */
2391 .balign 128
2392.L_op_aput: /* 0x4b */
2393/* File: arm/op_aput.S */
2394 /*
2395 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2396 *
2397 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2398 * instructions. We use a pair of FETCH_Bs instead.
2399 *
2400 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2401 *
2402 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2403 * If this changes, specialize.
2404 */
2405 /* op vAA, vBB, vCC */
2406 FETCH_B r2, 1, 0 @ r2<- BB
2407 mov r9, rINST, lsr #8 @ r9<- AA
2408 FETCH_B r3, 1, 1 @ r3<- CC
2409 GET_VREG r0, r2 @ r0<- vBB (array object)
2410 GET_VREG r1, r3 @ r1<- vCC (requested index)
2411 cmp r0, #0 @ null array object?
2412 beq common_errNullObject @ yes, bail
2413 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2414 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2415 cmp r1, r3 @ compare unsigned index, length
2416 bcs common_errArrayIndex @ index >= length, bail
2417 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2418 GET_VREG r2, r9 @ r2<- vAA
2419 GET_INST_OPCODE ip @ extract opcode from rINST
2420 str r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2
2421 GOTO_OPCODE ip @ jump to next instruction
2422
2423/* ------------------------------ */
2424 .balign 128
2425.L_op_aput_wide: /* 0x4c */
2426/* File: arm/op_aput_wide.S */
2427 /*
2428 * Array put, 64 bits. vBB[vCC] <- vAA.
2429 *
2430 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD.
2431 */
2432 /* aput-wide vAA, vBB, vCC */
2433 FETCH r0, 1 @ r0<- CCBB
2434 mov r9, rINST, lsr #8 @ r9<- AA
2435 and r2, r0, #255 @ r2<- BB
2436 mov r3, r0, lsr #8 @ r3<- CC
2437 GET_VREG r0, r2 @ r0<- vBB (array object)
2438 GET_VREG r1, r3 @ r1<- vCC (requested index)
2439 cmp r0, #0 @ null array object?
2440 beq common_errNullObject @ yes, bail
2441 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2442 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
2443 cmp r1, r3 @ compare unsigned index, length
2444 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2445 bcs common_errArrayIndex @ index >= length, bail
2446 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2447 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1
2448 GET_INST_OPCODE ip @ extract opcode from rINST
2449 strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC]
2450 GOTO_OPCODE ip @ jump to next instruction
2451
2452/* ------------------------------ */
2453 .balign 128
2454.L_op_aput_object: /* 0x4d */
2455/* File: arm/op_aput_object.S */
2456 /*
2457 * Store an object into an array. vBB[vCC] <- vAA.
2458 */
2459 /* op vAA, vBB, vCC */
2460 EXPORT_PC
2461 add r0, rFP, #OFF_FP_SHADOWFRAME
2462 mov r1, rPC
2463 mov r2, rINST
2464 bl MterpAputObject
2465 cmp r0, #0
2466 beq MterpPossibleException
2467 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2468 GET_INST_OPCODE ip @ extract opcode from rINST
2469 GOTO_OPCODE ip @ jump to next instruction
2470
2471/* ------------------------------ */
2472 .balign 128
2473.L_op_aput_boolean: /* 0x4e */
2474/* File: arm/op_aput_boolean.S */
2475/* File: arm/op_aput.S */
2476 /*
2477 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2478 *
2479 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2480 * instructions. We use a pair of FETCH_Bs instead.
2481 *
2482 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2483 *
2484 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2485 * If this changes, specialize.
2486 */
2487 /* op vAA, vBB, vCC */
2488 FETCH_B r2, 1, 0 @ r2<- BB
2489 mov r9, rINST, lsr #8 @ r9<- AA
2490 FETCH_B r3, 1, 1 @ r3<- CC
2491 GET_VREG r0, r2 @ r0<- vBB (array object)
2492 GET_VREG r1, r3 @ r1<- vCC (requested index)
2493 cmp r0, #0 @ null array object?
2494 beq common_errNullObject @ yes, bail
2495 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2496 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2497 cmp r1, r3 @ compare unsigned index, length
2498 bcs common_errArrayIndex @ index >= length, bail
2499 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2500 GET_VREG r2, r9 @ r2<- vAA
2501 GET_INST_OPCODE ip @ extract opcode from rINST
2502 strb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2
2503 GOTO_OPCODE ip @ jump to next instruction
2504
2505
2506/* ------------------------------ */
2507 .balign 128
2508.L_op_aput_byte: /* 0x4f */
2509/* File: arm/op_aput_byte.S */
2510/* File: arm/op_aput.S */
2511 /*
2512 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2513 *
2514 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2515 * instructions. We use a pair of FETCH_Bs instead.
2516 *
2517 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2518 *
2519 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2520 * If this changes, specialize.
2521 */
2522 /* op vAA, vBB, vCC */
2523 FETCH_B r2, 1, 0 @ r2<- BB
2524 mov r9, rINST, lsr #8 @ r9<- AA
2525 FETCH_B r3, 1, 1 @ r3<- CC
2526 GET_VREG r0, r2 @ r0<- vBB (array object)
2527 GET_VREG r1, r3 @ r1<- vCC (requested index)
2528 cmp r0, #0 @ null array object?
2529 beq common_errNullObject @ yes, bail
2530 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2531 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2532 cmp r1, r3 @ compare unsigned index, length
2533 bcs common_errArrayIndex @ index >= length, bail
2534 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2535 GET_VREG r2, r9 @ r2<- vAA
2536 GET_INST_OPCODE ip @ extract opcode from rINST
2537 strb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2
2538 GOTO_OPCODE ip @ jump to next instruction
2539
2540
2541/* ------------------------------ */
2542 .balign 128
2543.L_op_aput_char: /* 0x50 */
2544/* File: arm/op_aput_char.S */
2545/* File: arm/op_aput.S */
2546 /*
2547 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2548 *
2549 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2550 * instructions. We use a pair of FETCH_Bs instead.
2551 *
2552 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2553 *
2554 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2555 * If this changes, specialize.
2556 */
2557 /* op vAA, vBB, vCC */
2558 FETCH_B r2, 1, 0 @ r2<- BB
2559 mov r9, rINST, lsr #8 @ r9<- AA
2560 FETCH_B r3, 1, 1 @ r3<- CC
2561 GET_VREG r0, r2 @ r0<- vBB (array object)
2562 GET_VREG r1, r3 @ r1<- vCC (requested index)
2563 cmp r0, #0 @ null array object?
2564 beq common_errNullObject @ yes, bail
2565 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2566 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2567 cmp r1, r3 @ compare unsigned index, length
2568 bcs common_errArrayIndex @ index >= length, bail
2569 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2570 GET_VREG r2, r9 @ r2<- vAA
2571 GET_INST_OPCODE ip @ extract opcode from rINST
2572 strh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2
2573 GOTO_OPCODE ip @ jump to next instruction
2574
2575
2576/* ------------------------------ */
2577 .balign 128
2578.L_op_aput_short: /* 0x51 */
2579/* File: arm/op_aput_short.S */
2580/* File: arm/op_aput.S */
2581 /*
2582 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2583 *
2584 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2585 * instructions. We use a pair of FETCH_Bs instead.
2586 *
2587 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2588 *
2589 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2590 * If this changes, specialize.
2591 */
2592 /* op vAA, vBB, vCC */
2593 FETCH_B r2, 1, 0 @ r2<- BB
2594 mov r9, rINST, lsr #8 @ r9<- AA
2595 FETCH_B r3, 1, 1 @ r3<- CC
2596 GET_VREG r0, r2 @ r0<- vBB (array object)
2597 GET_VREG r1, r3 @ r1<- vCC (requested index)
2598 cmp r0, #0 @ null array object?
2599 beq common_errNullObject @ yes, bail
2600 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length
2601 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2602 cmp r1, r3 @ compare unsigned index, length
2603 bcs common_errArrayIndex @ index >= length, bail
2604 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2605 GET_VREG r2, r9 @ r2<- vAA
2606 GET_INST_OPCODE ip @ extract opcode from rINST
2607 strh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2
2608 GOTO_OPCODE ip @ jump to next instruction
2609
2610
2611/* ------------------------------ */
2612 .balign 128
2613.L_op_iget: /* 0x52 */
2614/* File: arm/op_iget.S */
2615 /*
2616 * General instance field get.
2617 *
2618 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2619 */
2620 EXPORT_PC
2621 FETCH r0, 1 @ r0<- field ref CCCC
2622 mov r1, rINST, lsr #12 @ r1<- B
2623 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2624 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer
2625 mov r3, rSELF @ r3<- self
2626 bl artGet32InstanceFromCode
2627 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
2628 ubfx r2, rINST, #8, #4 @ r2<- A
2629 PREFETCH_INST 2
2630 cmp r3, #0
2631 bne MterpPossibleException @ bail out
2632 .if 0
2633 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0
2634 .else
2635 SET_VREG r0, r2 @ fp[A]<- r0
2636 .endif
2637 ADVANCE 2
2638 GET_INST_OPCODE ip @ extract opcode from rINST
2639 GOTO_OPCODE ip @ jump to next instruction
2640
2641/* ------------------------------ */
2642 .balign 128
2643.L_op_iget_wide: /* 0x53 */
2644/* File: arm/op_iget_wide.S */
2645 /*
2646 * 64-bit instance field get.
2647 *
2648 * for: iget-wide
2649 */
2650 EXPORT_PC
2651 FETCH r0, 1 @ r0<- field ref CCCC
2652 mov r1, rINST, lsr #12 @ r1<- B
2653 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2654 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer
2655 mov r3, rSELF @ r3<- self
2656 bl artGet64InstanceFromCode
2657 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
2658 ubfx r2, rINST, #8, #4 @ r2<- A
2659 PREFETCH_INST 2
2660 cmp r3, #0
2661 bne MterpException @ bail out
2662 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
2663 stmia r3, {r0-r1} @ fp[A]<- r0/r1
2664 ADVANCE 2
2665 GET_INST_OPCODE ip @ extract opcode from rINST
2666 GOTO_OPCODE ip @ jump to next instruction
2667
2668/* ------------------------------ */
2669 .balign 128
2670.L_op_iget_object: /* 0x54 */
2671/* File: arm/op_iget_object.S */
2672/* File: arm/op_iget.S */
2673 /*
2674 * General instance field get.
2675 *
2676 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2677 */
2678 EXPORT_PC
2679 FETCH r0, 1 @ r0<- field ref CCCC
2680 mov r1, rINST, lsr #12 @ r1<- B
2681 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2682 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer
2683 mov r3, rSELF @ r3<- self
2684 bl artGetObjInstanceFromCode
2685 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
2686 ubfx r2, rINST, #8, #4 @ r2<- A
2687 PREFETCH_INST 2
2688 cmp r3, #0
2689 bne MterpPossibleException @ bail out
2690 .if 1
2691 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0
2692 .else
2693 SET_VREG r0, r2 @ fp[A]<- r0
2694 .endif
2695 ADVANCE 2
2696 GET_INST_OPCODE ip @ extract opcode from rINST
2697 GOTO_OPCODE ip @ jump to next instruction
2698
2699
2700/* ------------------------------ */
2701 .balign 128
2702.L_op_iget_boolean: /* 0x55 */
2703/* File: arm/op_iget_boolean.S */
2704/* File: arm/op_iget.S */
2705 /*
2706 * General instance field get.
2707 *
2708 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2709 */
2710 EXPORT_PC
2711 FETCH r0, 1 @ r0<- field ref CCCC
2712 mov r1, rINST, lsr #12 @ r1<- B
2713 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2714 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer
2715 mov r3, rSELF @ r3<- self
2716 bl artGetBooleanInstanceFromCode
2717 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
2718 ubfx r2, rINST, #8, #4 @ r2<- A
2719 PREFETCH_INST 2
2720 cmp r3, #0
2721 bne MterpPossibleException @ bail out
2722 .if 0
2723 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0
2724 .else
2725 SET_VREG r0, r2 @ fp[A]<- r0
2726 .endif
2727 ADVANCE 2
2728 GET_INST_OPCODE ip @ extract opcode from rINST
2729 GOTO_OPCODE ip @ jump to next instruction
2730
2731
2732/* ------------------------------ */
2733 .balign 128
2734.L_op_iget_byte: /* 0x56 */
2735/* File: arm/op_iget_byte.S */
2736/* File: arm/op_iget.S */
2737 /*
2738 * General instance field get.
2739 *
2740 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2741 */
2742 EXPORT_PC
2743 FETCH r0, 1 @ r0<- field ref CCCC
2744 mov r1, rINST, lsr #12 @ r1<- B
2745 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2746 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer
2747 mov r3, rSELF @ r3<- self
2748 bl artGetByteInstanceFromCode
2749 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
2750 ubfx r2, rINST, #8, #4 @ r2<- A
2751 PREFETCH_INST 2
2752 cmp r3, #0
2753 bne MterpPossibleException @ bail out
2754 .if 0
2755 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0
2756 .else
2757 SET_VREG r0, r2 @ fp[A]<- r0
2758 .endif
2759 ADVANCE 2
2760 GET_INST_OPCODE ip @ extract opcode from rINST
2761 GOTO_OPCODE ip @ jump to next instruction
2762
2763
2764/* ------------------------------ */
2765 .balign 128
2766.L_op_iget_char: /* 0x57 */
2767/* File: arm/op_iget_char.S */
2768/* File: arm/op_iget.S */
2769 /*
2770 * General instance field get.
2771 *
2772 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2773 */
2774 EXPORT_PC
2775 FETCH r0, 1 @ r0<- field ref CCCC
2776 mov r1, rINST, lsr #12 @ r1<- B
2777 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2778 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer
2779 mov r3, rSELF @ r3<- self
2780 bl artGetCharInstanceFromCode
2781 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
2782 ubfx r2, rINST, #8, #4 @ r2<- A
2783 PREFETCH_INST 2
2784 cmp r3, #0
2785 bne MterpPossibleException @ bail out
2786 .if 0
2787 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0
2788 .else
2789 SET_VREG r0, r2 @ fp[A]<- r0
2790 .endif
2791 ADVANCE 2
2792 GET_INST_OPCODE ip @ extract opcode from rINST
2793 GOTO_OPCODE ip @ jump to next instruction
2794
2795
2796/* ------------------------------ */
2797 .balign 128
2798.L_op_iget_short: /* 0x58 */
2799/* File: arm/op_iget_short.S */
2800/* File: arm/op_iget.S */
2801 /*
2802 * General instance field get.
2803 *
2804 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2805 */
2806 EXPORT_PC
2807 FETCH r0, 1 @ r0<- field ref CCCC
2808 mov r1, rINST, lsr #12 @ r1<- B
2809 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2810 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer
2811 mov r3, rSELF @ r3<- self
2812 bl artGetShortInstanceFromCode
2813 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
2814 ubfx r2, rINST, #8, #4 @ r2<- A
2815 PREFETCH_INST 2
2816 cmp r3, #0
2817 bne MterpPossibleException @ bail out
2818 .if 0
2819 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0
2820 .else
2821 SET_VREG r0, r2 @ fp[A]<- r0
2822 .endif
2823 ADVANCE 2
2824 GET_INST_OPCODE ip @ extract opcode from rINST
2825 GOTO_OPCODE ip @ jump to next instruction
2826
2827
2828/* ------------------------------ */
2829 .balign 128
2830.L_op_iput: /* 0x59 */
2831/* File: arm/op_iput.S */
2832 /*
2833 * General 32-bit instance field put.
2834 *
2835 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
2836 */
2837 /* op vA, vB, field@CCCC */
2838 .extern artSet32InstanceFromMterp
2839 EXPORT_PC
2840 FETCH r0, 1 @ r0<- field ref CCCC
2841 mov r1, rINST, lsr #12 @ r1<- B
2842 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2843 ubfx r2, rINST, #8, #4 @ r2<- A
2844 GET_VREG r2, r2 @ r2<- fp[A]
2845 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer
2846 PREFETCH_INST 2
2847 bl artSet32InstanceFromMterp
2848 cmp r0, #0
2849 bne MterpPossibleException
2850 ADVANCE 2 @ advance rPC
2851 GET_INST_OPCODE ip @ extract opcode from rINST
2852 GOTO_OPCODE ip @ jump to next instruction
2853
2854/* ------------------------------ */
2855 .balign 128
2856.L_op_iput_wide: /* 0x5a */
2857/* File: arm/op_iput_wide.S */
2858 /* iput-wide vA, vB, field@CCCC */
2859 .extern artSet64InstanceFromMterp
2860 EXPORT_PC
2861 FETCH r0, 1 @ r0<- field ref CCCC
2862 mov r1, rINST, lsr #12 @ r1<- B
2863 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2864 ubfx r2, rINST, #8, #4 @ r2<- A
2865 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
2866 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer
2867 PREFETCH_INST 2
2868 bl artSet64InstanceFromMterp
2869 cmp r0, #0
2870 bne MterpPossibleException
2871 ADVANCE 2 @ advance rPC
2872 GET_INST_OPCODE ip @ extract opcode from rINST
2873 GOTO_OPCODE ip @ jump to next instruction
2874
2875/* ------------------------------ */
2876 .balign 128
2877.L_op_iput_object: /* 0x5b */
2878/* File: arm/op_iput_object.S */
2879 EXPORT_PC
2880 add r0, rFP, #OFF_FP_SHADOWFRAME
2881 mov r1, rPC
2882 mov r2, rINST
2883 mov r3, rSELF
2884 bl MterpIputObject
2885 cmp r0, #0
2886 beq MterpException
2887 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
2888 GET_INST_OPCODE ip @ extract opcode from rINST
2889 GOTO_OPCODE ip @ jump to next instruction
2890
2891/* ------------------------------ */
2892 .balign 128
2893.L_op_iput_boolean: /* 0x5c */
2894/* File: arm/op_iput_boolean.S */
2895/* File: arm/op_iput.S */
2896 /*
2897 * General 32-bit instance field put.
2898 *
2899 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
2900 */
2901 /* op vA, vB, field@CCCC */
2902 .extern artSet8InstanceFromMterp
2903 EXPORT_PC
2904 FETCH r0, 1 @ r0<- field ref CCCC
2905 mov r1, rINST, lsr #12 @ r1<- B
2906 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2907 ubfx r2, rINST, #8, #4 @ r2<- A
2908 GET_VREG r2, r2 @ r2<- fp[A]
2909 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer
2910 PREFETCH_INST 2
2911 bl artSet8InstanceFromMterp
2912 cmp r0, #0
2913 bne MterpPossibleException
2914 ADVANCE 2 @ advance rPC
2915 GET_INST_OPCODE ip @ extract opcode from rINST
2916 GOTO_OPCODE ip @ jump to next instruction
2917
2918
2919/* ------------------------------ */
2920 .balign 128
2921.L_op_iput_byte: /* 0x5d */
2922/* File: arm/op_iput_byte.S */
2923/* File: arm/op_iput.S */
2924 /*
2925 * General 32-bit instance field put.
2926 *
2927 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
2928 */
2929 /* op vA, vB, field@CCCC */
2930 .extern artSet8InstanceFromMterp
2931 EXPORT_PC
2932 FETCH r0, 1 @ r0<- field ref CCCC
2933 mov r1, rINST, lsr #12 @ r1<- B
2934 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2935 ubfx r2, rINST, #8, #4 @ r2<- A
2936 GET_VREG r2, r2 @ r2<- fp[A]
2937 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer
2938 PREFETCH_INST 2
2939 bl artSet8InstanceFromMterp
2940 cmp r0, #0
2941 bne MterpPossibleException
2942 ADVANCE 2 @ advance rPC
2943 GET_INST_OPCODE ip @ extract opcode from rINST
2944 GOTO_OPCODE ip @ jump to next instruction
2945
2946
2947/* ------------------------------ */
2948 .balign 128
2949.L_op_iput_char: /* 0x5e */
2950/* File: arm/op_iput_char.S */
2951/* File: arm/op_iput.S */
2952 /*
2953 * General 32-bit instance field put.
2954 *
2955 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
2956 */
2957 /* op vA, vB, field@CCCC */
2958 .extern artSet16InstanceFromMterp
2959 EXPORT_PC
2960 FETCH r0, 1 @ r0<- field ref CCCC
2961 mov r1, rINST, lsr #12 @ r1<- B
2962 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2963 ubfx r2, rINST, #8, #4 @ r2<- A
2964 GET_VREG r2, r2 @ r2<- fp[A]
2965 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer
2966 PREFETCH_INST 2
2967 bl artSet16InstanceFromMterp
2968 cmp r0, #0
2969 bne MterpPossibleException
2970 ADVANCE 2 @ advance rPC
2971 GET_INST_OPCODE ip @ extract opcode from rINST
2972 GOTO_OPCODE ip @ jump to next instruction
2973
2974
2975/* ------------------------------ */
2976 .balign 128
2977.L_op_iput_short: /* 0x5f */
2978/* File: arm/op_iput_short.S */
2979/* File: arm/op_iput.S */
2980 /*
2981 * General 32-bit instance field put.
2982 *
2983 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
2984 */
2985 /* op vA, vB, field@CCCC */
2986 .extern artSet16InstanceFromMterp
2987 EXPORT_PC
2988 FETCH r0, 1 @ r0<- field ref CCCC
2989 mov r1, rINST, lsr #12 @ r1<- B
2990 GET_VREG r1, r1 @ r1<- fp[B], the object pointer
2991 ubfx r2, rINST, #8, #4 @ r2<- A
2992 GET_VREG r2, r2 @ r2<- fp[A]
2993 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer
2994 PREFETCH_INST 2
2995 bl artSet16InstanceFromMterp
2996 cmp r0, #0
2997 bne MterpPossibleException
2998 ADVANCE 2 @ advance rPC
2999 GET_INST_OPCODE ip @ extract opcode from rINST
3000 GOTO_OPCODE ip @ jump to next instruction
3001
3002
3003/* ------------------------------ */
3004 .balign 128
3005.L_op_sget: /* 0x60 */
3006/* File: arm/op_sget.S */
3007 /*
3008 * General SGET handler wrapper.
3009 *
3010 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3011 */
3012 /* op vAA, field@BBBB */
3013
3014 .extern artGet32StaticFromCode
3015 EXPORT_PC
3016 FETCH r0, 1 @ r0<- field ref BBBB
3017 ldr r1, [rFP, #OFF_FP_METHOD]
3018 mov r2, rSELF
3019 bl artGet32StaticFromCode
3020 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
3021 mov r2, rINST, lsr #8 @ r2<- AA
3022 PREFETCH_INST 2
3023 cmp r3, #0 @ Fail to resolve?
3024 bne MterpException @ bail out
3025.if 0
3026 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0
3027.else
3028 SET_VREG r0, r2 @ fp[AA]<- r0
3029.endif
3030 ADVANCE 2
3031 GET_INST_OPCODE ip @ extract opcode from rINST
3032 GOTO_OPCODE ip
3033
3034/* ------------------------------ */
3035 .balign 128
3036.L_op_sget_wide: /* 0x61 */
3037/* File: arm/op_sget_wide.S */
3038 /*
3039 * SGET_WIDE handler wrapper.
3040 *
3041 */
3042 /* sget-wide vAA, field@BBBB */
3043
3044 .extern artGet64StaticFromCode
3045 EXPORT_PC
3046 FETCH r0, 1 @ r0<- field ref BBBB
3047 ldr r1, [rFP, #OFF_FP_METHOD]
3048 mov r2, rSELF
3049 bl artGet64StaticFromCode
3050 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
3051 mov r9, rINST, lsr #8 @ r9<- AA
3052 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
3053 cmp r3, #0 @ Fail to resolve?
3054 bne MterpException @ bail out
3055 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
3056 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
3057 GET_INST_OPCODE ip @ extract opcode from rINST
3058 GOTO_OPCODE ip @ jump to next instruction
3059
3060/* ------------------------------ */
3061 .balign 128
3062.L_op_sget_object: /* 0x62 */
3063/* File: arm/op_sget_object.S */
3064/* File: arm/op_sget.S */
3065 /*
3066 * General SGET handler wrapper.
3067 *
3068 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3069 */
3070 /* op vAA, field@BBBB */
3071
3072 .extern artGetObjStaticFromCode
3073 EXPORT_PC
3074 FETCH r0, 1 @ r0<- field ref BBBB
3075 ldr r1, [rFP, #OFF_FP_METHOD]
3076 mov r2, rSELF
3077 bl artGetObjStaticFromCode
3078 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
3079 mov r2, rINST, lsr #8 @ r2<- AA
3080 PREFETCH_INST 2
3081 cmp r3, #0 @ Fail to resolve?
3082 bne MterpException @ bail out
3083.if 1
3084 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0
3085.else
3086 SET_VREG r0, r2 @ fp[AA]<- r0
3087.endif
3088 ADVANCE 2
3089 GET_INST_OPCODE ip @ extract opcode from rINST
3090 GOTO_OPCODE ip
3091
3092
3093/* ------------------------------ */
3094 .balign 128
3095.L_op_sget_boolean: /* 0x63 */
3096/* File: arm/op_sget_boolean.S */
3097/* File: arm/op_sget.S */
3098 /*
3099 * General SGET handler wrapper.
3100 *
3101 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3102 */
3103 /* op vAA, field@BBBB */
3104
3105 .extern artGetBooleanStaticFromCode
3106 EXPORT_PC
3107 FETCH r0, 1 @ r0<- field ref BBBB
3108 ldr r1, [rFP, #OFF_FP_METHOD]
3109 mov r2, rSELF
3110 bl artGetBooleanStaticFromCode
3111 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
3112 mov r2, rINST, lsr #8 @ r2<- AA
3113 PREFETCH_INST 2
3114 cmp r3, #0 @ Fail to resolve?
3115 bne MterpException @ bail out
3116.if 0
3117 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0
3118.else
3119 SET_VREG r0, r2 @ fp[AA]<- r0
3120.endif
3121 ADVANCE 2
3122 GET_INST_OPCODE ip @ extract opcode from rINST
3123 GOTO_OPCODE ip
3124
3125
3126/* ------------------------------ */
3127 .balign 128
3128.L_op_sget_byte: /* 0x64 */
3129/* File: arm/op_sget_byte.S */
3130/* File: arm/op_sget.S */
3131 /*
3132 * General SGET handler wrapper.
3133 *
3134 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3135 */
3136 /* op vAA, field@BBBB */
3137
3138 .extern artGetByteStaticFromCode
3139 EXPORT_PC
3140 FETCH r0, 1 @ r0<- field ref BBBB
3141 ldr r1, [rFP, #OFF_FP_METHOD]
3142 mov r2, rSELF
3143 bl artGetByteStaticFromCode
3144 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
3145 mov r2, rINST, lsr #8 @ r2<- AA
3146 PREFETCH_INST 2
3147 cmp r3, #0 @ Fail to resolve?
3148 bne MterpException @ bail out
3149.if 0
3150 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0
3151.else
3152 SET_VREG r0, r2 @ fp[AA]<- r0
3153.endif
3154 ADVANCE 2
3155 GET_INST_OPCODE ip @ extract opcode from rINST
3156 GOTO_OPCODE ip
3157
3158
3159/* ------------------------------ */
3160 .balign 128
3161.L_op_sget_char: /* 0x65 */
3162/* File: arm/op_sget_char.S */
3163/* File: arm/op_sget.S */
3164 /*
3165 * General SGET handler wrapper.
3166 *
3167 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3168 */
3169 /* op vAA, field@BBBB */
3170
3171 .extern artGetCharStaticFromCode
3172 EXPORT_PC
3173 FETCH r0, 1 @ r0<- field ref BBBB
3174 ldr r1, [rFP, #OFF_FP_METHOD]
3175 mov r2, rSELF
3176 bl artGetCharStaticFromCode
3177 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
3178 mov r2, rINST, lsr #8 @ r2<- AA
3179 PREFETCH_INST 2
3180 cmp r3, #0 @ Fail to resolve?
3181 bne MterpException @ bail out
3182.if 0
3183 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0
3184.else
3185 SET_VREG r0, r2 @ fp[AA]<- r0
3186.endif
3187 ADVANCE 2
3188 GET_INST_OPCODE ip @ extract opcode from rINST
3189 GOTO_OPCODE ip
3190
3191
3192/* ------------------------------ */
3193 .balign 128
3194.L_op_sget_short: /* 0x66 */
3195/* File: arm/op_sget_short.S */
3196/* File: arm/op_sget.S */
3197 /*
3198 * General SGET handler wrapper.
3199 *
3200 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3201 */
3202 /* op vAA, field@BBBB */
3203
3204 .extern artGetShortStaticFromCode
3205 EXPORT_PC
3206 FETCH r0, 1 @ r0<- field ref BBBB
3207 ldr r1, [rFP, #OFF_FP_METHOD]
3208 mov r2, rSELF
3209 bl artGetShortStaticFromCode
3210 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
3211 mov r2, rINST, lsr #8 @ r2<- AA
3212 PREFETCH_INST 2
3213 cmp r3, #0 @ Fail to resolve?
3214 bne MterpException @ bail out
3215.if 0
3216 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0
3217.else
3218 SET_VREG r0, r2 @ fp[AA]<- r0
3219.endif
3220 ADVANCE 2
3221 GET_INST_OPCODE ip @ extract opcode from rINST
3222 GOTO_OPCODE ip
3223
3224
3225/* ------------------------------ */
3226 .balign 128
3227.L_op_sput: /* 0x67 */
3228/* File: arm/op_sput.S */
3229 /*
3230 * General SPUT handler wrapper.
3231 *
3232 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3233 */
3234 /* op vAA, field@BBBB */
3235 EXPORT_PC
3236 FETCH r0, 1 @ r0<- field ref BBBB
3237 mov r3, rINST, lsr #8 @ r3<- AA
3238 GET_VREG r1, r3 @ r1<= fp[AA]
3239 ldr r2, [rFP, #OFF_FP_METHOD]
3240 mov r3, rSELF
3241 PREFETCH_INST 2 @ Get next inst, but don't advance rPC
3242 bl artSet32StaticFromCode
3243 cmp r0, #0 @ 0 on success, -1 on failure
3244 bne MterpException
3245 ADVANCE 2 @ Past exception point - now advance rPC
3246 GET_INST_OPCODE ip @ extract opcode from rINST
3247 GOTO_OPCODE ip @ jump to next instruction
3248
3249/* ------------------------------ */
3250 .balign 128
3251.L_op_sput_wide: /* 0x68 */
3252/* File: arm/op_sput_wide.S */
3253 /*
3254 * SPUT_WIDE handler wrapper.
3255 *
3256 */
3257 /* sput-wide vAA, field@BBBB */
3258 .extern artSet64IndirectStaticFromMterp
3259 EXPORT_PC
3260 FETCH r0, 1 @ r0<- field ref BBBB
3261 ldr r1, [rFP, #OFF_FP_METHOD]
3262 mov r2, rINST, lsr #8 @ r3<- AA
3263 add r2, rFP, r2, lsl #2
3264 mov r3, rSELF
3265 PREFETCH_INST 2 @ Get next inst, but don't advance rPC
3266 bl artSet64IndirectStaticFromMterp
3267 cmp r0, #0 @ 0 on success, -1 on failure
3268 bne MterpException
3269 ADVANCE 2 @ Past exception point - now advance rPC
3270 GET_INST_OPCODE ip @ extract opcode from rINST
3271 GOTO_OPCODE ip @ jump to next instruction
3272
3273/* ------------------------------ */
3274 .balign 128
3275.L_op_sput_object: /* 0x69 */
3276/* File: arm/op_sput_object.S */
3277 EXPORT_PC
3278 add r0, rFP, #OFF_FP_SHADOWFRAME
3279 mov r1, rPC
3280 mov r2, rINST
3281 mov r3, rSELF
3282 bl MterpSputObject
3283 cmp r0, #0
3284 beq MterpException
3285 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
3286 GET_INST_OPCODE ip @ extract opcode from rINST
3287 GOTO_OPCODE ip @ jump to next instruction
3288
3289/* ------------------------------ */
3290 .balign 128
3291.L_op_sput_boolean: /* 0x6a */
3292/* File: arm/op_sput_boolean.S */
3293/* File: arm/op_sput.S */
3294 /*
3295 * General SPUT handler wrapper.
3296 *
3297 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3298 */
3299 /* op vAA, field@BBBB */
3300 EXPORT_PC
3301 FETCH r0, 1 @ r0<- field ref BBBB
3302 mov r3, rINST, lsr #8 @ r3<- AA
3303 GET_VREG r1, r3 @ r1<= fp[AA]
3304 ldr r2, [rFP, #OFF_FP_METHOD]
3305 mov r3, rSELF
3306 PREFETCH_INST 2 @ Get next inst, but don't advance rPC
3307 bl artSet8StaticFromCode
3308 cmp r0, #0 @ 0 on success, -1 on failure
3309 bne MterpException
3310 ADVANCE 2 @ Past exception point - now advance rPC
3311 GET_INST_OPCODE ip @ extract opcode from rINST
3312 GOTO_OPCODE ip @ jump to next instruction
3313
3314
3315/* ------------------------------ */
3316 .balign 128
3317.L_op_sput_byte: /* 0x6b */
3318/* File: arm/op_sput_byte.S */
3319/* File: arm/op_sput.S */
3320 /*
3321 * General SPUT handler wrapper.
3322 *
3323 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3324 */
3325 /* op vAA, field@BBBB */
3326 EXPORT_PC
3327 FETCH r0, 1 @ r0<- field ref BBBB
3328 mov r3, rINST, lsr #8 @ r3<- AA
3329 GET_VREG r1, r3 @ r1<= fp[AA]
3330 ldr r2, [rFP, #OFF_FP_METHOD]
3331 mov r3, rSELF
3332 PREFETCH_INST 2 @ Get next inst, but don't advance rPC
3333 bl artSet8StaticFromCode
3334 cmp r0, #0 @ 0 on success, -1 on failure
3335 bne MterpException
3336 ADVANCE 2 @ Past exception point - now advance rPC
3337 GET_INST_OPCODE ip @ extract opcode from rINST
3338 GOTO_OPCODE ip @ jump to next instruction
3339
3340
3341/* ------------------------------ */
3342 .balign 128
3343.L_op_sput_char: /* 0x6c */
3344/* File: arm/op_sput_char.S */
3345/* File: arm/op_sput.S */
3346 /*
3347 * General SPUT handler wrapper.
3348 *
3349 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3350 */
3351 /* op vAA, field@BBBB */
3352 EXPORT_PC
3353 FETCH r0, 1 @ r0<- field ref BBBB
3354 mov r3, rINST, lsr #8 @ r3<- AA
3355 GET_VREG r1, r3 @ r1<= fp[AA]
3356 ldr r2, [rFP, #OFF_FP_METHOD]
3357 mov r3, rSELF
3358 PREFETCH_INST 2 @ Get next inst, but don't advance rPC
3359 bl artSet16StaticFromCode
3360 cmp r0, #0 @ 0 on success, -1 on failure
3361 bne MterpException
3362 ADVANCE 2 @ Past exception point - now advance rPC
3363 GET_INST_OPCODE ip @ extract opcode from rINST
3364 GOTO_OPCODE ip @ jump to next instruction
3365
3366
3367/* ------------------------------ */
3368 .balign 128
3369.L_op_sput_short: /* 0x6d */
3370/* File: arm/op_sput_short.S */
3371/* File: arm/op_sput.S */
3372 /*
3373 * General SPUT handler wrapper.
3374 *
3375 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3376 */
3377 /* op vAA, field@BBBB */
3378 EXPORT_PC
3379 FETCH r0, 1 @ r0<- field ref BBBB
3380 mov r3, rINST, lsr #8 @ r3<- AA
3381 GET_VREG r1, r3 @ r1<= fp[AA]
3382 ldr r2, [rFP, #OFF_FP_METHOD]
3383 mov r3, rSELF
3384 PREFETCH_INST 2 @ Get next inst, but don't advance rPC
3385 bl artSet16StaticFromCode
3386 cmp r0, #0 @ 0 on success, -1 on failure
3387 bne MterpException
3388 ADVANCE 2 @ Past exception point - now advance rPC
3389 GET_INST_OPCODE ip @ extract opcode from rINST
3390 GOTO_OPCODE ip @ jump to next instruction
3391
3392
3393/* ------------------------------ */
3394 .balign 128
3395.L_op_invoke_virtual: /* 0x6e */
3396/* File: arm/op_invoke_virtual.S */
3397/* File: arm/invoke.S */
3398 /*
3399 * Generic invoke handler wrapper.
3400 */
3401 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3402 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3403 .extern MterpInvokeVirtual
3404 EXPORT_PC
3405 mov r0, rSELF
3406 add r1, rFP, #OFF_FP_SHADOWFRAME
3407 mov r2, rPC
3408 mov r3, rINST
3409 bl MterpInvokeVirtual
3410 cmp r0, #0
3411 beq MterpException
3412 FETCH_ADVANCE_INST 3
3413 GET_INST_OPCODE ip
3414 GOTO_OPCODE ip
3415
3416
3417 /*
3418 * Handle a virtual method call.
3419 *
3420 * for: invoke-virtual, invoke-virtual/range
3421 */
3422 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3423 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3424
3425/* ------------------------------ */
3426 .balign 128
3427.L_op_invoke_super: /* 0x6f */
3428/* File: arm/op_invoke_super.S */
3429/* File: arm/invoke.S */
3430 /*
3431 * Generic invoke handler wrapper.
3432 */
3433 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3434 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3435 .extern MterpInvokeSuper
3436 EXPORT_PC
3437 mov r0, rSELF
3438 add r1, rFP, #OFF_FP_SHADOWFRAME
3439 mov r2, rPC
3440 mov r3, rINST
3441 bl MterpInvokeSuper
3442 cmp r0, #0
3443 beq MterpException
3444 FETCH_ADVANCE_INST 3
3445 GET_INST_OPCODE ip
3446 GOTO_OPCODE ip
3447
3448
3449 /*
3450 * Handle a "super" method call.
3451 *
3452 * for: invoke-super, invoke-super/range
3453 */
3454 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3455 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3456
3457/* ------------------------------ */
3458 .balign 128
3459.L_op_invoke_direct: /* 0x70 */
3460/* File: arm/op_invoke_direct.S */
3461/* File: arm/invoke.S */
3462 /*
3463 * Generic invoke handler wrapper.
3464 */
3465 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3466 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3467 .extern MterpInvokeDirect
3468 EXPORT_PC
3469 mov r0, rSELF
3470 add r1, rFP, #OFF_FP_SHADOWFRAME
3471 mov r2, rPC
3472 mov r3, rINST
3473 bl MterpInvokeDirect
3474 cmp r0, #0
3475 beq MterpException
3476 FETCH_ADVANCE_INST 3
3477 GET_INST_OPCODE ip
3478 GOTO_OPCODE ip
3479
3480
3481
3482/* ------------------------------ */
3483 .balign 128
3484.L_op_invoke_static: /* 0x71 */
3485/* File: arm/op_invoke_static.S */
3486/* File: arm/invoke.S */
3487 /*
3488 * Generic invoke handler wrapper.
3489 */
3490 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3491 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3492 .extern MterpInvokeStatic
3493 EXPORT_PC
3494 mov r0, rSELF
3495 add r1, rFP, #OFF_FP_SHADOWFRAME
3496 mov r2, rPC
3497 mov r3, rINST
3498 bl MterpInvokeStatic
3499 cmp r0, #0
3500 beq MterpException
3501 FETCH_ADVANCE_INST 3
3502 GET_INST_OPCODE ip
3503 GOTO_OPCODE ip
3504
3505
3506
3507
3508/* ------------------------------ */
3509 .balign 128
3510.L_op_invoke_interface: /* 0x72 */
3511/* File: arm/op_invoke_interface.S */
3512/* File: arm/invoke.S */
3513 /*
3514 * Generic invoke handler wrapper.
3515 */
3516 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3517 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3518 .extern MterpInvokeInterface
3519 EXPORT_PC
3520 mov r0, rSELF
3521 add r1, rFP, #OFF_FP_SHADOWFRAME
3522 mov r2, rPC
3523 mov r3, rINST
3524 bl MterpInvokeInterface
3525 cmp r0, #0
3526 beq MterpException
3527 FETCH_ADVANCE_INST 3
3528 GET_INST_OPCODE ip
3529 GOTO_OPCODE ip
3530
3531
3532 /*
3533 * Handle an interface method call.
3534 *
3535 * for: invoke-interface, invoke-interface/range
3536 */
3537 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3538 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3539
3540/* ------------------------------ */
3541 .balign 128
3542.L_op_return_void_no_barrier: /* 0x73 */
3543/* File: arm/op_return_void_no_barrier.S */
buzbeea2c97a92016-01-25 15:41:24 -0800[diff] [blame]3544 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
3545 mov r0, rSELF
3546 ands lr, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
3547 blne MterpSuspendCheck @ (self)
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]3548 mov r0, #0
3549 mov r1, #0
3550 b MterpReturn
3551
3552/* ------------------------------ */
3553 .balign 128
3554.L_op_invoke_virtual_range: /* 0x74 */
3555/* File: arm/op_invoke_virtual_range.S */
3556/* File: arm/invoke.S */
3557 /*
3558 * Generic invoke handler wrapper.
3559 */
3560 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3561 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3562 .extern MterpInvokeVirtualRange
3563 EXPORT_PC
3564 mov r0, rSELF
3565 add r1, rFP, #OFF_FP_SHADOWFRAME
3566 mov r2, rPC
3567 mov r3, rINST
3568 bl MterpInvokeVirtualRange
3569 cmp r0, #0
3570 beq MterpException
3571 FETCH_ADVANCE_INST 3
3572 GET_INST_OPCODE ip
3573 GOTO_OPCODE ip
3574
3575
3576
3577/* ------------------------------ */
3578 .balign 128
3579.L_op_invoke_super_range: /* 0x75 */
3580/* File: arm/op_invoke_super_range.S */
3581/* File: arm/invoke.S */
3582 /*
3583 * Generic invoke handler wrapper.
3584 */
3585 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3586 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3587 .extern MterpInvokeSuperRange
3588 EXPORT_PC
3589 mov r0, rSELF
3590 add r1, rFP, #OFF_FP_SHADOWFRAME
3591 mov r2, rPC
3592 mov r3, rINST
3593 bl MterpInvokeSuperRange
3594 cmp r0, #0
3595 beq MterpException
3596 FETCH_ADVANCE_INST 3
3597 GET_INST_OPCODE ip
3598 GOTO_OPCODE ip
3599
3600
3601
3602/* ------------------------------ */
3603 .balign 128
3604.L_op_invoke_direct_range: /* 0x76 */
3605/* File: arm/op_invoke_direct_range.S */
3606/* File: arm/invoke.S */
3607 /*
3608 * Generic invoke handler wrapper.
3609 */
3610 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3611 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3612 .extern MterpInvokeDirectRange
3613 EXPORT_PC
3614 mov r0, rSELF
3615 add r1, rFP, #OFF_FP_SHADOWFRAME
3616 mov r2, rPC
3617 mov r3, rINST
3618 bl MterpInvokeDirectRange
3619 cmp r0, #0
3620 beq MterpException
3621 FETCH_ADVANCE_INST 3
3622 GET_INST_OPCODE ip
3623 GOTO_OPCODE ip
3624
3625
3626
3627/* ------------------------------ */
3628 .balign 128
3629.L_op_invoke_static_range: /* 0x77 */
3630/* File: arm/op_invoke_static_range.S */
3631/* File: arm/invoke.S */
3632 /*
3633 * Generic invoke handler wrapper.
3634 */
3635 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3636 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3637 .extern MterpInvokeStaticRange
3638 EXPORT_PC
3639 mov r0, rSELF
3640 add r1, rFP, #OFF_FP_SHADOWFRAME
3641 mov r2, rPC
3642 mov r3, rINST
3643 bl MterpInvokeStaticRange
3644 cmp r0, #0
3645 beq MterpException
3646 FETCH_ADVANCE_INST 3
3647 GET_INST_OPCODE ip
3648 GOTO_OPCODE ip
3649
3650
3651
3652/* ------------------------------ */
3653 .balign 128
3654.L_op_invoke_interface_range: /* 0x78 */
3655/* File: arm/op_invoke_interface_range.S */
3656/* File: arm/invoke.S */
3657 /*
3658 * Generic invoke handler wrapper.
3659 */
3660 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3661 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3662 .extern MterpInvokeInterfaceRange
3663 EXPORT_PC
3664 mov r0, rSELF
3665 add r1, rFP, #OFF_FP_SHADOWFRAME
3666 mov r2, rPC
3667 mov r3, rINST
3668 bl MterpInvokeInterfaceRange
3669 cmp r0, #0
3670 beq MterpException
3671 FETCH_ADVANCE_INST 3
3672 GET_INST_OPCODE ip
3673 GOTO_OPCODE ip
3674
3675
3676
3677/* ------------------------------ */
3678 .balign 128
3679.L_op_unused_79: /* 0x79 */
3680/* File: arm/op_unused_79.S */
3681/* File: arm/unused.S */
3682/*
3683 * Bail to reference interpreter to throw.
3684 */
3685 b MterpFallback
3686
3687
3688/* ------------------------------ */
3689 .balign 128
3690.L_op_unused_7a: /* 0x7a */
3691/* File: arm/op_unused_7a.S */
3692/* File: arm/unused.S */
3693/*
3694 * Bail to reference interpreter to throw.
3695 */
3696 b MterpFallback
3697
3698
3699/* ------------------------------ */
3700 .balign 128
3701.L_op_neg_int: /* 0x7b */
3702/* File: arm/op_neg_int.S */
3703/* File: arm/unop.S */
3704 /*
3705 * Generic 32-bit unary operation. Provide an "instr" line that
3706 * specifies an instruction that performs "result = op r0".
3707 * This could be an ARM instruction or a function call.
3708 *
3709 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3710 * int-to-byte, int-to-char, int-to-short
3711 */
3712 /* unop vA, vB */
3713 mov r3, rINST, lsr #12 @ r3<- B
3714 ubfx r9, rINST, #8, #4 @ r9<- A
3715 GET_VREG r0, r3 @ r0<- vB
3716 @ optional op; may set condition codes
3717 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3718 rsb r0, r0, #0 @ r0<- op, r0-r3 changed
3719 GET_INST_OPCODE ip @ extract opcode from rINST
3720 SET_VREG r0, r9 @ vAA<- r0
3721 GOTO_OPCODE ip @ jump to next instruction
3722 /* 8-9 instructions */
3723
3724
3725/* ------------------------------ */
3726 .balign 128
3727.L_op_not_int: /* 0x7c */
3728/* File: arm/op_not_int.S */
3729/* File: arm/unop.S */
3730 /*
3731 * Generic 32-bit unary operation. Provide an "instr" line that
3732 * specifies an instruction that performs "result = op r0".
3733 * This could be an ARM instruction or a function call.
3734 *
3735 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3736 * int-to-byte, int-to-char, int-to-short
3737 */
3738 /* unop vA, vB */
3739 mov r3, rINST, lsr #12 @ r3<- B
3740 ubfx r9, rINST, #8, #4 @ r9<- A
3741 GET_VREG r0, r3 @ r0<- vB
3742 @ optional op; may set condition codes
3743 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3744 mvn r0, r0 @ r0<- op, r0-r3 changed
3745 GET_INST_OPCODE ip @ extract opcode from rINST
3746 SET_VREG r0, r9 @ vAA<- r0
3747 GOTO_OPCODE ip @ jump to next instruction
3748 /* 8-9 instructions */
3749
3750
3751/* ------------------------------ */
3752 .balign 128
3753.L_op_neg_long: /* 0x7d */
3754/* File: arm/op_neg_long.S */
3755/* File: arm/unopWide.S */
3756 /*
3757 * Generic 64-bit unary operation. Provide an "instr" line that
3758 * specifies an instruction that performs "result = op r0/r1".
3759 * This could be an ARM instruction or a function call.
3760 *
3761 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3762 */
3763 /* unop vA, vB */
3764 mov r3, rINST, lsr #12 @ r3<- B
3765 ubfx r9, rINST, #8, #4 @ r9<- A
3766 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3767 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3768 ldmia r3, {r0-r1} @ r0/r1<- vAA
3769 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3770 rsbs r0, r0, #0 @ optional op; may set condition codes
3771 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed
3772 GET_INST_OPCODE ip @ extract opcode from rINST
3773 stmia r9, {r0-r1} @ vAA<- r0/r1
3774 GOTO_OPCODE ip @ jump to next instruction
3775 /* 10-11 instructions */
3776
3777
3778/* ------------------------------ */
3779 .balign 128
3780.L_op_not_long: /* 0x7e */
3781/* File: arm/op_not_long.S */
3782/* File: arm/unopWide.S */
3783 /*
3784 * Generic 64-bit unary operation. Provide an "instr" line that
3785 * specifies an instruction that performs "result = op r0/r1".
3786 * This could be an ARM instruction or a function call.
3787 *
3788 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3789 */
3790 /* unop vA, vB */
3791 mov r3, rINST, lsr #12 @ r3<- B
3792 ubfx r9, rINST, #8, #4 @ r9<- A
3793 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3794 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3795 ldmia r3, {r0-r1} @ r0/r1<- vAA
3796 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3797 mvn r0, r0 @ optional op; may set condition codes
3798 mvn r1, r1 @ r0/r1<- op, r2-r3 changed
3799 GET_INST_OPCODE ip @ extract opcode from rINST
3800 stmia r9, {r0-r1} @ vAA<- r0/r1
3801 GOTO_OPCODE ip @ jump to next instruction
3802 /* 10-11 instructions */
3803
3804
3805/* ------------------------------ */
3806 .balign 128
3807.L_op_neg_float: /* 0x7f */
3808/* File: arm/op_neg_float.S */
3809/* File: arm/unop.S */
3810 /*
3811 * Generic 32-bit unary operation. Provide an "instr" line that
3812 * specifies an instruction that performs "result = op r0".
3813 * This could be an ARM instruction or a function call.
3814 *
3815 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3816 * int-to-byte, int-to-char, int-to-short
3817 */
3818 /* unop vA, vB */
3819 mov r3, rINST, lsr #12 @ r3<- B
3820 ubfx r9, rINST, #8, #4 @ r9<- A
3821 GET_VREG r0, r3 @ r0<- vB
3822 @ optional op; may set condition codes
3823 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3824 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed
3825 GET_INST_OPCODE ip @ extract opcode from rINST
3826 SET_VREG r0, r9 @ vAA<- r0
3827 GOTO_OPCODE ip @ jump to next instruction
3828 /* 8-9 instructions */
3829
3830
3831/* ------------------------------ */
3832 .balign 128
3833.L_op_neg_double: /* 0x80 */
3834/* File: arm/op_neg_double.S */
3835/* File: arm/unopWide.S */
3836 /*
3837 * Generic 64-bit unary operation. Provide an "instr" line that
3838 * specifies an instruction that performs "result = op r0/r1".
3839 * This could be an ARM instruction or a function call.
3840 *
3841 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3842 */
3843 /* unop vA, vB */
3844 mov r3, rINST, lsr #12 @ r3<- B
3845 ubfx r9, rINST, #8, #4 @ r9<- A
3846 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3847 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3848 ldmia r3, {r0-r1} @ r0/r1<- vAA
3849 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3850 @ optional op; may set condition codes
3851 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed
3852 GET_INST_OPCODE ip @ extract opcode from rINST
3853 stmia r9, {r0-r1} @ vAA<- r0/r1
3854 GOTO_OPCODE ip @ jump to next instruction
3855 /* 10-11 instructions */
3856
3857
3858/* ------------------------------ */
3859 .balign 128
3860.L_op_int_to_long: /* 0x81 */
3861/* File: arm/op_int_to_long.S */
3862/* File: arm/unopWider.S */
3863 /*
3864 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3865 * that specifies an instruction that performs "result = op r0", where
3866 * "result" is a 64-bit quantity in r0/r1.
3867 *
3868 * For: int-to-long, int-to-double, float-to-long, float-to-double
3869 */
3870 /* unop vA, vB */
3871 mov r3, rINST, lsr #12 @ r3<- B
3872 ubfx r9, rINST, #8, #4 @ r9<- A
3873 GET_VREG r0, r3 @ r0<- vB
3874 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3875 @ optional op; may set condition codes
3876 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3877 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed
3878 GET_INST_OPCODE ip @ extract opcode from rINST
3879 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3880 GOTO_OPCODE ip @ jump to next instruction
3881 /* 9-10 instructions */
3882
3883
3884/* ------------------------------ */
3885 .balign 128
3886.L_op_int_to_float: /* 0x82 */
3887/* File: arm/op_int_to_float.S */
3888/* File: arm/funop.S */
3889 /*
3890 * Generic 32-bit unary floating-point operation. Provide an "instr"
3891 * line that specifies an instruction that performs "s1 = op s0".
3892 *
3893 * for: int-to-float, float-to-int
3894 */
3895 /* unop vA, vB */
3896 mov r3, rINST, lsr #12 @ r3<- B
3897 mov r9, rINST, lsr #8 @ r9<- A+
3898 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
3899 flds s0, [r3] @ s0<- vB
3900 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3901 and r9, r9, #15 @ r9<- A
3902 fsitos s1, s0 @ s1<- op
3903 GET_INST_OPCODE ip @ extract opcode from rINST
3904 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
3905 fsts s1, [r9] @ vA<- s1
3906 GOTO_OPCODE ip @ jump to next instruction
3907
3908
3909/* ------------------------------ */
3910 .balign 128
3911.L_op_int_to_double: /* 0x83 */
3912/* File: arm/op_int_to_double.S */
3913/* File: arm/funopWider.S */
3914 /*
3915 * Generic 32bit-to-64bit floating point unary operation. Provide an
3916 * "instr" line that specifies an instruction that performs "d0 = op s0".
3917 *
3918 * For: int-to-double, float-to-double
3919 */
3920 /* unop vA, vB */
3921 mov r3, rINST, lsr #12 @ r3<- B
3922 mov r9, rINST, lsr #8 @ r9<- A+
3923 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
3924 flds s0, [r3] @ s0<- vB
3925 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3926 and r9, r9, #15 @ r9<- A
3927 fsitod d0, s0 @ d0<- op
3928 GET_INST_OPCODE ip @ extract opcode from rINST
3929 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
3930 fstd d0, [r9] @ vA<- d0
3931 GOTO_OPCODE ip @ jump to next instruction
3932
3933
3934/* ------------------------------ */
3935 .balign 128
3936.L_op_long_to_int: /* 0x84 */
3937/* File: arm/op_long_to_int.S */
3938/* we ignore the high word, making this equivalent to a 32-bit reg move */
3939/* File: arm/op_move.S */
3940 /* for move, move-object, long-to-int */
3941 /* op vA, vB */
3942 mov r1, rINST, lsr #12 @ r1<- B from 15:12
3943 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8
3944 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3945 GET_VREG r2, r1 @ r2<- fp[B]
3946 GET_INST_OPCODE ip @ ip<- opcode from rINST
3947 .if 0
3948 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2
3949 .else
3950 SET_VREG r2, r0 @ fp[A]<- r2
3951 .endif
3952 GOTO_OPCODE ip @ execute next instruction
3953
3954
3955/* ------------------------------ */
3956 .balign 128
3957.L_op_long_to_float: /* 0x85 */
3958/* File: arm/op_long_to_float.S */
3959/* File: arm/unopNarrower.S */
3960 /*
3961 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
3962 * that specifies an instruction that performs "result = op r0/r1", where
3963 * "result" is a 32-bit quantity in r0.
3964 *
3965 * For: long-to-float, double-to-int, double-to-float
3966 *
3967 * (This would work for long-to-int, but that instruction is actually
3968 * an exact match for op_move.)
3969 */
3970 /* unop vA, vB */
3971 mov r3, rINST, lsr #12 @ r3<- B
3972 ubfx r9, rINST, #8, #4 @ r9<- A
3973 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3974 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1
3975 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
3976 @ optional op; may set condition codes
3977 bl __aeabi_l2f @ r0<- op, r0-r3 changed
3978 GET_INST_OPCODE ip @ extract opcode from rINST
3979 SET_VREG r0, r9 @ vA<- r0
3980 GOTO_OPCODE ip @ jump to next instruction
3981 /* 9-10 instructions */
3982
3983
3984/* ------------------------------ */
3985 .balign 128
3986.L_op_long_to_double: /* 0x86 */
3987/* File: arm/op_long_to_double.S */
3988 /*
3989 * Specialised 64-bit floating point operation.
3990 *
3991 * Note: The result will be returned in d2.
3992 *
3993 * For: long-to-double
3994 */
3995 mov r3, rINST, lsr #12 @ r3<- B
3996 ubfx r9, rINST, #8, #4 @ r9<- A
3997 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3998 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3999 vldr d0, [r3] @ d0<- vAA
4000 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4001
4002 vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh)
4003 vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl)
4004 vldr d3, constvalop_long_to_double
4005 vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl
4006
4007 GET_INST_OPCODE ip @ extract opcode from rINST
4008 vstr.64 d2, [r9] @ vAA<- d2
4009 GOTO_OPCODE ip @ jump to next instruction
4010
4011 /* literal pool helper */
4012constvalop_long_to_double:
4013 .8byte 0x41f0000000000000
4014
4015/* ------------------------------ */
4016 .balign 128
4017.L_op_float_to_int: /* 0x87 */
4018/* File: arm/op_float_to_int.S */
4019/* File: arm/funop.S */
4020 /*
4021 * Generic 32-bit unary floating-point operation. Provide an "instr"
4022 * line that specifies an instruction that performs "s1 = op s0".
4023 *
4024 * for: int-to-float, float-to-int
4025 */
4026 /* unop vA, vB */
4027 mov r3, rINST, lsr #12 @ r3<- B
4028 mov r9, rINST, lsr #8 @ r9<- A+
4029 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
4030 flds s0, [r3] @ s0<- vB
4031 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4032 and r9, r9, #15 @ r9<- A
4033 ftosizs s1, s0 @ s1<- op
4034 GET_INST_OPCODE ip @ extract opcode from rINST
4035 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
4036 fsts s1, [r9] @ vA<- s1
4037 GOTO_OPCODE ip @ jump to next instruction
4038
4039
4040/* ------------------------------ */
4041 .balign 128
4042.L_op_float_to_long: /* 0x88 */
4043/* File: arm/op_float_to_long.S */
4044@include "arm/unopWider.S" {"instr":"bl __aeabi_f2lz"}
4045/* File: arm/unopWider.S */
4046 /*
4047 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
4048 * that specifies an instruction that performs "result = op r0", where
4049 * "result" is a 64-bit quantity in r0/r1.
4050 *
4051 * For: int-to-long, int-to-double, float-to-long, float-to-double
4052 */
4053 /* unop vA, vB */
4054 mov r3, rINST, lsr #12 @ r3<- B
4055 ubfx r9, rINST, #8, #4 @ r9<- A
4056 GET_VREG r0, r3 @ r0<- vB
4057 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
4058 @ optional op; may set condition codes
4059 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4060 bl f2l_doconv @ r0<- op, r0-r3 changed
4061 GET_INST_OPCODE ip @ extract opcode from rINST
4062 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
4063 GOTO_OPCODE ip @ jump to next instruction
4064 /* 9-10 instructions */
4065
4066
4067
4068/* ------------------------------ */
4069 .balign 128
4070.L_op_float_to_double: /* 0x89 */
4071/* File: arm/op_float_to_double.S */
4072/* File: arm/funopWider.S */
4073 /*
4074 * Generic 32bit-to-64bit floating point unary operation. Provide an
4075 * "instr" line that specifies an instruction that performs "d0 = op s0".
4076 *
4077 * For: int-to-double, float-to-double
4078 */
4079 /* unop vA, vB */
4080 mov r3, rINST, lsr #12 @ r3<- B
4081 mov r9, rINST, lsr #8 @ r9<- A+
4082 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
4083 flds s0, [r3] @ s0<- vB
4084 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4085 and r9, r9, #15 @ r9<- A
4086 fcvtds d0, s0 @ d0<- op
4087 GET_INST_OPCODE ip @ extract opcode from rINST
4088 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
4089 fstd d0, [r9] @ vA<- d0
4090 GOTO_OPCODE ip @ jump to next instruction
4091
4092
4093/* ------------------------------ */
4094 .balign 128
4095.L_op_double_to_int: /* 0x8a */
4096/* File: arm/op_double_to_int.S */
4097/* File: arm/funopNarrower.S */
4098 /*
4099 * Generic 64bit-to-32bit unary floating point operation. Provide an
4100 * "instr" line that specifies an instruction that performs "s0 = op d0".
4101 *
4102 * For: double-to-int, double-to-float
4103 */
4104 /* unop vA, vB */
4105 mov r3, rINST, lsr #12 @ r3<- B
4106 mov r9, rINST, lsr #8 @ r9<- A+
4107 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
4108 fldd d0, [r3] @ d0<- vB
4109 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4110 and r9, r9, #15 @ r9<- A
4111 ftosizd s0, d0 @ s0<- op
4112 GET_INST_OPCODE ip @ extract opcode from rINST
4113 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
4114 fsts s0, [r9] @ vA<- s0
4115 GOTO_OPCODE ip @ jump to next instruction
4116
4117
4118/* ------------------------------ */
4119 .balign 128
4120.L_op_double_to_long: /* 0x8b */
4121/* File: arm/op_double_to_long.S */
4122@include "arm/unopWide.S" {"instr":"bl __aeabi_d2lz"}
4123/* File: arm/unopWide.S */
4124 /*
4125 * Generic 64-bit unary operation. Provide an "instr" line that
4126 * specifies an instruction that performs "result = op r0/r1".
4127 * This could be an ARM instruction or a function call.
4128 *
4129 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
4130 */
4131 /* unop vA, vB */
4132 mov r3, rINST, lsr #12 @ r3<- B
4133 ubfx r9, rINST, #8, #4 @ r9<- A
4134 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
4135 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
4136 ldmia r3, {r0-r1} @ r0/r1<- vAA
4137 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4138 @ optional op; may set condition codes
4139 bl d2l_doconv @ r0/r1<- op, r2-r3 changed
4140 GET_INST_OPCODE ip @ extract opcode from rINST
4141 stmia r9, {r0-r1} @ vAA<- r0/r1
4142 GOTO_OPCODE ip @ jump to next instruction
4143 /* 10-11 instructions */
4144
4145
4146
4147/* ------------------------------ */
4148 .balign 128
4149.L_op_double_to_float: /* 0x8c */
4150/* File: arm/op_double_to_float.S */
4151/* File: arm/funopNarrower.S */
4152 /*
4153 * Generic 64bit-to-32bit unary floating point operation. Provide an
4154 * "instr" line that specifies an instruction that performs "s0 = op d0".
4155 *
4156 * For: double-to-int, double-to-float
4157 */
4158 /* unop vA, vB */
4159 mov r3, rINST, lsr #12 @ r3<- B
4160 mov r9, rINST, lsr #8 @ r9<- A+
4161 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
4162 fldd d0, [r3] @ d0<- vB
4163 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4164 and r9, r9, #15 @ r9<- A
4165 fcvtsd s0, d0 @ s0<- op
4166 GET_INST_OPCODE ip @ extract opcode from rINST
4167 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
4168 fsts s0, [r9] @ vA<- s0
4169 GOTO_OPCODE ip @ jump to next instruction
4170
4171
4172/* ------------------------------ */
4173 .balign 128
4174.L_op_int_to_byte: /* 0x8d */
4175/* File: arm/op_int_to_byte.S */
4176/* File: arm/unop.S */
4177 /*
4178 * Generic 32-bit unary operation. Provide an "instr" line that
4179 * specifies an instruction that performs "result = op r0".
4180 * This could be an ARM instruction or a function call.
4181 *
4182 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
4183 * int-to-byte, int-to-char, int-to-short
4184 */
4185 /* unop vA, vB */
4186 mov r3, rINST, lsr #12 @ r3<- B
4187 ubfx r9, rINST, #8, #4 @ r9<- A
4188 GET_VREG r0, r3 @ r0<- vB
4189 @ optional op; may set condition codes
4190 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4191 sxtb r0, r0 @ r0<- op, r0-r3 changed
4192 GET_INST_OPCODE ip @ extract opcode from rINST
4193 SET_VREG r0, r9 @ vAA<- r0
4194 GOTO_OPCODE ip @ jump to next instruction
4195 /* 8-9 instructions */
4196
4197
4198/* ------------------------------ */
4199 .balign 128
4200.L_op_int_to_char: /* 0x8e */
4201/* File: arm/op_int_to_char.S */
4202/* File: arm/unop.S */
4203 /*
4204 * Generic 32-bit unary operation. Provide an "instr" line that
4205 * specifies an instruction that performs "result = op r0".
4206 * This could be an ARM instruction or a function call.
4207 *
4208 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
4209 * int-to-byte, int-to-char, int-to-short
4210 */
4211 /* unop vA, vB */
4212 mov r3, rINST, lsr #12 @ r3<- B
4213 ubfx r9, rINST, #8, #4 @ r9<- A
4214 GET_VREG r0, r3 @ r0<- vB
4215 @ optional op; may set condition codes
4216 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4217 uxth r0, r0 @ r0<- op, r0-r3 changed
4218 GET_INST_OPCODE ip @ extract opcode from rINST
4219 SET_VREG r0, r9 @ vAA<- r0
4220 GOTO_OPCODE ip @ jump to next instruction
4221 /* 8-9 instructions */
4222
4223
4224/* ------------------------------ */
4225 .balign 128
4226.L_op_int_to_short: /* 0x8f */
4227/* File: arm/op_int_to_short.S */
4228/* File: arm/unop.S */
4229 /*
4230 * Generic 32-bit unary operation. Provide an "instr" line that
4231 * specifies an instruction that performs "result = op r0".
4232 * This could be an ARM instruction or a function call.
4233 *
4234 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
4235 * int-to-byte, int-to-char, int-to-short
4236 */
4237 /* unop vA, vB */
4238 mov r3, rINST, lsr #12 @ r3<- B
4239 ubfx r9, rINST, #8, #4 @ r9<- A
4240 GET_VREG r0, r3 @ r0<- vB
4241 @ optional op; may set condition codes
4242 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
4243 sxth r0, r0 @ r0<- op, r0-r3 changed
4244 GET_INST_OPCODE ip @ extract opcode from rINST
4245 SET_VREG r0, r9 @ vAA<- r0
4246 GOTO_OPCODE ip @ jump to next instruction
4247 /* 8-9 instructions */
4248
4249
4250/* ------------------------------ */
4251 .balign 128
4252.L_op_add_int: /* 0x90 */
4253/* File: arm/op_add_int.S */
4254/* File: arm/binop.S */
4255 /*
4256 * Generic 32-bit binary operation. Provide an "instr" line that
4257 * specifies an instruction that performs "result = r0 op r1".
4258 * This could be an ARM instruction or a function call. (If the result
4259 * comes back in a register other than r0, you can override "result".)
4260 *
4261 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4262 * vCC (r1). Useful for integer division and modulus. Note that we
4263 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4264 * handles it correctly.
4265 *
4266 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4267 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4268 * mul-float, div-float, rem-float
4269 */
4270 /* binop vAA, vBB, vCC */
4271 FETCH r0, 1 @ r0<- CCBB
4272 mov r9, rINST, lsr #8 @ r9<- AA
4273 mov r3, r0, lsr #8 @ r3<- CC
4274 and r2, r0, #255 @ r2<- BB
4275 GET_VREG r1, r3 @ r1<- vCC
4276 GET_VREG r0, r2 @ r0<- vBB
4277 .if 0
4278 cmp r1, #0 @ is second operand zero?
4279 beq common_errDivideByZero
4280 .endif
4281
4282 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4283 @ optional op; may set condition codes
4284 add r0, r0, r1 @ r0<- op, r0-r3 changed
4285 GET_INST_OPCODE ip @ extract opcode from rINST
4286 SET_VREG r0, r9 @ vAA<- r0
4287 GOTO_OPCODE ip @ jump to next instruction
4288 /* 11-14 instructions */
4289
4290
4291/* ------------------------------ */
4292 .balign 128
4293.L_op_sub_int: /* 0x91 */
4294/* File: arm/op_sub_int.S */
4295/* File: arm/binop.S */
4296 /*
4297 * Generic 32-bit binary operation. Provide an "instr" line that
4298 * specifies an instruction that performs "result = r0 op r1".
4299 * This could be an ARM instruction or a function call. (If the result
4300 * comes back in a register other than r0, you can override "result".)
4301 *
4302 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4303 * vCC (r1). Useful for integer division and modulus. Note that we
4304 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4305 * handles it correctly.
4306 *
4307 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4308 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4309 * mul-float, div-float, rem-float
4310 */
4311 /* binop vAA, vBB, vCC */
4312 FETCH r0, 1 @ r0<- CCBB
4313 mov r9, rINST, lsr #8 @ r9<- AA
4314 mov r3, r0, lsr #8 @ r3<- CC
4315 and r2, r0, #255 @ r2<- BB
4316 GET_VREG r1, r3 @ r1<- vCC
4317 GET_VREG r0, r2 @ r0<- vBB
4318 .if 0
4319 cmp r1, #0 @ is second operand zero?
4320 beq common_errDivideByZero
4321 .endif
4322
4323 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4324 @ optional op; may set condition codes
4325 sub r0, r0, r1 @ r0<- op, r0-r3 changed
4326 GET_INST_OPCODE ip @ extract opcode from rINST
4327 SET_VREG r0, r9 @ vAA<- r0
4328 GOTO_OPCODE ip @ jump to next instruction
4329 /* 11-14 instructions */
4330
4331
4332/* ------------------------------ */
4333 .balign 128
4334.L_op_mul_int: /* 0x92 */
4335/* File: arm/op_mul_int.S */
4336/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
4337/* File: arm/binop.S */
4338 /*
4339 * Generic 32-bit binary operation. Provide an "instr" line that
4340 * specifies an instruction that performs "result = r0 op r1".
4341 * This could be an ARM instruction or a function call. (If the result
4342 * comes back in a register other than r0, you can override "result".)
4343 *
4344 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4345 * vCC (r1). Useful for integer division and modulus. Note that we
4346 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4347 * handles it correctly.
4348 *
4349 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4350 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4351 * mul-float, div-float, rem-float
4352 */
4353 /* binop vAA, vBB, vCC */
4354 FETCH r0, 1 @ r0<- CCBB
4355 mov r9, rINST, lsr #8 @ r9<- AA
4356 mov r3, r0, lsr #8 @ r3<- CC
4357 and r2, r0, #255 @ r2<- BB
4358 GET_VREG r1, r3 @ r1<- vCC
4359 GET_VREG r0, r2 @ r0<- vBB
4360 .if 0
4361 cmp r1, #0 @ is second operand zero?
4362 beq common_errDivideByZero
4363 .endif
4364
4365 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4366 @ optional op; may set condition codes
4367 mul r0, r1, r0 @ r0<- op, r0-r3 changed
4368 GET_INST_OPCODE ip @ extract opcode from rINST
4369 SET_VREG r0, r9 @ vAA<- r0
4370 GOTO_OPCODE ip @ jump to next instruction
4371 /* 11-14 instructions */
4372
4373
4374/* ------------------------------ */
4375 .balign 128
4376.L_op_div_int: /* 0x93 */
4377/* File: arm/op_div_int.S */
4378 /*
4379 * Specialized 32-bit binary operation
4380 *
4381 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
4382 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
4383 * ARMv7 CPUs that have hardware division support).
4384 *
4385 * div-int
4386 *
4387 */
4388 FETCH r0, 1 @ r0<- CCBB
4389 mov r9, rINST, lsr #8 @ r9<- AA
4390 mov r3, r0, lsr #8 @ r3<- CC
4391 and r2, r0, #255 @ r2<- BB
4392 GET_VREG r1, r3 @ r1<- vCC
4393 GET_VREG r0, r2 @ r0<- vBB
4394 cmp r1, #0 @ is second operand zero?
4395 beq common_errDivideByZero
4396
4397 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4398#ifdef __ARM_ARCH_EXT_IDIV__
4399 sdiv r0, r0, r1 @ r0<- op
4400#else
4401 bl __aeabi_idiv @ r0<- op, r0-r3 changed
4402#endif
4403 GET_INST_OPCODE ip @ extract opcode from rINST
4404 SET_VREG r0, r9 @ vAA<- r0
4405 GOTO_OPCODE ip @ jump to next instruction
4406 /* 11-14 instructions */
4407
4408/* ------------------------------ */
4409 .balign 128
4410.L_op_rem_int: /* 0x94 */
4411/* File: arm/op_rem_int.S */
4412 /*
4413 * Specialized 32-bit binary operation
4414 *
4415 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper
4416 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
4417 * ARMv7 CPUs that have hardware division support).
4418 *
4419 * NOTE: idivmod returns quotient in r0 and remainder in r1
4420 *
4421 * rem-int
4422 *
4423 */
4424 FETCH r0, 1 @ r0<- CCBB
4425 mov r9, rINST, lsr #8 @ r9<- AA
4426 mov r3, r0, lsr #8 @ r3<- CC
4427 and r2, r0, #255 @ r2<- BB
4428 GET_VREG r1, r3 @ r1<- vCC
4429 GET_VREG r0, r2 @ r0<- vBB
4430 cmp r1, #0 @ is second operand zero?
4431 beq common_errDivideByZero
4432
4433 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4434#ifdef __ARM_ARCH_EXT_IDIV__
4435 sdiv r2, r0, r1
4436 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed
4437#else
4438 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
4439#endif
4440 GET_INST_OPCODE ip @ extract opcode from rINST
4441 SET_VREG r1, r9 @ vAA<- r1
4442 GOTO_OPCODE ip @ jump to next instruction
4443 /* 11-14 instructions */
4444
4445/* ------------------------------ */
4446 .balign 128
4447.L_op_and_int: /* 0x95 */
4448/* File: arm/op_and_int.S */
4449/* File: arm/binop.S */
4450 /*
4451 * Generic 32-bit binary operation. Provide an "instr" line that
4452 * specifies an instruction that performs "result = r0 op r1".
4453 * This could be an ARM instruction or a function call. (If the result
4454 * comes back in a register other than r0, you can override "result".)
4455 *
4456 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4457 * vCC (r1). Useful for integer division and modulus. Note that we
4458 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4459 * handles it correctly.
4460 *
4461 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4462 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4463 * mul-float, div-float, rem-float
4464 */
4465 /* binop vAA, vBB, vCC */
4466 FETCH r0, 1 @ r0<- CCBB
4467 mov r9, rINST, lsr #8 @ r9<- AA
4468 mov r3, r0, lsr #8 @ r3<- CC
4469 and r2, r0, #255 @ r2<- BB
4470 GET_VREG r1, r3 @ r1<- vCC
4471 GET_VREG r0, r2 @ r0<- vBB
4472 .if 0
4473 cmp r1, #0 @ is second operand zero?
4474 beq common_errDivideByZero
4475 .endif
4476
4477 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4478 @ optional op; may set condition codes
4479 and r0, r0, r1 @ r0<- op, r0-r3 changed
4480 GET_INST_OPCODE ip @ extract opcode from rINST
4481 SET_VREG r0, r9 @ vAA<- r0
4482 GOTO_OPCODE ip @ jump to next instruction
4483 /* 11-14 instructions */
4484
4485
4486/* ------------------------------ */
4487 .balign 128
4488.L_op_or_int: /* 0x96 */
4489/* File: arm/op_or_int.S */
4490/* File: arm/binop.S */
4491 /*
4492 * Generic 32-bit binary operation. Provide an "instr" line that
4493 * specifies an instruction that performs "result = r0 op r1".
4494 * This could be an ARM instruction or a function call. (If the result
4495 * comes back in a register other than r0, you can override "result".)
4496 *
4497 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4498 * vCC (r1). Useful for integer division and modulus. Note that we
4499 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4500 * handles it correctly.
4501 *
4502 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4503 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4504 * mul-float, div-float, rem-float
4505 */
4506 /* binop vAA, vBB, vCC */
4507 FETCH r0, 1 @ r0<- CCBB
4508 mov r9, rINST, lsr #8 @ r9<- AA
4509 mov r3, r0, lsr #8 @ r3<- CC
4510 and r2, r0, #255 @ r2<- BB
4511 GET_VREG r1, r3 @ r1<- vCC
4512 GET_VREG r0, r2 @ r0<- vBB
4513 .if 0
4514 cmp r1, #0 @ is second operand zero?
4515 beq common_errDivideByZero
4516 .endif
4517
4518 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4519 @ optional op; may set condition codes
4520 orr r0, r0, r1 @ r0<- op, r0-r3 changed
4521 GET_INST_OPCODE ip @ extract opcode from rINST
4522 SET_VREG r0, r9 @ vAA<- r0
4523 GOTO_OPCODE ip @ jump to next instruction
4524 /* 11-14 instructions */
4525
4526
4527/* ------------------------------ */
4528 .balign 128
4529.L_op_xor_int: /* 0x97 */
4530/* File: arm/op_xor_int.S */
4531/* File: arm/binop.S */
4532 /*
4533 * Generic 32-bit binary operation. Provide an "instr" line that
4534 * specifies an instruction that performs "result = r0 op r1".
4535 * This could be an ARM instruction or a function call. (If the result
4536 * comes back in a register other than r0, you can override "result".)
4537 *
4538 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4539 * vCC (r1). Useful for integer division and modulus. Note that we
4540 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4541 * handles it correctly.
4542 *
4543 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4544 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4545 * mul-float, div-float, rem-float
4546 */
4547 /* binop vAA, vBB, vCC */
4548 FETCH r0, 1 @ r0<- CCBB
4549 mov r9, rINST, lsr #8 @ r9<- AA
4550 mov r3, r0, lsr #8 @ r3<- CC
4551 and r2, r0, #255 @ r2<- BB
4552 GET_VREG r1, r3 @ r1<- vCC
4553 GET_VREG r0, r2 @ r0<- vBB
4554 .if 0
4555 cmp r1, #0 @ is second operand zero?
4556 beq common_errDivideByZero
4557 .endif
4558
4559 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4560 @ optional op; may set condition codes
4561 eor r0, r0, r1 @ r0<- op, r0-r3 changed
4562 GET_INST_OPCODE ip @ extract opcode from rINST
4563 SET_VREG r0, r9 @ vAA<- r0
4564 GOTO_OPCODE ip @ jump to next instruction
4565 /* 11-14 instructions */
4566
4567
4568/* ------------------------------ */
4569 .balign 128
4570.L_op_shl_int: /* 0x98 */
4571/* File: arm/op_shl_int.S */
4572/* File: arm/binop.S */
4573 /*
4574 * Generic 32-bit binary operation. Provide an "instr" line that
4575 * specifies an instruction that performs "result = r0 op r1".
4576 * This could be an ARM instruction or a function call. (If the result
4577 * comes back in a register other than r0, you can override "result".)
4578 *
4579 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4580 * vCC (r1). Useful for integer division and modulus. Note that we
4581 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4582 * handles it correctly.
4583 *
4584 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4585 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4586 * mul-float, div-float, rem-float
4587 */
4588 /* binop vAA, vBB, vCC */
4589 FETCH r0, 1 @ r0<- CCBB
4590 mov r9, rINST, lsr #8 @ r9<- AA
4591 mov r3, r0, lsr #8 @ r3<- CC
4592 and r2, r0, #255 @ r2<- BB
4593 GET_VREG r1, r3 @ r1<- vCC
4594 GET_VREG r0, r2 @ r0<- vBB
4595 .if 0
4596 cmp r1, #0 @ is second operand zero?
4597 beq common_errDivideByZero
4598 .endif
4599
4600 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4601 and r1, r1, #31 @ optional op; may set condition codes
4602 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
4603 GET_INST_OPCODE ip @ extract opcode from rINST
4604 SET_VREG r0, r9 @ vAA<- r0
4605 GOTO_OPCODE ip @ jump to next instruction
4606 /* 11-14 instructions */
4607
4608
4609/* ------------------------------ */
4610 .balign 128
4611.L_op_shr_int: /* 0x99 */
4612/* File: arm/op_shr_int.S */
4613/* File: arm/binop.S */
4614 /*
4615 * Generic 32-bit binary operation. Provide an "instr" line that
4616 * specifies an instruction that performs "result = r0 op r1".
4617 * This could be an ARM instruction or a function call. (If the result
4618 * comes back in a register other than r0, you can override "result".)
4619 *
4620 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4621 * vCC (r1). Useful for integer division and modulus. Note that we
4622 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4623 * handles it correctly.
4624 *
4625 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4626 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4627 * mul-float, div-float, rem-float
4628 */
4629 /* binop vAA, vBB, vCC */
4630 FETCH r0, 1 @ r0<- CCBB
4631 mov r9, rINST, lsr #8 @ r9<- AA
4632 mov r3, r0, lsr #8 @ r3<- CC
4633 and r2, r0, #255 @ r2<- BB
4634 GET_VREG r1, r3 @ r1<- vCC
4635 GET_VREG r0, r2 @ r0<- vBB
4636 .if 0
4637 cmp r1, #0 @ is second operand zero?
4638 beq common_errDivideByZero
4639 .endif
4640
4641 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4642 and r1, r1, #31 @ optional op; may set condition codes
4643 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
4644 GET_INST_OPCODE ip @ extract opcode from rINST
4645 SET_VREG r0, r9 @ vAA<- r0
4646 GOTO_OPCODE ip @ jump to next instruction
4647 /* 11-14 instructions */
4648
4649
4650/* ------------------------------ */
4651 .balign 128
4652.L_op_ushr_int: /* 0x9a */
4653/* File: arm/op_ushr_int.S */
4654/* File: arm/binop.S */
4655 /*
4656 * Generic 32-bit binary operation. Provide an "instr" line that
4657 * specifies an instruction that performs "result = r0 op r1".
4658 * This could be an ARM instruction or a function call. (If the result
4659 * comes back in a register other than r0, you can override "result".)
4660 *
4661 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4662 * vCC (r1). Useful for integer division and modulus. Note that we
4663 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4664 * handles it correctly.
4665 *
4666 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4667 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4668 * mul-float, div-float, rem-float
4669 */
4670 /* binop vAA, vBB, vCC */
4671 FETCH r0, 1 @ r0<- CCBB
4672 mov r9, rINST, lsr #8 @ r9<- AA
4673 mov r3, r0, lsr #8 @ r3<- CC
4674 and r2, r0, #255 @ r2<- BB
4675 GET_VREG r1, r3 @ r1<- vCC
4676 GET_VREG r0, r2 @ r0<- vBB
4677 .if 0
4678 cmp r1, #0 @ is second operand zero?
4679 beq common_errDivideByZero
4680 .endif
4681
4682 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4683 and r1, r1, #31 @ optional op; may set condition codes
4684 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
4685 GET_INST_OPCODE ip @ extract opcode from rINST
4686 SET_VREG r0, r9 @ vAA<- r0
4687 GOTO_OPCODE ip @ jump to next instruction
4688 /* 11-14 instructions */
4689
4690
4691/* ------------------------------ */
4692 .balign 128
4693.L_op_add_long: /* 0x9b */
4694/* File: arm/op_add_long.S */
4695/* File: arm/binopWide.S */
4696 /*
4697 * Generic 64-bit binary operation. Provide an "instr" line that
4698 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4699 * This could be an ARM instruction or a function call. (If the result
4700 * comes back in a register other than r0, you can override "result".)
4701 *
4702 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4703 * vCC (r1). Useful for integer division and modulus.
4704 *
4705 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4706 * xor-long, add-double, sub-double, mul-double, div-double,
4707 * rem-double
4708 *
4709 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4710 */
4711 /* binop vAA, vBB, vCC */
4712 FETCH r0, 1 @ r0<- CCBB
4713 mov r9, rINST, lsr #8 @ r9<- AA
4714 and r2, r0, #255 @ r2<- BB
4715 mov r3, r0, lsr #8 @ r3<- CC
4716 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4717 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4718 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4719 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4720 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4721 .if 0
4722 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4723 beq common_errDivideByZero
4724 .endif
4725 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4726
4727 adds r0, r0, r2 @ optional op; may set condition codes
4728 adc r1, r1, r3 @ result<- op, r0-r3 changed
4729 GET_INST_OPCODE ip @ extract opcode from rINST
4730 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4731 GOTO_OPCODE ip @ jump to next instruction
4732 /* 14-17 instructions */
4733
4734
4735/* ------------------------------ */
4736 .balign 128
4737.L_op_sub_long: /* 0x9c */
4738/* File: arm/op_sub_long.S */
4739/* File: arm/binopWide.S */
4740 /*
4741 * Generic 64-bit binary operation. Provide an "instr" line that
4742 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4743 * This could be an ARM instruction or a function call. (If the result
4744 * comes back in a register other than r0, you can override "result".)
4745 *
4746 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4747 * vCC (r1). Useful for integer division and modulus.
4748 *
4749 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4750 * xor-long, add-double, sub-double, mul-double, div-double,
4751 * rem-double
4752 *
4753 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4754 */
4755 /* binop vAA, vBB, vCC */
4756 FETCH r0, 1 @ r0<- CCBB
4757 mov r9, rINST, lsr #8 @ r9<- AA
4758 and r2, r0, #255 @ r2<- BB
4759 mov r3, r0, lsr #8 @ r3<- CC
4760 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4761 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4762 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4763 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4764 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4765 .if 0
4766 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4767 beq common_errDivideByZero
4768 .endif
4769 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4770
4771 subs r0, r0, r2 @ optional op; may set condition codes
4772 sbc r1, r1, r3 @ result<- op, r0-r3 changed
4773 GET_INST_OPCODE ip @ extract opcode from rINST
4774 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4775 GOTO_OPCODE ip @ jump to next instruction
4776 /* 14-17 instructions */
4777
4778
4779/* ------------------------------ */
4780 .balign 128
4781.L_op_mul_long: /* 0x9d */
4782/* File: arm/op_mul_long.S */
4783 /*
4784 * Signed 64-bit integer multiply.
4785 *
4786 * Consider WXxYZ (r1r0 x r3r2) with a long multiply:
4787 * WX
4788 * x YZ
4789 * --------
4790 * ZW ZX
4791 * YW YX
4792 *
4793 * The low word of the result holds ZX, the high word holds
4794 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because
4795 * it doesn't fit in the low 64 bits.
4796 *
4797 * Unlike most ARM math operations, multiply instructions have
4798 * restrictions on using the same register more than once (Rd and Rm
4799 * cannot be the same).
4800 */
4801 /* mul-long vAA, vBB, vCC */
4802 FETCH r0, 1 @ r0<- CCBB
4803 and r2, r0, #255 @ r2<- BB
4804 mov r3, r0, lsr #8 @ r3<- CC
4805 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4806 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4807 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4808 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4809 mul ip, r2, r1 @ ip<- ZxW
4810 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
4811 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
4812 mov r0, rINST, lsr #8 @ r0<- AA
4813 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
4814 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA]
4815 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4816 GET_INST_OPCODE ip @ extract opcode from rINST
4817 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
4818 GOTO_OPCODE ip @ jump to next instruction
4819
4820/* ------------------------------ */
4821 .balign 128
4822.L_op_div_long: /* 0x9e */
4823/* File: arm/op_div_long.S */
4824/* File: arm/binopWide.S */
4825 /*
4826 * Generic 64-bit binary operation. Provide an "instr" line that
4827 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4828 * This could be an ARM instruction or a function call. (If the result
4829 * comes back in a register other than r0, you can override "result".)
4830 *
4831 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4832 * vCC (r1). Useful for integer division and modulus.
4833 *
4834 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4835 * xor-long, add-double, sub-double, mul-double, div-double,
4836 * rem-double
4837 *
4838 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4839 */
4840 /* binop vAA, vBB, vCC */
4841 FETCH r0, 1 @ r0<- CCBB
4842 mov r9, rINST, lsr #8 @ r9<- AA
4843 and r2, r0, #255 @ r2<- BB
4844 mov r3, r0, lsr #8 @ r3<- CC
4845 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4846 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4847 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4848 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4849 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4850 .if 1
4851 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4852 beq common_errDivideByZero
4853 .endif
4854 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4855
4856 @ optional op; may set condition codes
4857 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4858 GET_INST_OPCODE ip @ extract opcode from rINST
4859 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4860 GOTO_OPCODE ip @ jump to next instruction
4861 /* 14-17 instructions */
4862
4863
4864/* ------------------------------ */
4865 .balign 128
4866.L_op_rem_long: /* 0x9f */
4867/* File: arm/op_rem_long.S */
4868/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
4869/* File: arm/binopWide.S */
4870 /*
4871 * Generic 64-bit binary operation. Provide an "instr" line that
4872 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4873 * This could be an ARM instruction or a function call. (If the result
4874 * comes back in a register other than r0, you can override "result".)
4875 *
4876 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4877 * vCC (r1). Useful for integer division and modulus.
4878 *
4879 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4880 * xor-long, add-double, sub-double, mul-double, div-double,
4881 * rem-double
4882 *
4883 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4884 */
4885 /* binop vAA, vBB, vCC */
4886 FETCH r0, 1 @ r0<- CCBB
4887 mov r9, rINST, lsr #8 @ r9<- AA
4888 and r2, r0, #255 @ r2<- BB
4889 mov r3, r0, lsr #8 @ r3<- CC
4890 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4891 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4892 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4893 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4894 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4895 .if 1
4896 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4897 beq common_errDivideByZero
4898 .endif
4899 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4900
4901 @ optional op; may set condition codes
4902 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4903 GET_INST_OPCODE ip @ extract opcode from rINST
4904 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
4905 GOTO_OPCODE ip @ jump to next instruction
4906 /* 14-17 instructions */
4907
4908
4909/* ------------------------------ */
4910 .balign 128
4911.L_op_and_long: /* 0xa0 */
4912/* File: arm/op_and_long.S */
4913/* File: arm/binopWide.S */
4914 /*
4915 * Generic 64-bit binary operation. Provide an "instr" line that
4916 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4917 * This could be an ARM instruction or a function call. (If the result
4918 * comes back in a register other than r0, you can override "result".)
4919 *
4920 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4921 * vCC (r1). Useful for integer division and modulus.
4922 *
4923 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4924 * xor-long, add-double, sub-double, mul-double, div-double,
4925 * rem-double
4926 *
4927 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4928 */
4929 /* binop vAA, vBB, vCC */
4930 FETCH r0, 1 @ r0<- CCBB
4931 mov r9, rINST, lsr #8 @ r9<- AA
4932 and r2, r0, #255 @ r2<- BB
4933 mov r3, r0, lsr #8 @ r3<- CC
4934 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4935 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4936 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4937 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4938 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4939 .if 0
4940 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4941 beq common_errDivideByZero
4942 .endif
4943 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4944
4945 and r0, r0, r2 @ optional op; may set condition codes
4946 and r1, r1, r3 @ result<- op, r0-r3 changed
4947 GET_INST_OPCODE ip @ extract opcode from rINST
4948 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4949 GOTO_OPCODE ip @ jump to next instruction
4950 /* 14-17 instructions */
4951
4952
4953/* ------------------------------ */
4954 .balign 128
4955.L_op_or_long: /* 0xa1 */
4956/* File: arm/op_or_long.S */
4957/* File: arm/binopWide.S */
4958 /*
4959 * Generic 64-bit binary operation. Provide an "instr" line that
4960 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4961 * This could be an ARM instruction or a function call. (If the result
4962 * comes back in a register other than r0, you can override "result".)
4963 *
4964 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4965 * vCC (r1). Useful for integer division and modulus.
4966 *
4967 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4968 * xor-long, add-double, sub-double, mul-double, div-double,
4969 * rem-double
4970 *
4971 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4972 */
4973 /* binop vAA, vBB, vCC */
4974 FETCH r0, 1 @ r0<- CCBB
4975 mov r9, rINST, lsr #8 @ r9<- AA
4976 and r2, r0, #255 @ r2<- BB
4977 mov r3, r0, lsr #8 @ r3<- CC
4978 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4979 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4980 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4981 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4982 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4983 .if 0
4984 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4985 beq common_errDivideByZero
4986 .endif
4987 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
4988
4989 orr r0, r0, r2 @ optional op; may set condition codes
4990 orr r1, r1, r3 @ result<- op, r0-r3 changed
4991 GET_INST_OPCODE ip @ extract opcode from rINST
4992 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4993 GOTO_OPCODE ip @ jump to next instruction
4994 /* 14-17 instructions */
4995
4996
4997/* ------------------------------ */
4998 .balign 128
4999.L_op_xor_long: /* 0xa2 */
5000/* File: arm/op_xor_long.S */
5001/* File: arm/binopWide.S */
5002 /*
5003 * Generic 64-bit binary operation. Provide an "instr" line that
5004 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5005 * This could be an ARM instruction or a function call. (If the result
5006 * comes back in a register other than r0, you can override "result".)
5007 *
5008 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5009 * vCC (r1). Useful for integer division and modulus.
5010 *
5011 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5012 * xor-long, add-double, sub-double, mul-double, div-double,
5013 * rem-double
5014 *
5015 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5016 */
5017 /* binop vAA, vBB, vCC */
5018 FETCH r0, 1 @ r0<- CCBB
5019 mov r9, rINST, lsr #8 @ r9<- AA
5020 and r2, r0, #255 @ r2<- BB
5021 mov r3, r0, lsr #8 @ r3<- CC
5022 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5023 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
5024 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
5025 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
5026 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
5027 .if 0
5028 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5029 beq common_errDivideByZero
5030 .endif
5031 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5032
5033 eor r0, r0, r2 @ optional op; may set condition codes
5034 eor r1, r1, r3 @ result<- op, r0-r3 changed
5035 GET_INST_OPCODE ip @ extract opcode from rINST
5036 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5037 GOTO_OPCODE ip @ jump to next instruction
5038 /* 14-17 instructions */
5039
5040
5041/* ------------------------------ */
5042 .balign 128
5043.L_op_shl_long: /* 0xa3 */
5044/* File: arm/op_shl_long.S */
5045 /*
5046 * Long integer shift. This is different from the generic 32/64-bit
5047 * binary operations because vAA/vBB are 64-bit but vCC (the shift
5048 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
5049 * 6 bits of the shift distance.
5050 */
5051 /* shl-long vAA, vBB, vCC */
5052 FETCH r0, 1 @ r0<- CCBB
5053 mov r9, rINST, lsr #8 @ r9<- AA
5054 and r3, r0, #255 @ r3<- BB
5055 mov r0, r0, lsr #8 @ r0<- CC
5056 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
5057 GET_VREG r2, r0 @ r2<- vCC
5058 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
5059 and r2, r2, #63 @ r2<- r2 & 0x3f
5060 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5061
5062 mov r1, r1, asl r2 @ r1<- r1 << r2
5063 rsb r3, r2, #32 @ r3<- 32 - r2
5064 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
5065 subs ip, r2, #32 @ ip<- r2 - 32
5066 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
5067 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5068 mov r0, r0, asl r2 @ r0<- r0 << r2
5069 GET_INST_OPCODE ip @ extract opcode from rINST
5070 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
5071 GOTO_OPCODE ip @ jump to next instruction
5072
5073/* ------------------------------ */
5074 .balign 128
5075.L_op_shr_long: /* 0xa4 */
5076/* File: arm/op_shr_long.S */
5077 /*
5078 * Long integer shift. This is different from the generic 32/64-bit
5079 * binary operations because vAA/vBB are 64-bit but vCC (the shift
5080 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
5081 * 6 bits of the shift distance.
5082 */
5083 /* shr-long vAA, vBB, vCC */
5084 FETCH r0, 1 @ r0<- CCBB
5085 mov r9, rINST, lsr #8 @ r9<- AA
5086 and r3, r0, #255 @ r3<- BB
5087 mov r0, r0, lsr #8 @ r0<- CC
5088 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
5089 GET_VREG r2, r0 @ r2<- vCC
5090 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
5091 and r2, r2, #63 @ r0<- r0 & 0x3f
5092 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5093
5094 mov r0, r0, lsr r2 @ r0<- r2 >> r2
5095 rsb r3, r2, #32 @ r3<- 32 - r2
5096 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
5097 subs ip, r2, #32 @ ip<- r2 - 32
5098 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
5099 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5100 mov r1, r1, asr r2 @ r1<- r1 >> r2
5101 GET_INST_OPCODE ip @ extract opcode from rINST
5102 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
5103 GOTO_OPCODE ip @ jump to next instruction
5104
5105/* ------------------------------ */
5106 .balign 128
5107.L_op_ushr_long: /* 0xa5 */
5108/* File: arm/op_ushr_long.S */
5109 /*
5110 * Long integer shift. This is different from the generic 32/64-bit
5111 * binary operations because vAA/vBB are 64-bit but vCC (the shift
5112 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
5113 * 6 bits of the shift distance.
5114 */
5115 /* ushr-long vAA, vBB, vCC */
5116 FETCH r0, 1 @ r0<- CCBB
5117 mov r9, rINST, lsr #8 @ r9<- AA
5118 and r3, r0, #255 @ r3<- BB
5119 mov r0, r0, lsr #8 @ r0<- CC
5120 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
5121 GET_VREG r2, r0 @ r2<- vCC
5122 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
5123 and r2, r2, #63 @ r0<- r0 & 0x3f
5124 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5125
5126 mov r0, r0, lsr r2 @ r0<- r2 >> r2
5127 rsb r3, r2, #32 @ r3<- 32 - r2
5128 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
5129 subs ip, r2, #32 @ ip<- r2 - 32
5130 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
5131 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5132 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
5133 GET_INST_OPCODE ip @ extract opcode from rINST
5134 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
5135 GOTO_OPCODE ip @ jump to next instruction
5136
5137/* ------------------------------ */
5138 .balign 128
5139.L_op_add_float: /* 0xa6 */
5140/* File: arm/op_add_float.S */
5141/* File: arm/fbinop.S */
5142 /*
5143 * Generic 32-bit floating-point operation. Provide an "instr" line that
5144 * specifies an instruction that performs "s2 = s0 op s1". Because we
5145 * use the "softfp" ABI, this must be an instruction, not a function call.
5146 *
5147 * For: add-float, sub-float, mul-float, div-float
5148 */
5149 /* floatop vAA, vBB, vCC */
5150 FETCH r0, 1 @ r0<- CCBB
5151 mov r9, rINST, lsr #8 @ r9<- AA
5152 mov r3, r0, lsr #8 @ r3<- CC
5153 and r2, r0, #255 @ r2<- BB
5154 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
5155 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
5156 flds s1, [r3] @ s1<- vCC
5157 flds s0, [r2] @ s0<- vBB
5158
5159 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5160 fadds s2, s0, s1 @ s2<- op
5161 GET_INST_OPCODE ip @ extract opcode from rINST
5162 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA
5163 fsts s2, [r9] @ vAA<- s2
5164 GOTO_OPCODE ip @ jump to next instruction
5165
5166
5167/* ------------------------------ */
5168 .balign 128
5169.L_op_sub_float: /* 0xa7 */
5170/* File: arm/op_sub_float.S */
5171/* File: arm/fbinop.S */
5172 /*
5173 * Generic 32-bit floating-point operation. Provide an "instr" line that
5174 * specifies an instruction that performs "s2 = s0 op s1". Because we
5175 * use the "softfp" ABI, this must be an instruction, not a function call.
5176 *
5177 * For: add-float, sub-float, mul-float, div-float
5178 */
5179 /* floatop vAA, vBB, vCC */
5180 FETCH r0, 1 @ r0<- CCBB
5181 mov r9, rINST, lsr #8 @ r9<- AA
5182 mov r3, r0, lsr #8 @ r3<- CC
5183 and r2, r0, #255 @ r2<- BB
5184 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
5185 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
5186 flds s1, [r3] @ s1<- vCC
5187 flds s0, [r2] @ s0<- vBB
5188
5189 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5190 fsubs s2, s0, s1 @ s2<- op
5191 GET_INST_OPCODE ip @ extract opcode from rINST
5192 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA
5193 fsts s2, [r9] @ vAA<- s2
5194 GOTO_OPCODE ip @ jump to next instruction
5195
5196
5197/* ------------------------------ */
5198 .balign 128
5199.L_op_mul_float: /* 0xa8 */
5200/* File: arm/op_mul_float.S */
5201/* File: arm/fbinop.S */
5202 /*
5203 * Generic 32-bit floating-point operation. Provide an "instr" line that
5204 * specifies an instruction that performs "s2 = s0 op s1". Because we
5205 * use the "softfp" ABI, this must be an instruction, not a function call.
5206 *
5207 * For: add-float, sub-float, mul-float, div-float
5208 */
5209 /* floatop vAA, vBB, vCC */
5210 FETCH r0, 1 @ r0<- CCBB
5211 mov r9, rINST, lsr #8 @ r9<- AA
5212 mov r3, r0, lsr #8 @ r3<- CC
5213 and r2, r0, #255 @ r2<- BB
5214 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
5215 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
5216 flds s1, [r3] @ s1<- vCC
5217 flds s0, [r2] @ s0<- vBB
5218
5219 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5220 fmuls s2, s0, s1 @ s2<- op
5221 GET_INST_OPCODE ip @ extract opcode from rINST
5222 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA
5223 fsts s2, [r9] @ vAA<- s2
5224 GOTO_OPCODE ip @ jump to next instruction
5225
5226
5227/* ------------------------------ */
5228 .balign 128
5229.L_op_div_float: /* 0xa9 */
5230/* File: arm/op_div_float.S */
5231/* File: arm/fbinop.S */
5232 /*
5233 * Generic 32-bit floating-point operation. Provide an "instr" line that
5234 * specifies an instruction that performs "s2 = s0 op s1". Because we
5235 * use the "softfp" ABI, this must be an instruction, not a function call.
5236 *
5237 * For: add-float, sub-float, mul-float, div-float
5238 */
5239 /* floatop vAA, vBB, vCC */
5240 FETCH r0, 1 @ r0<- CCBB
5241 mov r9, rINST, lsr #8 @ r9<- AA
5242 mov r3, r0, lsr #8 @ r3<- CC
5243 and r2, r0, #255 @ r2<- BB
5244 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
5245 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
5246 flds s1, [r3] @ s1<- vCC
5247 flds s0, [r2] @ s0<- vBB
5248
5249 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5250 fdivs s2, s0, s1 @ s2<- op
5251 GET_INST_OPCODE ip @ extract opcode from rINST
5252 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA
5253 fsts s2, [r9] @ vAA<- s2
5254 GOTO_OPCODE ip @ jump to next instruction
5255
5256
5257/* ------------------------------ */
5258 .balign 128
5259.L_op_rem_float: /* 0xaa */
5260/* File: arm/op_rem_float.S */
5261/* EABI doesn't define a float remainder function, but libm does */
5262/* File: arm/binop.S */
5263 /*
5264 * Generic 32-bit binary operation. Provide an "instr" line that
5265 * specifies an instruction that performs "result = r0 op r1".
5266 * This could be an ARM instruction or a function call. (If the result
5267 * comes back in a register other than r0, you can override "result".)
5268 *
5269 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5270 * vCC (r1). Useful for integer division and modulus. Note that we
5271 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
5272 * handles it correctly.
5273 *
5274 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
5275 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
5276 * mul-float, div-float, rem-float
5277 */
5278 /* binop vAA, vBB, vCC */
5279 FETCH r0, 1 @ r0<- CCBB
5280 mov r9, rINST, lsr #8 @ r9<- AA
5281 mov r3, r0, lsr #8 @ r3<- CC
5282 and r2, r0, #255 @ r2<- BB
5283 GET_VREG r1, r3 @ r1<- vCC
5284 GET_VREG r0, r2 @ r0<- vBB
5285 .if 0
5286 cmp r1, #0 @ is second operand zero?
5287 beq common_errDivideByZero
5288 .endif
5289
5290 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5291 @ optional op; may set condition codes
5292 bl fmodf @ r0<- op, r0-r3 changed
5293 GET_INST_OPCODE ip @ extract opcode from rINST
5294 SET_VREG r0, r9 @ vAA<- r0
5295 GOTO_OPCODE ip @ jump to next instruction
5296 /* 11-14 instructions */
5297
5298
5299/* ------------------------------ */
5300 .balign 128
5301.L_op_add_double: /* 0xab */
5302/* File: arm/op_add_double.S */
5303/* File: arm/fbinopWide.S */
5304 /*
5305 * Generic 64-bit double-precision floating point binary operation.
5306 * Provide an "instr" line that specifies an instruction that performs
5307 * "d2 = d0 op d1".
5308 *
5309 * for: add-double, sub-double, mul-double, div-double
5310 */
5311 /* doubleop vAA, vBB, vCC */
5312 FETCH r0, 1 @ r0<- CCBB
5313 mov r9, rINST, lsr #8 @ r9<- AA
5314 mov r3, r0, lsr #8 @ r3<- CC
5315 and r2, r0, #255 @ r2<- BB
5316 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
5317 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
5318 fldd d1, [r3] @ d1<- vCC
5319 fldd d0, [r2] @ d0<- vBB
5320
5321 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5322 faddd d2, d0, d1 @ s2<- op
5323 GET_INST_OPCODE ip @ extract opcode from rINST
5324 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA
5325 fstd d2, [r9] @ vAA<- d2
5326 GOTO_OPCODE ip @ jump to next instruction
5327
5328
5329/* ------------------------------ */
5330 .balign 128
5331.L_op_sub_double: /* 0xac */
5332/* File: arm/op_sub_double.S */
5333/* File: arm/fbinopWide.S */
5334 /*
5335 * Generic 64-bit double-precision floating point binary operation.
5336 * Provide an "instr" line that specifies an instruction that performs
5337 * "d2 = d0 op d1".
5338 *
5339 * for: add-double, sub-double, mul-double, div-double
5340 */
5341 /* doubleop vAA, vBB, vCC */
5342 FETCH r0, 1 @ r0<- CCBB
5343 mov r9, rINST, lsr #8 @ r9<- AA
5344 mov r3, r0, lsr #8 @ r3<- CC
5345 and r2, r0, #255 @ r2<- BB
5346 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
5347 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
5348 fldd d1, [r3] @ d1<- vCC
5349 fldd d0, [r2] @ d0<- vBB
5350
5351 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5352 fsubd d2, d0, d1 @ s2<- op
5353 GET_INST_OPCODE ip @ extract opcode from rINST
5354 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA
5355 fstd d2, [r9] @ vAA<- d2
5356 GOTO_OPCODE ip @ jump to next instruction
5357
5358
5359/* ------------------------------ */
5360 .balign 128
5361.L_op_mul_double: /* 0xad */
5362/* File: arm/op_mul_double.S */
5363/* File: arm/fbinopWide.S */
5364 /*
5365 * Generic 64-bit double-precision floating point binary operation.
5366 * Provide an "instr" line that specifies an instruction that performs
5367 * "d2 = d0 op d1".
5368 *
5369 * for: add-double, sub-double, mul-double, div-double
5370 */
5371 /* doubleop vAA, vBB, vCC */
5372 FETCH r0, 1 @ r0<- CCBB
5373 mov r9, rINST, lsr #8 @ r9<- AA
5374 mov r3, r0, lsr #8 @ r3<- CC
5375 and r2, r0, #255 @ r2<- BB
5376 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
5377 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
5378 fldd d1, [r3] @ d1<- vCC
5379 fldd d0, [r2] @ d0<- vBB
5380
5381 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5382 fmuld d2, d0, d1 @ s2<- op
5383 GET_INST_OPCODE ip @ extract opcode from rINST
5384 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA
5385 fstd d2, [r9] @ vAA<- d2
5386 GOTO_OPCODE ip @ jump to next instruction
5387
5388
5389/* ------------------------------ */
5390 .balign 128
5391.L_op_div_double: /* 0xae */
5392/* File: arm/op_div_double.S */
5393/* File: arm/fbinopWide.S */
5394 /*
5395 * Generic 64-bit double-precision floating point binary operation.
5396 * Provide an "instr" line that specifies an instruction that performs
5397 * "d2 = d0 op d1".
5398 *
5399 * for: add-double, sub-double, mul-double, div-double
5400 */
5401 /* doubleop vAA, vBB, vCC */
5402 FETCH r0, 1 @ r0<- CCBB
5403 mov r9, rINST, lsr #8 @ r9<- AA
5404 mov r3, r0, lsr #8 @ r3<- CC
5405 and r2, r0, #255 @ r2<- BB
5406 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
5407 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
5408 fldd d1, [r3] @ d1<- vCC
5409 fldd d0, [r2] @ d0<- vBB
5410
5411 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5412 fdivd d2, d0, d1 @ s2<- op
5413 GET_INST_OPCODE ip @ extract opcode from rINST
5414 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA
5415 fstd d2, [r9] @ vAA<- d2
5416 GOTO_OPCODE ip @ jump to next instruction
5417
5418
5419/* ------------------------------ */
5420 .balign 128
5421.L_op_rem_double: /* 0xaf */
5422/* File: arm/op_rem_double.S */
5423/* EABI doesn't define a double remainder function, but libm does */
5424/* File: arm/binopWide.S */
5425 /*
5426 * Generic 64-bit binary operation. Provide an "instr" line that
5427 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5428 * This could be an ARM instruction or a function call. (If the result
5429 * comes back in a register other than r0, you can override "result".)
5430 *
5431 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5432 * vCC (r1). Useful for integer division and modulus.
5433 *
5434 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5435 * xor-long, add-double, sub-double, mul-double, div-double,
5436 * rem-double
5437 *
5438 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5439 */
5440 /* binop vAA, vBB, vCC */
5441 FETCH r0, 1 @ r0<- CCBB
5442 mov r9, rINST, lsr #8 @ r9<- AA
5443 and r2, r0, #255 @ r2<- BB
5444 mov r3, r0, lsr #8 @ r3<- CC
5445 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5446 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
5447 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
5448 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
5449 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
5450 .if 0
5451 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5452 beq common_errDivideByZero
5453 .endif
5454 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
5455
5456 @ optional op; may set condition codes
5457 bl fmod @ result<- op, r0-r3 changed
5458 GET_INST_OPCODE ip @ extract opcode from rINST
5459 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5460 GOTO_OPCODE ip @ jump to next instruction
5461 /* 14-17 instructions */
5462
5463
5464/* ------------------------------ */
5465 .balign 128
5466.L_op_add_int_2addr: /* 0xb0 */
5467/* File: arm/op_add_int_2addr.S */
5468/* File: arm/binop2addr.S */
5469 /*
5470 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5471 * that specifies an instruction that performs "result = r0 op r1".
5472 * This could be an ARM instruction or a function call. (If the result
5473 * comes back in a register other than r0, you can override "result".)
5474 *
5475 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5476 * vCC (r1). Useful for integer division and modulus.
5477 *
5478 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5479 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5480 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5481 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5482 */
5483 /* binop/2addr vA, vB */
5484 mov r3, rINST, lsr #12 @ r3<- B
5485 ubfx r9, rINST, #8, #4 @ r9<- A
5486 GET_VREG r1, r3 @ r1<- vB
5487 GET_VREG r0, r9 @ r0<- vA
5488 .if 0
5489 cmp r1, #0 @ is second operand zero?
5490 beq common_errDivideByZero
5491 .endif
5492 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5493
5494 @ optional op; may set condition codes
5495 add r0, r0, r1 @ r0<- op, r0-r3 changed
5496 GET_INST_OPCODE ip @ extract opcode from rINST
5497 SET_VREG r0, r9 @ vAA<- r0
5498 GOTO_OPCODE ip @ jump to next instruction
5499 /* 10-13 instructions */
5500
5501
5502/* ------------------------------ */
5503 .balign 128
5504.L_op_sub_int_2addr: /* 0xb1 */
5505/* File: arm/op_sub_int_2addr.S */
5506/* File: arm/binop2addr.S */
5507 /*
5508 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5509 * that specifies an instruction that performs "result = r0 op r1".
5510 * This could be an ARM instruction or a function call. (If the result
5511 * comes back in a register other than r0, you can override "result".)
5512 *
5513 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5514 * vCC (r1). Useful for integer division and modulus.
5515 *
5516 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5517 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5518 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5519 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5520 */
5521 /* binop/2addr vA, vB */
5522 mov r3, rINST, lsr #12 @ r3<- B
5523 ubfx r9, rINST, #8, #4 @ r9<- A
5524 GET_VREG r1, r3 @ r1<- vB
5525 GET_VREG r0, r9 @ r0<- vA
5526 .if 0
5527 cmp r1, #0 @ is second operand zero?
5528 beq common_errDivideByZero
5529 .endif
5530 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5531
5532 @ optional op; may set condition codes
5533 sub r0, r0, r1 @ r0<- op, r0-r3 changed
5534 GET_INST_OPCODE ip @ extract opcode from rINST
5535 SET_VREG r0, r9 @ vAA<- r0
5536 GOTO_OPCODE ip @ jump to next instruction
5537 /* 10-13 instructions */
5538
5539
5540/* ------------------------------ */
5541 .balign 128
5542.L_op_mul_int_2addr: /* 0xb2 */
5543/* File: arm/op_mul_int_2addr.S */
5544/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
5545/* File: arm/binop2addr.S */
5546 /*
5547 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5548 * that specifies an instruction that performs "result = r0 op r1".
5549 * This could be an ARM instruction or a function call. (If the result
5550 * comes back in a register other than r0, you can override "result".)
5551 *
5552 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5553 * vCC (r1). Useful for integer division and modulus.
5554 *
5555 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5556 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5557 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5558 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5559 */
5560 /* binop/2addr vA, vB */
5561 mov r3, rINST, lsr #12 @ r3<- B
5562 ubfx r9, rINST, #8, #4 @ r9<- A
5563 GET_VREG r1, r3 @ r1<- vB
5564 GET_VREG r0, r9 @ r0<- vA
5565 .if 0
5566 cmp r1, #0 @ is second operand zero?
5567 beq common_errDivideByZero
5568 .endif
5569 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5570
5571 @ optional op; may set condition codes
5572 mul r0, r1, r0 @ r0<- op, r0-r3 changed
5573 GET_INST_OPCODE ip @ extract opcode from rINST
5574 SET_VREG r0, r9 @ vAA<- r0
5575 GOTO_OPCODE ip @ jump to next instruction
5576 /* 10-13 instructions */
5577
5578
5579/* ------------------------------ */
5580 .balign 128
5581.L_op_div_int_2addr: /* 0xb3 */
5582/* File: arm/op_div_int_2addr.S */
5583 /*
5584 * Specialized 32-bit binary operation
5585 *
5586 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
5587 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
5588 * ARMv7 CPUs that have hardware division support).
5589 *
5590 * div-int/2addr
5591 *
5592 */
5593 mov r3, rINST, lsr #12 @ r3<- B
5594 ubfx r9, rINST, #8, #4 @ r9<- A
5595 GET_VREG r1, r3 @ r1<- vB
5596 GET_VREG r0, r9 @ r0<- vA
5597 cmp r1, #0 @ is second operand zero?
5598 beq common_errDivideByZero
5599 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5600
5601#ifdef __ARM_ARCH_EXT_IDIV__
5602 sdiv r0, r0, r1 @ r0<- op
5603#else
5604 bl __aeabi_idiv @ r0<- op, r0-r3 changed
5605#endif
5606 GET_INST_OPCODE ip @ extract opcode from rINST
5607 SET_VREG r0, r9 @ vAA<- r0
5608 GOTO_OPCODE ip @ jump to next instruction
5609 /* 10-13 instructions */
5610
5611
5612/* ------------------------------ */
5613 .balign 128
5614.L_op_rem_int_2addr: /* 0xb4 */
5615/* File: arm/op_rem_int_2addr.S */
5616 /*
5617 * Specialized 32-bit binary operation
5618 *
5619 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper
5620 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
5621 * ARMv7 CPUs that have hardware division support).
5622 *
5623 * NOTE: idivmod returns quotient in r0 and remainder in r1
5624 *
5625 * rem-int/2addr
5626 *
5627 */
5628 mov r3, rINST, lsr #12 @ r3<- B
5629 ubfx r9, rINST, #8, #4 @ r9<- A
5630 GET_VREG r1, r3 @ r1<- vB
5631 GET_VREG r0, r9 @ r0<- vA
5632 cmp r1, #0 @ is second operand zero?
5633 beq common_errDivideByZero
5634 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5635
5636#ifdef __ARM_ARCH_EXT_IDIV__
5637 sdiv r2, r0, r1
5638 mls r1, r1, r2, r0 @ r1<- op
5639#else
5640 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
5641#endif
5642 GET_INST_OPCODE ip @ extract opcode from rINST
5643 SET_VREG r1, r9 @ vAA<- r1
5644 GOTO_OPCODE ip @ jump to next instruction
5645 /* 10-13 instructions */
5646
5647
5648/* ------------------------------ */
5649 .balign 128
5650.L_op_and_int_2addr: /* 0xb5 */
5651/* File: arm/op_and_int_2addr.S */
5652/* File: arm/binop2addr.S */
5653 /*
5654 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5655 * that specifies an instruction that performs "result = r0 op r1".
5656 * This could be an ARM instruction or a function call. (If the result
5657 * comes back in a register other than r0, you can override "result".)
5658 *
5659 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5660 * vCC (r1). Useful for integer division and modulus.
5661 *
5662 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5663 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5664 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5665 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5666 */
5667 /* binop/2addr vA, vB */
5668 mov r3, rINST, lsr #12 @ r3<- B
5669 ubfx r9, rINST, #8, #4 @ r9<- A
5670 GET_VREG r1, r3 @ r1<- vB
5671 GET_VREG r0, r9 @ r0<- vA
5672 .if 0
5673 cmp r1, #0 @ is second operand zero?
5674 beq common_errDivideByZero
5675 .endif
5676 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5677
5678 @ optional op; may set condition codes
5679 and r0, r0, r1 @ r0<- op, r0-r3 changed
5680 GET_INST_OPCODE ip @ extract opcode from rINST
5681 SET_VREG r0, r9 @ vAA<- r0
5682 GOTO_OPCODE ip @ jump to next instruction
5683 /* 10-13 instructions */
5684
5685
5686/* ------------------------------ */
5687 .balign 128
5688.L_op_or_int_2addr: /* 0xb6 */
5689/* File: arm/op_or_int_2addr.S */
5690/* File: arm/binop2addr.S */
5691 /*
5692 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5693 * that specifies an instruction that performs "result = r0 op r1".
5694 * This could be an ARM instruction or a function call. (If the result
5695 * comes back in a register other than r0, you can override "result".)
5696 *
5697 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5698 * vCC (r1). Useful for integer division and modulus.
5699 *
5700 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5701 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5702 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5703 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5704 */
5705 /* binop/2addr vA, vB */
5706 mov r3, rINST, lsr #12 @ r3<- B
5707 ubfx r9, rINST, #8, #4 @ r9<- A
5708 GET_VREG r1, r3 @ r1<- vB
5709 GET_VREG r0, r9 @ r0<- vA
5710 .if 0
5711 cmp r1, #0 @ is second operand zero?
5712 beq common_errDivideByZero
5713 .endif
5714 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5715
5716 @ optional op; may set condition codes
5717 orr r0, r0, r1 @ r0<- op, r0-r3 changed
5718 GET_INST_OPCODE ip @ extract opcode from rINST
5719 SET_VREG r0, r9 @ vAA<- r0
5720 GOTO_OPCODE ip @ jump to next instruction
5721 /* 10-13 instructions */
5722
5723
5724/* ------------------------------ */
5725 .balign 128
5726.L_op_xor_int_2addr: /* 0xb7 */
5727/* File: arm/op_xor_int_2addr.S */
5728/* File: arm/binop2addr.S */
5729 /*
5730 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5731 * that specifies an instruction that performs "result = r0 op r1".
5732 * This could be an ARM instruction or a function call. (If the result
5733 * comes back in a register other than r0, you can override "result".)
5734 *
5735 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5736 * vCC (r1). Useful for integer division and modulus.
5737 *
5738 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5739 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5740 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5741 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5742 */
5743 /* binop/2addr vA, vB */
5744 mov r3, rINST, lsr #12 @ r3<- B
5745 ubfx r9, rINST, #8, #4 @ r9<- A
5746 GET_VREG r1, r3 @ r1<- vB
5747 GET_VREG r0, r9 @ r0<- vA
5748 .if 0
5749 cmp r1, #0 @ is second operand zero?
5750 beq common_errDivideByZero
5751 .endif
5752 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5753
5754 @ optional op; may set condition codes
5755 eor r0, r0, r1 @ r0<- op, r0-r3 changed
5756 GET_INST_OPCODE ip @ extract opcode from rINST
5757 SET_VREG r0, r9 @ vAA<- r0
5758 GOTO_OPCODE ip @ jump to next instruction
5759 /* 10-13 instructions */
5760
5761
5762/* ------------------------------ */
5763 .balign 128
5764.L_op_shl_int_2addr: /* 0xb8 */
5765/* File: arm/op_shl_int_2addr.S */
5766/* File: arm/binop2addr.S */
5767 /*
5768 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5769 * that specifies an instruction that performs "result = r0 op r1".
5770 * This could be an ARM instruction or a function call. (If the result
5771 * comes back in a register other than r0, you can override "result".)
5772 *
5773 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5774 * vCC (r1). Useful for integer division and modulus.
5775 *
5776 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5777 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5778 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5779 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5780 */
5781 /* binop/2addr vA, vB */
5782 mov r3, rINST, lsr #12 @ r3<- B
5783 ubfx r9, rINST, #8, #4 @ r9<- A
5784 GET_VREG r1, r3 @ r1<- vB
5785 GET_VREG r0, r9 @ r0<- vA
5786 .if 0
5787 cmp r1, #0 @ is second operand zero?
5788 beq common_errDivideByZero
5789 .endif
5790 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5791
5792 and r1, r1, #31 @ optional op; may set condition codes
5793 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
5794 GET_INST_OPCODE ip @ extract opcode from rINST
5795 SET_VREG r0, r9 @ vAA<- r0
5796 GOTO_OPCODE ip @ jump to next instruction
5797 /* 10-13 instructions */
5798
5799
5800/* ------------------------------ */
5801 .balign 128
5802.L_op_shr_int_2addr: /* 0xb9 */
5803/* File: arm/op_shr_int_2addr.S */
5804/* File: arm/binop2addr.S */
5805 /*
5806 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5807 * that specifies an instruction that performs "result = r0 op r1".
5808 * This could be an ARM instruction or a function call. (If the result
5809 * comes back in a register other than r0, you can override "result".)
5810 *
5811 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5812 * vCC (r1). Useful for integer division and modulus.
5813 *
5814 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5815 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5816 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5817 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5818 */
5819 /* binop/2addr vA, vB */
5820 mov r3, rINST, lsr #12 @ r3<- B
5821 ubfx r9, rINST, #8, #4 @ r9<- A
5822 GET_VREG r1, r3 @ r1<- vB
5823 GET_VREG r0, r9 @ r0<- vA
5824 .if 0
5825 cmp r1, #0 @ is second operand zero?
5826 beq common_errDivideByZero
5827 .endif
5828 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5829
5830 and r1, r1, #31 @ optional op; may set condition codes
5831 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
5832 GET_INST_OPCODE ip @ extract opcode from rINST
5833 SET_VREG r0, r9 @ vAA<- r0
5834 GOTO_OPCODE ip @ jump to next instruction
5835 /* 10-13 instructions */
5836
5837
5838/* ------------------------------ */
5839 .balign 128
5840.L_op_ushr_int_2addr: /* 0xba */
5841/* File: arm/op_ushr_int_2addr.S */
5842/* File: arm/binop2addr.S */
5843 /*
5844 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5845 * that specifies an instruction that performs "result = r0 op r1".
5846 * This could be an ARM instruction or a function call. (If the result
5847 * comes back in a register other than r0, you can override "result".)
5848 *
5849 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5850 * vCC (r1). Useful for integer division and modulus.
5851 *
5852 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5853 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5854 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5855 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5856 */
5857 /* binop/2addr vA, vB */
5858 mov r3, rINST, lsr #12 @ r3<- B
5859 ubfx r9, rINST, #8, #4 @ r9<- A
5860 GET_VREG r1, r3 @ r1<- vB
5861 GET_VREG r0, r9 @ r0<- vA
5862 .if 0
5863 cmp r1, #0 @ is second operand zero?
5864 beq common_errDivideByZero
5865 .endif
5866 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5867
5868 and r1, r1, #31 @ optional op; may set condition codes
5869 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
5870 GET_INST_OPCODE ip @ extract opcode from rINST
5871 SET_VREG r0, r9 @ vAA<- r0
5872 GOTO_OPCODE ip @ jump to next instruction
5873 /* 10-13 instructions */
5874
5875
5876/* ------------------------------ */
5877 .balign 128
5878.L_op_add_long_2addr: /* 0xbb */
5879/* File: arm/op_add_long_2addr.S */
5880/* File: arm/binopWide2addr.S */
5881 /*
5882 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5883 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5884 * This could be an ARM instruction or a function call. (If the result
5885 * comes back in a register other than r0, you can override "result".)
5886 *
5887 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5888 * vCC (r1). Useful for integer division and modulus.
5889 *
5890 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5891 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5892 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5893 * rem-double/2addr
5894 */
5895 /* binop/2addr vA, vB */
5896 mov r1, rINST, lsr #12 @ r1<- B
5897 ubfx r9, rINST, #8, #4 @ r9<- A
5898 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5899 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5900 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5901 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5902 .if 0
5903 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5904 beq common_errDivideByZero
5905 .endif
5906 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5907
5908 adds r0, r0, r2 @ optional op; may set condition codes
5909 adc r1, r1, r3 @ result<- op, r0-r3 changed
5910 GET_INST_OPCODE ip @ extract opcode from rINST
5911 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5912 GOTO_OPCODE ip @ jump to next instruction
5913 /* 12-15 instructions */
5914
5915
5916/* ------------------------------ */
5917 .balign 128
5918.L_op_sub_long_2addr: /* 0xbc */
5919/* File: arm/op_sub_long_2addr.S */
5920/* File: arm/binopWide2addr.S */
5921 /*
5922 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5923 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5924 * This could be an ARM instruction or a function call. (If the result
5925 * comes back in a register other than r0, you can override "result".)
5926 *
5927 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5928 * vCC (r1). Useful for integer division and modulus.
5929 *
5930 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5931 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5932 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5933 * rem-double/2addr
5934 */
5935 /* binop/2addr vA, vB */
5936 mov r1, rINST, lsr #12 @ r1<- B
5937 ubfx r9, rINST, #8, #4 @ r9<- A
5938 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5939 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5940 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5941 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5942 .if 0
5943 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5944 beq common_errDivideByZero
5945 .endif
5946 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5947
5948 subs r0, r0, r2 @ optional op; may set condition codes
5949 sbc r1, r1, r3 @ result<- op, r0-r3 changed
5950 GET_INST_OPCODE ip @ extract opcode from rINST
5951 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5952 GOTO_OPCODE ip @ jump to next instruction
5953 /* 12-15 instructions */
5954
5955
5956/* ------------------------------ */
5957 .balign 128
5958.L_op_mul_long_2addr: /* 0xbd */
5959/* File: arm/op_mul_long_2addr.S */
5960 /*
5961 * Signed 64-bit integer multiply, "/2addr" version.
5962 *
5963 * See op_mul_long for an explanation.
5964 *
5965 * We get a little tight on registers, so to avoid looking up &fp[A]
5966 * again we stuff it into rINST.
5967 */
5968 /* mul-long/2addr vA, vB */
5969 mov r1, rINST, lsr #12 @ r1<- B
5970 ubfx r9, rINST, #8, #4 @ r9<- A
5971 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5972 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A]
5973 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5974 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1
5975 mul ip, r2, r1 @ ip<- ZxW
5976 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
5977 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
5978 mov r0, rINST @ r0<- &fp[A] (free up rINST)
5979 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
5980 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
5981 GET_INST_OPCODE ip @ extract opcode from rINST
5982 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
5983 GOTO_OPCODE ip @ jump to next instruction
5984
5985/* ------------------------------ */
5986 .balign 128
5987.L_op_div_long_2addr: /* 0xbe */
5988/* File: arm/op_div_long_2addr.S */
5989/* File: arm/binopWide2addr.S */
5990 /*
5991 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5992 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5993 * This could be an ARM instruction or a function call. (If the result
5994 * comes back in a register other than r0, you can override "result".)
5995 *
5996 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5997 * vCC (r1). Useful for integer division and modulus.
5998 *
5999 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6000 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6001 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6002 * rem-double/2addr
6003 */
6004 /* binop/2addr vA, vB */
6005 mov r1, rINST, lsr #12 @ r1<- B
6006 ubfx r9, rINST, #8, #4 @ r9<- A
6007 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6008 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6009 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6010 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6011 .if 1
6012 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6013 beq common_errDivideByZero
6014 .endif
6015 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6016
6017 @ optional op; may set condition codes
6018 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
6019 GET_INST_OPCODE ip @ extract opcode from rINST
6020 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6021 GOTO_OPCODE ip @ jump to next instruction
6022 /* 12-15 instructions */
6023
6024
6025/* ------------------------------ */
6026 .balign 128
6027.L_op_rem_long_2addr: /* 0xbf */
6028/* File: arm/op_rem_long_2addr.S */
6029/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
6030/* File: arm/binopWide2addr.S */
6031 /*
6032 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6033 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6034 * This could be an ARM instruction or a function call. (If the result
6035 * comes back in a register other than r0, you can override "result".)
6036 *
6037 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6038 * vCC (r1). Useful for integer division and modulus.
6039 *
6040 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6041 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6042 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6043 * rem-double/2addr
6044 */
6045 /* binop/2addr vA, vB */
6046 mov r1, rINST, lsr #12 @ r1<- B
6047 ubfx r9, rINST, #8, #4 @ r9<- A
6048 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6049 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6050 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6051 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6052 .if 1
6053 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6054 beq common_errDivideByZero
6055 .endif
6056 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6057
6058 @ optional op; may set condition codes
6059 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
6060 GET_INST_OPCODE ip @ extract opcode from rINST
6061 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
6062 GOTO_OPCODE ip @ jump to next instruction
6063 /* 12-15 instructions */
6064
6065
6066/* ------------------------------ */
6067 .balign 128
6068.L_op_and_long_2addr: /* 0xc0 */
6069/* File: arm/op_and_long_2addr.S */
6070/* File: arm/binopWide2addr.S */
6071 /*
6072 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6073 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6074 * This could be an ARM instruction or a function call. (If the result
6075 * comes back in a register other than r0, you can override "result".)
6076 *
6077 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6078 * vCC (r1). Useful for integer division and modulus.
6079 *
6080 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6081 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6082 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6083 * rem-double/2addr
6084 */
6085 /* binop/2addr vA, vB */
6086 mov r1, rINST, lsr #12 @ r1<- B
6087 ubfx r9, rINST, #8, #4 @ r9<- A
6088 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6089 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6090 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6091 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6092 .if 0
6093 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6094 beq common_errDivideByZero
6095 .endif
6096 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6097
6098 and r0, r0, r2 @ optional op; may set condition codes
6099 and r1, r1, r3 @ result<- op, r0-r3 changed
6100 GET_INST_OPCODE ip @ extract opcode from rINST
6101 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6102 GOTO_OPCODE ip @ jump to next instruction
6103 /* 12-15 instructions */
6104
6105
6106/* ------------------------------ */
6107 .balign 128
6108.L_op_or_long_2addr: /* 0xc1 */
6109/* File: arm/op_or_long_2addr.S */
6110/* File: arm/binopWide2addr.S */
6111 /*
6112 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6113 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6114 * This could be an ARM instruction or a function call. (If the result
6115 * comes back in a register other than r0, you can override "result".)
6116 *
6117 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6118 * vCC (r1). Useful for integer division and modulus.
6119 *
6120 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6121 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6122 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6123 * rem-double/2addr
6124 */
6125 /* binop/2addr vA, vB */
6126 mov r1, rINST, lsr #12 @ r1<- B
6127 ubfx r9, rINST, #8, #4 @ r9<- A
6128 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6129 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6130 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6131 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6132 .if 0
6133 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6134 beq common_errDivideByZero
6135 .endif
6136 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6137
6138 orr r0, r0, r2 @ optional op; may set condition codes
6139 orr r1, r1, r3 @ result<- op, r0-r3 changed
6140 GET_INST_OPCODE ip @ extract opcode from rINST
6141 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6142 GOTO_OPCODE ip @ jump to next instruction
6143 /* 12-15 instructions */
6144
6145
6146/* ------------------------------ */
6147 .balign 128
6148.L_op_xor_long_2addr: /* 0xc2 */
6149/* File: arm/op_xor_long_2addr.S */
6150/* File: arm/binopWide2addr.S */
6151 /*
6152 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6153 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6154 * This could be an ARM instruction or a function call. (If the result
6155 * comes back in a register other than r0, you can override "result".)
6156 *
6157 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6158 * vCC (r1). Useful for integer division and modulus.
6159 *
6160 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6161 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6162 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6163 * rem-double/2addr
6164 */
6165 /* binop/2addr vA, vB */
6166 mov r1, rINST, lsr #12 @ r1<- B
6167 ubfx r9, rINST, #8, #4 @ r9<- A
6168 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6169 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6170 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6171 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6172 .if 0
6173 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6174 beq common_errDivideByZero
6175 .endif
6176 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6177
6178 eor r0, r0, r2 @ optional op; may set condition codes
6179 eor r1, r1, r3 @ result<- op, r0-r3 changed
6180 GET_INST_OPCODE ip @ extract opcode from rINST
6181 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6182 GOTO_OPCODE ip @ jump to next instruction
6183 /* 12-15 instructions */
6184
6185
6186/* ------------------------------ */
6187 .balign 128
6188.L_op_shl_long_2addr: /* 0xc3 */
6189/* File: arm/op_shl_long_2addr.S */
6190 /*
6191 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6192 * 32-bit shift distance.
6193 */
6194 /* shl-long/2addr vA, vB */
6195 mov r3, rINST, lsr #12 @ r3<- B
6196 ubfx r9, rINST, #8, #4 @ r9<- A
6197 GET_VREG r2, r3 @ r2<- vB
6198 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6199 and r2, r2, #63 @ r2<- r2 & 0x3f
6200 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6201
6202 mov r1, r1, asl r2 @ r1<- r1 << r2
6203 rsb r3, r2, #32 @ r3<- 32 - r2
6204 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
6205 subs ip, r2, #32 @ ip<- r2 - 32
6206 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6207 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
6208 mov r0, r0, asl r2 @ r0<- r0 << r2
6209 GET_INST_OPCODE ip @ extract opcode from rINST
6210 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
6211 GOTO_OPCODE ip @ jump to next instruction
6212
6213/* ------------------------------ */
6214 .balign 128
6215.L_op_shr_long_2addr: /* 0xc4 */
6216/* File: arm/op_shr_long_2addr.S */
6217 /*
6218 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6219 * 32-bit shift distance.
6220 */
6221 /* shr-long/2addr vA, vB */
6222 mov r3, rINST, lsr #12 @ r3<- B
6223 ubfx r9, rINST, #8, #4 @ r9<- A
6224 GET_VREG r2, r3 @ r2<- vB
6225 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6226 and r2, r2, #63 @ r2<- r2 & 0x3f
6227 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6228
6229 mov r0, r0, lsr r2 @ r0<- r2 >> r2
6230 rsb r3, r2, #32 @ r3<- 32 - r2
6231 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
6232 subs ip, r2, #32 @ ip<- r2 - 32
6233 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6234 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
6235 mov r1, r1, asr r2 @ r1<- r1 >> r2
6236 GET_INST_OPCODE ip @ extract opcode from rINST
6237 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
6238 GOTO_OPCODE ip @ jump to next instruction
6239
6240/* ------------------------------ */
6241 .balign 128
6242.L_op_ushr_long_2addr: /* 0xc5 */
6243/* File: arm/op_ushr_long_2addr.S */
6244 /*
6245 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6246 * 32-bit shift distance.
6247 */
6248 /* ushr-long/2addr vA, vB */
6249 mov r3, rINST, lsr #12 @ r3<- B
6250 ubfx r9, rINST, #8, #4 @ r9<- A
6251 GET_VREG r2, r3 @ r2<- vB
6252 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6253 and r2, r2, #63 @ r2<- r2 & 0x3f
6254 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6255
6256 mov r0, r0, lsr r2 @ r0<- r2 >> r2
6257 rsb r3, r2, #32 @ r3<- 32 - r2
6258 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
6259 subs ip, r2, #32 @ ip<- r2 - 32
6260 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6261 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
6262 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
6263 GET_INST_OPCODE ip @ extract opcode from rINST
6264 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
6265 GOTO_OPCODE ip @ jump to next instruction
6266
6267/* ------------------------------ */
6268 .balign 128
6269.L_op_add_float_2addr: /* 0xc6 */
6270/* File: arm/op_add_float_2addr.S */
6271/* File: arm/fbinop2addr.S */
6272 /*
6273 * Generic 32-bit floating point "/2addr" binary operation. Provide
6274 * an "instr" line that specifies an instruction that performs
6275 * "s2 = s0 op s1".
6276 *
6277 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6278 */
6279 /* binop/2addr vA, vB */
6280 mov r3, rINST, lsr #12 @ r3<- B
6281 mov r9, rINST, lsr #8 @ r9<- A+
6282 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
6283 and r9, r9, #15 @ r9<- A
6284 flds s1, [r3] @ s1<- vB
6285 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
6286 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6287 flds s0, [r9] @ s0<- vA
6288
6289 fadds s2, s0, s1 @ s2<- op
6290 GET_INST_OPCODE ip @ extract opcode from rINST
6291 fsts s2, [r9] @ vAA<- s2
6292 GOTO_OPCODE ip @ jump to next instruction
6293
6294
6295/* ------------------------------ */
6296 .balign 128
6297.L_op_sub_float_2addr: /* 0xc7 */
6298/* File: arm/op_sub_float_2addr.S */
6299/* File: arm/fbinop2addr.S */
6300 /*
6301 * Generic 32-bit floating point "/2addr" binary operation. Provide
6302 * an "instr" line that specifies an instruction that performs
6303 * "s2 = s0 op s1".
6304 *
6305 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6306 */
6307 /* binop/2addr vA, vB */
6308 mov r3, rINST, lsr #12 @ r3<- B
6309 mov r9, rINST, lsr #8 @ r9<- A+
6310 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
6311 and r9, r9, #15 @ r9<- A
6312 flds s1, [r3] @ s1<- vB
6313 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
6314 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6315 flds s0, [r9] @ s0<- vA
6316
6317 fsubs s2, s0, s1 @ s2<- op
6318 GET_INST_OPCODE ip @ extract opcode from rINST
6319 fsts s2, [r9] @ vAA<- s2
6320 GOTO_OPCODE ip @ jump to next instruction
6321
6322
6323/* ------------------------------ */
6324 .balign 128
6325.L_op_mul_float_2addr: /* 0xc8 */
6326/* File: arm/op_mul_float_2addr.S */
6327/* File: arm/fbinop2addr.S */
6328 /*
6329 * Generic 32-bit floating point "/2addr" binary operation. Provide
6330 * an "instr" line that specifies an instruction that performs
6331 * "s2 = s0 op s1".
6332 *
6333 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6334 */
6335 /* binop/2addr vA, vB */
6336 mov r3, rINST, lsr #12 @ r3<- B
6337 mov r9, rINST, lsr #8 @ r9<- A+
6338 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
6339 and r9, r9, #15 @ r9<- A
6340 flds s1, [r3] @ s1<- vB
6341 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
6342 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6343 flds s0, [r9] @ s0<- vA
6344
6345 fmuls s2, s0, s1 @ s2<- op
6346 GET_INST_OPCODE ip @ extract opcode from rINST
6347 fsts s2, [r9] @ vAA<- s2
6348 GOTO_OPCODE ip @ jump to next instruction
6349
6350
6351/* ------------------------------ */
6352 .balign 128
6353.L_op_div_float_2addr: /* 0xc9 */
6354/* File: arm/op_div_float_2addr.S */
6355/* File: arm/fbinop2addr.S */
6356 /*
6357 * Generic 32-bit floating point "/2addr" binary operation. Provide
6358 * an "instr" line that specifies an instruction that performs
6359 * "s2 = s0 op s1".
6360 *
6361 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6362 */
6363 /* binop/2addr vA, vB */
6364 mov r3, rINST, lsr #12 @ r3<- B
6365 mov r9, rINST, lsr #8 @ r9<- A+
6366 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
6367 and r9, r9, #15 @ r9<- A
6368 flds s1, [r3] @ s1<- vB
6369 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
6370 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6371 flds s0, [r9] @ s0<- vA
6372
6373 fdivs s2, s0, s1 @ s2<- op
6374 GET_INST_OPCODE ip @ extract opcode from rINST
6375 fsts s2, [r9] @ vAA<- s2
6376 GOTO_OPCODE ip @ jump to next instruction
6377
6378
6379/* ------------------------------ */
6380 .balign 128
6381.L_op_rem_float_2addr: /* 0xca */
6382/* File: arm/op_rem_float_2addr.S */
6383/* EABI doesn't define a float remainder function, but libm does */
6384/* File: arm/binop2addr.S */
6385 /*
6386 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
6387 * that specifies an instruction that performs "result = r0 op r1".
6388 * This could be an ARM instruction or a function call. (If the result
6389 * comes back in a register other than r0, you can override "result".)
6390 *
6391 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6392 * vCC (r1). Useful for integer division and modulus.
6393 *
6394 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
6395 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
6396 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
6397 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
6398 */
6399 /* binop/2addr vA, vB */
6400 mov r3, rINST, lsr #12 @ r3<- B
6401 ubfx r9, rINST, #8, #4 @ r9<- A
6402 GET_VREG r1, r3 @ r1<- vB
6403 GET_VREG r0, r9 @ r0<- vA
6404 .if 0
6405 cmp r1, #0 @ is second operand zero?
6406 beq common_errDivideByZero
6407 .endif
6408 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6409
6410 @ optional op; may set condition codes
6411 bl fmodf @ r0<- op, r0-r3 changed
6412 GET_INST_OPCODE ip @ extract opcode from rINST
6413 SET_VREG r0, r9 @ vAA<- r0
6414 GOTO_OPCODE ip @ jump to next instruction
6415 /* 10-13 instructions */
6416
6417
6418/* ------------------------------ */
6419 .balign 128
6420.L_op_add_double_2addr: /* 0xcb */
6421/* File: arm/op_add_double_2addr.S */
6422/* File: arm/fbinopWide2addr.S */
6423 /*
6424 * Generic 64-bit floating point "/2addr" binary operation. Provide
6425 * an "instr" line that specifies an instruction that performs
6426 * "d2 = d0 op d1".
6427 *
6428 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6429 * div-double/2addr
6430 */
6431 /* binop/2addr vA, vB */
6432 mov r3, rINST, lsr #12 @ r3<- B
6433 mov r9, rINST, lsr #8 @ r9<- A+
6434 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
6435 and r9, r9, #15 @ r9<- A
6436 fldd d1, [r3] @ d1<- vB
6437 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
6438 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6439 fldd d0, [r9] @ d0<- vA
6440
6441 faddd d2, d0, d1 @ d2<- op
6442 GET_INST_OPCODE ip @ extract opcode from rINST
6443 fstd d2, [r9] @ vAA<- d2
6444 GOTO_OPCODE ip @ jump to next instruction
6445
6446
6447/* ------------------------------ */
6448 .balign 128
6449.L_op_sub_double_2addr: /* 0xcc */
6450/* File: arm/op_sub_double_2addr.S */
6451/* File: arm/fbinopWide2addr.S */
6452 /*
6453 * Generic 64-bit floating point "/2addr" binary operation. Provide
6454 * an "instr" line that specifies an instruction that performs
6455 * "d2 = d0 op d1".
6456 *
6457 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6458 * div-double/2addr
6459 */
6460 /* binop/2addr vA, vB */
6461 mov r3, rINST, lsr #12 @ r3<- B
6462 mov r9, rINST, lsr #8 @ r9<- A+
6463 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
6464 and r9, r9, #15 @ r9<- A
6465 fldd d1, [r3] @ d1<- vB
6466 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
6467 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6468 fldd d0, [r9] @ d0<- vA
6469
6470 fsubd d2, d0, d1 @ d2<- op
6471 GET_INST_OPCODE ip @ extract opcode from rINST
6472 fstd d2, [r9] @ vAA<- d2
6473 GOTO_OPCODE ip @ jump to next instruction
6474
6475
6476/* ------------------------------ */
6477 .balign 128
6478.L_op_mul_double_2addr: /* 0xcd */
6479/* File: arm/op_mul_double_2addr.S */
6480/* File: arm/fbinopWide2addr.S */
6481 /*
6482 * Generic 64-bit floating point "/2addr" binary operation. Provide
6483 * an "instr" line that specifies an instruction that performs
6484 * "d2 = d0 op d1".
6485 *
6486 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6487 * div-double/2addr
6488 */
6489 /* binop/2addr vA, vB */
6490 mov r3, rINST, lsr #12 @ r3<- B
6491 mov r9, rINST, lsr #8 @ r9<- A+
6492 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
6493 and r9, r9, #15 @ r9<- A
6494 fldd d1, [r3] @ d1<- vB
6495 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
6496 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6497 fldd d0, [r9] @ d0<- vA
6498
6499 fmuld d2, d0, d1 @ d2<- op
6500 GET_INST_OPCODE ip @ extract opcode from rINST
6501 fstd d2, [r9] @ vAA<- d2
6502 GOTO_OPCODE ip @ jump to next instruction
6503
6504
6505/* ------------------------------ */
6506 .balign 128
6507.L_op_div_double_2addr: /* 0xce */
6508/* File: arm/op_div_double_2addr.S */
6509/* File: arm/fbinopWide2addr.S */
6510 /*
6511 * Generic 64-bit floating point "/2addr" binary operation. Provide
6512 * an "instr" line that specifies an instruction that performs
6513 * "d2 = d0 op d1".
6514 *
6515 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6516 * div-double/2addr
6517 */
6518 /* binop/2addr vA, vB */
6519 mov r3, rINST, lsr #12 @ r3<- B
6520 mov r9, rINST, lsr #8 @ r9<- A+
6521 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
6522 and r9, r9, #15 @ r9<- A
6523 fldd d1, [r3] @ d1<- vB
6524 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA
6525 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6526 fldd d0, [r9] @ d0<- vA
6527
6528 fdivd d2, d0, d1 @ d2<- op
6529 GET_INST_OPCODE ip @ extract opcode from rINST
6530 fstd d2, [r9] @ vAA<- d2
6531 GOTO_OPCODE ip @ jump to next instruction
6532
6533
6534/* ------------------------------ */
6535 .balign 128
6536.L_op_rem_double_2addr: /* 0xcf */
6537/* File: arm/op_rem_double_2addr.S */
6538/* EABI doesn't define a double remainder function, but libm does */
6539/* File: arm/binopWide2addr.S */
6540 /*
6541 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6542 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6543 * This could be an ARM instruction or a function call. (If the result
6544 * comes back in a register other than r0, you can override "result".)
6545 *
6546 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6547 * vCC (r1). Useful for integer division and modulus.
6548 *
6549 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6550 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6551 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6552 * rem-double/2addr
6553 */
6554 /* binop/2addr vA, vB */
6555 mov r1, rINST, lsr #12 @ r1<- B
6556 ubfx r9, rINST, #8, #4 @ r9<- A
6557 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6558 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6559 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6560 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6561 .if 0
6562 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6563 beq common_errDivideByZero
6564 .endif
6565 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
6566
6567 @ optional op; may set condition codes
6568 bl fmod @ result<- op, r0-r3 changed
6569 GET_INST_OPCODE ip @ extract opcode from rINST
6570 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6571 GOTO_OPCODE ip @ jump to next instruction
6572 /* 12-15 instructions */
6573
6574
6575/* ------------------------------ */
6576 .balign 128
6577.L_op_add_int_lit16: /* 0xd0 */
6578/* File: arm/op_add_int_lit16.S */
6579/* File: arm/binopLit16.S */
6580 /*
6581 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6582 * that specifies an instruction that performs "result = r0 op r1".
6583 * This could be an ARM instruction or a function call. (If the result
6584 * comes back in a register other than r0, you can override "result".)
6585 *
6586 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6587 * vCC (r1). Useful for integer division and modulus.
6588 *
6589 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6590 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6591 */
6592 /* binop/lit16 vA, vB, #+CCCC */
6593 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
6594 mov r2, rINST, lsr #12 @ r2<- B
6595 ubfx r9, rINST, #8, #4 @ r9<- A
6596 GET_VREG r0, r2 @ r0<- vB
6597 .if 0
6598 cmp r1, #0 @ is second operand zero?
6599 beq common_errDivideByZero
6600 .endif
6601 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6602
6603 add r0, r0, r1 @ r0<- op, r0-r3 changed
6604 GET_INST_OPCODE ip @ extract opcode from rINST
6605 SET_VREG r0, r9 @ vAA<- r0
6606 GOTO_OPCODE ip @ jump to next instruction
6607 /* 10-13 instructions */
6608
6609
6610/* ------------------------------ */
6611 .balign 128
6612.L_op_rsub_int: /* 0xd1 */
6613/* File: arm/op_rsub_int.S */
6614/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
6615/* File: arm/binopLit16.S */
6616 /*
6617 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6618 * that specifies an instruction that performs "result = r0 op r1".
6619 * This could be an ARM instruction or a function call. (If the result
6620 * comes back in a register other than r0, you can override "result".)
6621 *
6622 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6623 * vCC (r1). Useful for integer division and modulus.
6624 *
6625 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6626 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6627 */
6628 /* binop/lit16 vA, vB, #+CCCC */
6629 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
6630 mov r2, rINST, lsr #12 @ r2<- B
6631 ubfx r9, rINST, #8, #4 @ r9<- A
6632 GET_VREG r0, r2 @ r0<- vB
6633 .if 0
6634 cmp r1, #0 @ is second operand zero?
6635 beq common_errDivideByZero
6636 .endif
6637 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6638
6639 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6640 GET_INST_OPCODE ip @ extract opcode from rINST
6641 SET_VREG r0, r9 @ vAA<- r0
6642 GOTO_OPCODE ip @ jump to next instruction
6643 /* 10-13 instructions */
6644
6645
6646/* ------------------------------ */
6647 .balign 128
6648.L_op_mul_int_lit16: /* 0xd2 */
6649/* File: arm/op_mul_int_lit16.S */
6650/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6651/* File: arm/binopLit16.S */
6652 /*
6653 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6654 * that specifies an instruction that performs "result = r0 op r1".
6655 * This could be an ARM instruction or a function call. (If the result
6656 * comes back in a register other than r0, you can override "result".)
6657 *
6658 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6659 * vCC (r1). Useful for integer division and modulus.
6660 *
6661 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6662 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6663 */
6664 /* binop/lit16 vA, vB, #+CCCC */
6665 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
6666 mov r2, rINST, lsr #12 @ r2<- B
6667 ubfx r9, rINST, #8, #4 @ r9<- A
6668 GET_VREG r0, r2 @ r0<- vB
6669 .if 0
6670 cmp r1, #0 @ is second operand zero?
6671 beq common_errDivideByZero
6672 .endif
6673 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6674
6675 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6676 GET_INST_OPCODE ip @ extract opcode from rINST
6677 SET_VREG r0, r9 @ vAA<- r0
6678 GOTO_OPCODE ip @ jump to next instruction
6679 /* 10-13 instructions */
6680
6681
6682/* ------------------------------ */
6683 .balign 128
6684.L_op_div_int_lit16: /* 0xd3 */
6685/* File: arm/op_div_int_lit16.S */
6686 /*
6687 * Specialized 32-bit binary operation
6688 *
6689 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
6690 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
6691 * ARMv7 CPUs that have hardware division support).
6692 *
6693 * div-int/lit16
6694 *
6695 */
6696 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
6697 mov r2, rINST, lsr #12 @ r2<- B
6698 ubfx r9, rINST, #8, #4 @ r9<- A
6699 GET_VREG r0, r2 @ r0<- vB
6700 cmp r1, #0 @ is second operand zero?
6701 beq common_errDivideByZero
6702 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6703
6704#ifdef __ARM_ARCH_EXT_IDIV__
6705 sdiv r0, r0, r1 @ r0<- op
6706#else
6707 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6708#endif
6709 GET_INST_OPCODE ip @ extract opcode from rINST
6710 SET_VREG r0, r9 @ vAA<- r0
6711 GOTO_OPCODE ip @ jump to next instruction
6712 /* 10-13 instructions */
6713
6714/* ------------------------------ */
6715 .balign 128
6716.L_op_rem_int_lit16: /* 0xd4 */
6717/* File: arm/op_rem_int_lit16.S */
6718 /*
6719 * Specialized 32-bit binary operation
6720 *
6721 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper
6722 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
6723 * ARMv7 CPUs that have hardware division support).
6724 *
6725 * NOTE: idivmod returns quotient in r0 and remainder in r1
6726 *
6727 * rem-int/lit16
6728 *
6729 */
6730 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
6731 mov r2, rINST, lsr #12 @ r2<- B
6732 ubfx r9, rINST, #8, #4 @ r9<- A
6733 GET_VREG r0, r2 @ r0<- vB
6734 cmp r1, #0 @ is second operand zero?
6735 beq common_errDivideByZero
6736 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6737
6738#ifdef __ARM_ARCH_EXT_IDIV__
6739 sdiv r2, r0, r1
6740 mls r1, r1, r2, r0 @ r1<- op
6741#else
6742 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6743#endif
6744 GET_INST_OPCODE ip @ extract opcode from rINST
6745 SET_VREG r1, r9 @ vAA<- r1
6746 GOTO_OPCODE ip @ jump to next instruction
6747 /* 10-13 instructions */
6748
6749/* ------------------------------ */
6750 .balign 128
6751.L_op_and_int_lit16: /* 0xd5 */
6752/* File: arm/op_and_int_lit16.S */
6753/* File: arm/binopLit16.S */
6754 /*
6755 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6756 * that specifies an instruction that performs "result = r0 op r1".
6757 * This could be an ARM instruction or a function call. (If the result
6758 * comes back in a register other than r0, you can override "result".)
6759 *
6760 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6761 * vCC (r1). Useful for integer division and modulus.
6762 *
6763 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6764 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6765 */
6766 /* binop/lit16 vA, vB, #+CCCC */
6767 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
6768 mov r2, rINST, lsr #12 @ r2<- B
6769 ubfx r9, rINST, #8, #4 @ r9<- A
6770 GET_VREG r0, r2 @ r0<- vB
6771 .if 0
6772 cmp r1, #0 @ is second operand zero?
6773 beq common_errDivideByZero
6774 .endif
6775 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6776
6777 and r0, r0, r1 @ r0<- op, r0-r3 changed
6778 GET_INST_OPCODE ip @ extract opcode from rINST
6779 SET_VREG r0, r9 @ vAA<- r0
6780 GOTO_OPCODE ip @ jump to next instruction
6781 /* 10-13 instructions */
6782
6783
6784/* ------------------------------ */
6785 .balign 128
6786.L_op_or_int_lit16: /* 0xd6 */
6787/* File: arm/op_or_int_lit16.S */
6788/* File: arm/binopLit16.S */
6789 /*
6790 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6791 * that specifies an instruction that performs "result = r0 op r1".
6792 * This could be an ARM instruction or a function call. (If the result
6793 * comes back in a register other than r0, you can override "result".)
6794 *
6795 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6796 * vCC (r1). Useful for integer division and modulus.
6797 *
6798 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6799 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6800 */
6801 /* binop/lit16 vA, vB, #+CCCC */
6802 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
6803 mov r2, rINST, lsr #12 @ r2<- B
6804 ubfx r9, rINST, #8, #4 @ r9<- A
6805 GET_VREG r0, r2 @ r0<- vB
6806 .if 0
6807 cmp r1, #0 @ is second operand zero?
6808 beq common_errDivideByZero
6809 .endif
6810 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6811
6812 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6813 GET_INST_OPCODE ip @ extract opcode from rINST
6814 SET_VREG r0, r9 @ vAA<- r0
6815 GOTO_OPCODE ip @ jump to next instruction
6816 /* 10-13 instructions */
6817
6818
6819/* ------------------------------ */
6820 .balign 128
6821.L_op_xor_int_lit16: /* 0xd7 */
6822/* File: arm/op_xor_int_lit16.S */
6823/* File: arm/binopLit16.S */
6824 /*
6825 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6826 * that specifies an instruction that performs "result = r0 op r1".
6827 * This could be an ARM instruction or a function call. (If the result
6828 * comes back in a register other than r0, you can override "result".)
6829 *
6830 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6831 * vCC (r1). Useful for integer division and modulus.
6832 *
6833 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6834 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6835 */
6836 /* binop/lit16 vA, vB, #+CCCC */
6837 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
6838 mov r2, rINST, lsr #12 @ r2<- B
6839 ubfx r9, rINST, #8, #4 @ r9<- A
6840 GET_VREG r0, r2 @ r0<- vB
6841 .if 0
6842 cmp r1, #0 @ is second operand zero?
6843 beq common_errDivideByZero
6844 .endif
6845 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6846
6847 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6848 GET_INST_OPCODE ip @ extract opcode from rINST
6849 SET_VREG r0, r9 @ vAA<- r0
6850 GOTO_OPCODE ip @ jump to next instruction
6851 /* 10-13 instructions */
6852
6853
6854/* ------------------------------ */
6855 .balign 128
6856.L_op_add_int_lit8: /* 0xd8 */
6857/* File: arm/op_add_int_lit8.S */
6858/* File: arm/binopLit8.S */
6859 /*
6860 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6861 * that specifies an instruction that performs "result = r0 op r1".
6862 * This could be an ARM instruction or a function call. (If the result
6863 * comes back in a register other than r0, you can override "result".)
6864 *
6865 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6866 * vCC (r1). Useful for integer division and modulus.
6867 *
6868 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6869 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6870 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6871 */
6872 /* binop/lit8 vAA, vBB, #+CC */
6873 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
6874 mov r9, rINST, lsr #8 @ r9<- AA
6875 and r2, r3, #255 @ r2<- BB
6876 GET_VREG r0, r2 @ r0<- vBB
6877 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6878 .if 0
6879 @cmp r1, #0 @ is second operand zero?
6880 beq common_errDivideByZero
6881 .endif
6882 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6883
6884 @ optional op; may set condition codes
6885 add r0, r0, r1 @ r0<- op, r0-r3 changed
6886 GET_INST_OPCODE ip @ extract opcode from rINST
6887 SET_VREG r0, r9 @ vAA<- r0
6888 GOTO_OPCODE ip @ jump to next instruction
6889 /* 10-12 instructions */
6890
6891
6892/* ------------------------------ */
6893 .balign 128
6894.L_op_rsub_int_lit8: /* 0xd9 */
6895/* File: arm/op_rsub_int_lit8.S */
6896/* File: arm/binopLit8.S */
6897 /*
6898 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6899 * that specifies an instruction that performs "result = r0 op r1".
6900 * This could be an ARM instruction or a function call. (If the result
6901 * comes back in a register other than r0, you can override "result".)
6902 *
6903 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6904 * vCC (r1). Useful for integer division and modulus.
6905 *
6906 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6907 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6908 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6909 */
6910 /* binop/lit8 vAA, vBB, #+CC */
6911 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
6912 mov r9, rINST, lsr #8 @ r9<- AA
6913 and r2, r3, #255 @ r2<- BB
6914 GET_VREG r0, r2 @ r0<- vBB
6915 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6916 .if 0
6917 @cmp r1, #0 @ is second operand zero?
6918 beq common_errDivideByZero
6919 .endif
6920 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6921
6922 @ optional op; may set condition codes
6923 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6924 GET_INST_OPCODE ip @ extract opcode from rINST
6925 SET_VREG r0, r9 @ vAA<- r0
6926 GOTO_OPCODE ip @ jump to next instruction
6927 /* 10-12 instructions */
6928
6929
6930/* ------------------------------ */
6931 .balign 128
6932.L_op_mul_int_lit8: /* 0xda */
6933/* File: arm/op_mul_int_lit8.S */
6934/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6935/* File: arm/binopLit8.S */
6936 /*
6937 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6938 * that specifies an instruction that performs "result = r0 op r1".
6939 * This could be an ARM instruction or a function call. (If the result
6940 * comes back in a register other than r0, you can override "result".)
6941 *
6942 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6943 * vCC (r1). Useful for integer division and modulus.
6944 *
6945 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6946 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6947 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6948 */
6949 /* binop/lit8 vAA, vBB, #+CC */
6950 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
6951 mov r9, rINST, lsr #8 @ r9<- AA
6952 and r2, r3, #255 @ r2<- BB
6953 GET_VREG r0, r2 @ r0<- vBB
6954 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6955 .if 0
6956 @cmp r1, #0 @ is second operand zero?
6957 beq common_errDivideByZero
6958 .endif
6959 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6960
6961 @ optional op; may set condition codes
6962 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6963 GET_INST_OPCODE ip @ extract opcode from rINST
6964 SET_VREG r0, r9 @ vAA<- r0
6965 GOTO_OPCODE ip @ jump to next instruction
6966 /* 10-12 instructions */
6967
6968
6969/* ------------------------------ */
6970 .balign 128
6971.L_op_div_int_lit8: /* 0xdb */
6972/* File: arm/op_div_int_lit8.S */
6973 /*
6974 * Specialized 32-bit binary operation
6975 *
6976 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
6977 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
6978 * ARMv7 CPUs that have hardware division support).
6979 *
6980 * div-int/lit8
6981 *
6982 */
6983 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
6984 mov r9, rINST, lsr #8 @ r9<- AA
6985 and r2, r3, #255 @ r2<- BB
6986 GET_VREG r0, r2 @ r0<- vBB
6987 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6988 @cmp r1, #0 @ is second operand zero?
6989 beq common_errDivideByZero
6990 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
6991
6992#ifdef __ARM_ARCH_EXT_IDIV__
6993 sdiv r0, r0, r1 @ r0<- op
6994#else
6995 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6996#endif
6997 GET_INST_OPCODE ip @ extract opcode from rINST
6998 SET_VREG r0, r9 @ vAA<- r0
6999 GOTO_OPCODE ip @ jump to next instruction
7000 /* 10-12 instructions */
7001
7002/* ------------------------------ */
7003 .balign 128
7004.L_op_rem_int_lit8: /* 0xdc */
7005/* File: arm/op_rem_int_lit8.S */
7006 /*
7007 * Specialized 32-bit binary operation
7008 *
7009 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper
7010 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
7011 * ARMv7 CPUs that have hardware division support).
7012 *
7013 * NOTE: idivmod returns quotient in r0 and remainder in r1
7014 *
7015 * rem-int/lit8
7016 *
7017 */
7018 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC)
7019 mov r9, rINST, lsr #8 @ r9<- AA
7020 and r2, r3, #255 @ r2<- BB
7021 GET_VREG r0, r2 @ r0<- vBB
7022 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7023 @cmp r1, #0 @ is second operand zero?
7024 beq common_errDivideByZero
7025 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7026
7027#ifdef __ARM_ARCH_EXT_IDIV__
7028 sdiv r2, r0, r1
7029 mls r1, r1, r2, r0 @ r1<- op
7030#else
7031 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
7032#endif
7033 GET_INST_OPCODE ip @ extract opcode from rINST
7034 SET_VREG r1, r9 @ vAA<- r1
7035 GOTO_OPCODE ip @ jump to next instruction
7036 /* 10-12 instructions */
7037
7038/* ------------------------------ */
7039 .balign 128
7040.L_op_and_int_lit8: /* 0xdd */
7041/* File: arm/op_and_int_lit8.S */
7042/* File: arm/binopLit8.S */
7043 /*
7044 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7045 * that specifies an instruction that performs "result = r0 op r1".
7046 * This could be an ARM instruction or a function call. (If the result
7047 * comes back in a register other than r0, you can override "result".)
7048 *
7049 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7050 * vCC (r1). Useful for integer division and modulus.
7051 *
7052 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7053 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7054 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7055 */
7056 /* binop/lit8 vAA, vBB, #+CC */
7057 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
7058 mov r9, rINST, lsr #8 @ r9<- AA
7059 and r2, r3, #255 @ r2<- BB
7060 GET_VREG r0, r2 @ r0<- vBB
7061 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7062 .if 0
7063 @cmp r1, #0 @ is second operand zero?
7064 beq common_errDivideByZero
7065 .endif
7066 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7067
7068 @ optional op; may set condition codes
7069 and r0, r0, r1 @ r0<- op, r0-r3 changed
7070 GET_INST_OPCODE ip @ extract opcode from rINST
7071 SET_VREG r0, r9 @ vAA<- r0
7072 GOTO_OPCODE ip @ jump to next instruction
7073 /* 10-12 instructions */
7074
7075
7076/* ------------------------------ */
7077 .balign 128
7078.L_op_or_int_lit8: /* 0xde */
7079/* File: arm/op_or_int_lit8.S */
7080/* File: arm/binopLit8.S */
7081 /*
7082 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7083 * that specifies an instruction that performs "result = r0 op r1".
7084 * This could be an ARM instruction or a function call. (If the result
7085 * comes back in a register other than r0, you can override "result".)
7086 *
7087 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7088 * vCC (r1). Useful for integer division and modulus.
7089 *
7090 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7091 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7092 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7093 */
7094 /* binop/lit8 vAA, vBB, #+CC */
7095 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
7096 mov r9, rINST, lsr #8 @ r9<- AA
7097 and r2, r3, #255 @ r2<- BB
7098 GET_VREG r0, r2 @ r0<- vBB
7099 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7100 .if 0
7101 @cmp r1, #0 @ is second operand zero?
7102 beq common_errDivideByZero
7103 .endif
7104 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7105
7106 @ optional op; may set condition codes
7107 orr r0, r0, r1 @ r0<- op, r0-r3 changed
7108 GET_INST_OPCODE ip @ extract opcode from rINST
7109 SET_VREG r0, r9 @ vAA<- r0
7110 GOTO_OPCODE ip @ jump to next instruction
7111 /* 10-12 instructions */
7112
7113
7114/* ------------------------------ */
7115 .balign 128
7116.L_op_xor_int_lit8: /* 0xdf */
7117/* File: arm/op_xor_int_lit8.S */
7118/* File: arm/binopLit8.S */
7119 /*
7120 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7121 * that specifies an instruction that performs "result = r0 op r1".
7122 * This could be an ARM instruction or a function call. (If the result
7123 * comes back in a register other than r0, you can override "result".)
7124 *
7125 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7126 * vCC (r1). Useful for integer division and modulus.
7127 *
7128 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7129 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7130 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7131 */
7132 /* binop/lit8 vAA, vBB, #+CC */
7133 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
7134 mov r9, rINST, lsr #8 @ r9<- AA
7135 and r2, r3, #255 @ r2<- BB
7136 GET_VREG r0, r2 @ r0<- vBB
7137 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7138 .if 0
7139 @cmp r1, #0 @ is second operand zero?
7140 beq common_errDivideByZero
7141 .endif
7142 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7143
7144 @ optional op; may set condition codes
7145 eor r0, r0, r1 @ r0<- op, r0-r3 changed
7146 GET_INST_OPCODE ip @ extract opcode from rINST
7147 SET_VREG r0, r9 @ vAA<- r0
7148 GOTO_OPCODE ip @ jump to next instruction
7149 /* 10-12 instructions */
7150
7151
7152/* ------------------------------ */
7153 .balign 128
7154.L_op_shl_int_lit8: /* 0xe0 */
7155/* File: arm/op_shl_int_lit8.S */
7156/* File: arm/binopLit8.S */
7157 /*
7158 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7159 * that specifies an instruction that performs "result = r0 op r1".
7160 * This could be an ARM instruction or a function call. (If the result
7161 * comes back in a register other than r0, you can override "result".)
7162 *
7163 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7164 * vCC (r1). Useful for integer division and modulus.
7165 *
7166 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7167 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7168 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7169 */
7170 /* binop/lit8 vAA, vBB, #+CC */
7171 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
7172 mov r9, rINST, lsr #8 @ r9<- AA
7173 and r2, r3, #255 @ r2<- BB
7174 GET_VREG r0, r2 @ r0<- vBB
7175 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7176 .if 0
7177 @cmp r1, #0 @ is second operand zero?
7178 beq common_errDivideByZero
7179 .endif
7180 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7181
7182 and r1, r1, #31 @ optional op; may set condition codes
7183 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
7184 GET_INST_OPCODE ip @ extract opcode from rINST
7185 SET_VREG r0, r9 @ vAA<- r0
7186 GOTO_OPCODE ip @ jump to next instruction
7187 /* 10-12 instructions */
7188
7189
7190/* ------------------------------ */
7191 .balign 128
7192.L_op_shr_int_lit8: /* 0xe1 */
7193/* File: arm/op_shr_int_lit8.S */
7194/* File: arm/binopLit8.S */
7195 /*
7196 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7197 * that specifies an instruction that performs "result = r0 op r1".
7198 * This could be an ARM instruction or a function call. (If the result
7199 * comes back in a register other than r0, you can override "result".)
7200 *
7201 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7202 * vCC (r1). Useful for integer division and modulus.
7203 *
7204 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7205 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7206 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7207 */
7208 /* binop/lit8 vAA, vBB, #+CC */
7209 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
7210 mov r9, rINST, lsr #8 @ r9<- AA
7211 and r2, r3, #255 @ r2<- BB
7212 GET_VREG r0, r2 @ r0<- vBB
7213 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7214 .if 0
7215 @cmp r1, #0 @ is second operand zero?
7216 beq common_errDivideByZero
7217 .endif
7218 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7219
7220 and r1, r1, #31 @ optional op; may set condition codes
7221 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
7222 GET_INST_OPCODE ip @ extract opcode from rINST
7223 SET_VREG r0, r9 @ vAA<- r0
7224 GOTO_OPCODE ip @ jump to next instruction
7225 /* 10-12 instructions */
7226
7227
7228/* ------------------------------ */
7229 .balign 128
7230.L_op_ushr_int_lit8: /* 0xe2 */
7231/* File: arm/op_ushr_int_lit8.S */
7232/* File: arm/binopLit8.S */
7233 /*
7234 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7235 * that specifies an instruction that performs "result = r0 op r1".
7236 * This could be an ARM instruction or a function call. (If the result
7237 * comes back in a register other than r0, you can override "result".)
7238 *
7239 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7240 * vCC (r1). Useful for integer division and modulus.
7241 *
7242 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7243 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7244 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7245 */
7246 /* binop/lit8 vAA, vBB, #+CC */
7247 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC
7248 mov r9, rINST, lsr #8 @ r9<- AA
7249 and r2, r3, #255 @ r2<- BB
7250 GET_VREG r0, r2 @ r0<- vBB
7251 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7252 .if 0
7253 @cmp r1, #0 @ is second operand zero?
7254 beq common_errDivideByZero
7255 .endif
7256 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7257
7258 and r1, r1, #31 @ optional op; may set condition codes
7259 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
7260 GET_INST_OPCODE ip @ extract opcode from rINST
7261 SET_VREG r0, r9 @ vAA<- r0
7262 GOTO_OPCODE ip @ jump to next instruction
7263 /* 10-12 instructions */
7264
7265
7266/* ------------------------------ */
7267 .balign 128
7268.L_op_iget_quick: /* 0xe3 */
7269/* File: arm/op_iget_quick.S */
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7270 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7271 /* op vA, vB, offset@CCCC */
7272 mov r2, rINST, lsr #12 @ r2<- B
7273 FETCH r1, 1 @ r1<- field byte offset
7274 GET_VREG r3, r2 @ r3<- object we're operating on
7275 ubfx r2, rINST, #8, #4 @ r2<- A
7276 cmp r3, #0 @ check object for null
7277 beq common_errNullObject @ object was null
7278 ldr r0, [r3, r1] @ r0<- obj.field
7279 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7280 SET_VREG r0, r2 @ fp[A]<- r0
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7281 GET_INST_OPCODE ip @ extract opcode from rINST
7282 GOTO_OPCODE ip @ jump to next instruction
7283
7284/* ------------------------------ */
7285 .balign 128
7286.L_op_iget_wide_quick: /* 0xe4 */
7287/* File: arm/op_iget_wide_quick.S */
7288 /* iget-wide-quick vA, vB, offset@CCCC */
7289 mov r2, rINST, lsr #12 @ r2<- B
7290 FETCH ip, 1 @ ip<- field byte offset
7291 GET_VREG r3, r2 @ r3<- object we're operating on
7292 ubfx r2, rINST, #8, #4 @ r2<- A
7293 cmp r3, #0 @ check object for null
7294 beq common_errNullObject @ object was null
7295 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned)
7296 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7297 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
7298 GET_INST_OPCODE ip @ extract opcode from rINST
7299 stmia r3, {r0-r1} @ fp[A]<- r0/r1
7300 GOTO_OPCODE ip @ jump to next instruction
7301
7302/* ------------------------------ */
7303 .balign 128
7304.L_op_iget_object_quick: /* 0xe5 */
7305/* File: arm/op_iget_object_quick.S */
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7306 /* For: iget-object-quick */
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7307 /* op vA, vB, offset@CCCC */
7308 mov r2, rINST, lsr #12 @ r2<- B
7309 FETCH r1, 1 @ r1<- field byte offset
buzbeebb6e7262016-01-14 05:34:34 -0800[diff] [blame]7310 EXPORT_PC
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7311 GET_VREG r0, r2 @ r0<- object we're operating on
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7312 bl artIGetObjectFromMterp @ (obj, offset)
7313 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
7314 ubfx r2, rINST, #8, #4 @ r2<- A
7315 PREFETCH_INST 2
7316 cmp r3, #0
7317 bne MterpPossibleException @ bail out
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7318 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7319 ADVANCE 2 @ advance rPC
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7320 GET_INST_OPCODE ip @ extract opcode from rINST
7321 GOTO_OPCODE ip @ jump to next instruction
7322
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7323/* ------------------------------ */
7324 .balign 128
7325.L_op_iput_quick: /* 0xe6 */
7326/* File: arm/op_iput_quick.S */
7327 /* For: iput-quick, iput-object-quick */
7328 /* op vA, vB, offset@CCCC */
7329 mov r2, rINST, lsr #12 @ r2<- B
7330 FETCH r1, 1 @ r1<- field byte offset
7331 GET_VREG r3, r2 @ r3<- fp[B], the object pointer
7332 ubfx r2, rINST, #8, #4 @ r2<- A
7333 cmp r3, #0 @ check object for null
7334 beq common_errNullObject @ object was null
7335 GET_VREG r0, r2 @ r0<- fp[A]
7336 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7337 str r0, [r3, r1] @ obj.field<- r0
7338 GET_INST_OPCODE ip @ extract opcode from rINST
7339 GOTO_OPCODE ip @ jump to next instruction
7340
7341/* ------------------------------ */
7342 .balign 128
7343.L_op_iput_wide_quick: /* 0xe7 */
7344/* File: arm/op_iput_wide_quick.S */
7345 /* iput-wide-quick vA, vB, offset@CCCC */
7346 mov r2, rINST, lsr #12 @ r2<- B
7347 FETCH r3, 1 @ r3<- field byte offset
7348 GET_VREG r2, r2 @ r2<- fp[B], the object pointer
7349 ubfx r0, rINST, #8, #4 @ r0<- A
7350 cmp r2, #0 @ check object for null
7351 beq common_errNullObject @ object was null
7352 add r0, rFP, r0, lsl #2 @ r0<- &fp[A]
7353 ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1]
7354 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7355 strd r0, [r2, r3] @ obj.field<- r0/r1
7356 GET_INST_OPCODE ip @ extract opcode from rINST
7357 GOTO_OPCODE ip @ jump to next instruction
7358
7359/* ------------------------------ */
7360 .balign 128
7361.L_op_iput_object_quick: /* 0xe8 */
7362/* File: arm/op_iput_object_quick.S */
7363 EXPORT_PC
7364 add r0, rFP, #OFF_FP_SHADOWFRAME
7365 mov r1, rPC
7366 mov r2, rINST
7367 bl MterpIputObjectQuick
7368 cmp r0, #0
7369 beq MterpException
7370 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7371 GET_INST_OPCODE ip @ extract opcode from rINST
7372 GOTO_OPCODE ip @ jump to next instruction
7373
7374/* ------------------------------ */
7375 .balign 128
7376.L_op_invoke_virtual_quick: /* 0xe9 */
7377/* File: arm/op_invoke_virtual_quick.S */
7378/* File: arm/invoke.S */
7379 /*
7380 * Generic invoke handler wrapper.
7381 */
7382 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7383 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7384 .extern MterpInvokeVirtualQuick
7385 EXPORT_PC
7386 mov r0, rSELF
7387 add r1, rFP, #OFF_FP_SHADOWFRAME
7388 mov r2, rPC
7389 mov r3, rINST
7390 bl MterpInvokeVirtualQuick
7391 cmp r0, #0
7392 beq MterpException
7393 FETCH_ADVANCE_INST 3
7394 GET_INST_OPCODE ip
7395 GOTO_OPCODE ip
7396
7397
7398
7399/* ------------------------------ */
7400 .balign 128
7401.L_op_invoke_virtual_range_quick: /* 0xea */
7402/* File: arm/op_invoke_virtual_range_quick.S */
7403/* File: arm/invoke.S */
7404 /*
7405 * Generic invoke handler wrapper.
7406 */
7407 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7408 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7409 .extern MterpInvokeVirtualQuickRange
7410 EXPORT_PC
7411 mov r0, rSELF
7412 add r1, rFP, #OFF_FP_SHADOWFRAME
7413 mov r2, rPC
7414 mov r3, rINST
7415 bl MterpInvokeVirtualQuickRange
7416 cmp r0, #0
7417 beq MterpException
7418 FETCH_ADVANCE_INST 3
7419 GET_INST_OPCODE ip
7420 GOTO_OPCODE ip
7421
7422
7423
7424/* ------------------------------ */
7425 .balign 128
7426.L_op_iput_boolean_quick: /* 0xeb */
7427/* File: arm/op_iput_boolean_quick.S */
7428/* File: arm/op_iput_quick.S */
7429 /* For: iput-quick, iput-object-quick */
7430 /* op vA, vB, offset@CCCC */
7431 mov r2, rINST, lsr #12 @ r2<- B
7432 FETCH r1, 1 @ r1<- field byte offset
7433 GET_VREG r3, r2 @ r3<- fp[B], the object pointer
7434 ubfx r2, rINST, #8, #4 @ r2<- A
7435 cmp r3, #0 @ check object for null
7436 beq common_errNullObject @ object was null
7437 GET_VREG r0, r2 @ r0<- fp[A]
7438 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7439 strb r0, [r3, r1] @ obj.field<- r0
7440 GET_INST_OPCODE ip @ extract opcode from rINST
7441 GOTO_OPCODE ip @ jump to next instruction
7442
7443
7444/* ------------------------------ */
7445 .balign 128
7446.L_op_iput_byte_quick: /* 0xec */
7447/* File: arm/op_iput_byte_quick.S */
7448/* File: arm/op_iput_quick.S */
7449 /* For: iput-quick, iput-object-quick */
7450 /* op vA, vB, offset@CCCC */
7451 mov r2, rINST, lsr #12 @ r2<- B
7452 FETCH r1, 1 @ r1<- field byte offset
7453 GET_VREG r3, r2 @ r3<- fp[B], the object pointer
7454 ubfx r2, rINST, #8, #4 @ r2<- A
7455 cmp r3, #0 @ check object for null
7456 beq common_errNullObject @ object was null
7457 GET_VREG r0, r2 @ r0<- fp[A]
7458 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7459 strb r0, [r3, r1] @ obj.field<- r0
7460 GET_INST_OPCODE ip @ extract opcode from rINST
7461 GOTO_OPCODE ip @ jump to next instruction
7462
7463
7464/* ------------------------------ */
7465 .balign 128
7466.L_op_iput_char_quick: /* 0xed */
7467/* File: arm/op_iput_char_quick.S */
7468/* File: arm/op_iput_quick.S */
7469 /* For: iput-quick, iput-object-quick */
7470 /* op vA, vB, offset@CCCC */
7471 mov r2, rINST, lsr #12 @ r2<- B
7472 FETCH r1, 1 @ r1<- field byte offset
7473 GET_VREG r3, r2 @ r3<- fp[B], the object pointer
7474 ubfx r2, rINST, #8, #4 @ r2<- A
7475 cmp r3, #0 @ check object for null
7476 beq common_errNullObject @ object was null
7477 GET_VREG r0, r2 @ r0<- fp[A]
7478 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7479 strh r0, [r3, r1] @ obj.field<- r0
7480 GET_INST_OPCODE ip @ extract opcode from rINST
7481 GOTO_OPCODE ip @ jump to next instruction
7482
7483
7484/* ------------------------------ */
7485 .balign 128
7486.L_op_iput_short_quick: /* 0xee */
7487/* File: arm/op_iput_short_quick.S */
7488/* File: arm/op_iput_quick.S */
7489 /* For: iput-quick, iput-object-quick */
7490 /* op vA, vB, offset@CCCC */
7491 mov r2, rINST, lsr #12 @ r2<- B
7492 FETCH r1, 1 @ r1<- field byte offset
7493 GET_VREG r3, r2 @ r3<- fp[B], the object pointer
7494 ubfx r2, rINST, #8, #4 @ r2<- A
7495 cmp r3, #0 @ check object for null
7496 beq common_errNullObject @ object was null
7497 GET_VREG r0, r2 @ r0<- fp[A]
7498 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7499 strh r0, [r3, r1] @ obj.field<- r0
7500 GET_INST_OPCODE ip @ extract opcode from rINST
7501 GOTO_OPCODE ip @ jump to next instruction
7502
7503
7504/* ------------------------------ */
7505 .balign 128
7506.L_op_iget_boolean_quick: /* 0xef */
7507/* File: arm/op_iget_boolean_quick.S */
7508/* File: arm/op_iget_quick.S */
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7509 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7510 /* op vA, vB, offset@CCCC */
7511 mov r2, rINST, lsr #12 @ r2<- B
7512 FETCH r1, 1 @ r1<- field byte offset
7513 GET_VREG r3, r2 @ r3<- object we're operating on
7514 ubfx r2, rINST, #8, #4 @ r2<- A
7515 cmp r3, #0 @ check object for null
7516 beq common_errNullObject @ object was null
7517 ldrb r0, [r3, r1] @ r0<- obj.field
7518 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7519 SET_VREG r0, r2 @ fp[A]<- r0
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7520 GET_INST_OPCODE ip @ extract opcode from rINST
7521 GOTO_OPCODE ip @ jump to next instruction
7522
7523
7524/* ------------------------------ */
7525 .balign 128
7526.L_op_iget_byte_quick: /* 0xf0 */
7527/* File: arm/op_iget_byte_quick.S */
7528/* File: arm/op_iget_quick.S */
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7529 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7530 /* op vA, vB, offset@CCCC */
7531 mov r2, rINST, lsr #12 @ r2<- B
7532 FETCH r1, 1 @ r1<- field byte offset
7533 GET_VREG r3, r2 @ r3<- object we're operating on
7534 ubfx r2, rINST, #8, #4 @ r2<- A
7535 cmp r3, #0 @ check object for null
7536 beq common_errNullObject @ object was null
7537 ldrsb r0, [r3, r1] @ r0<- obj.field
7538 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7539 SET_VREG r0, r2 @ fp[A]<- r0
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7540 GET_INST_OPCODE ip @ extract opcode from rINST
7541 GOTO_OPCODE ip @ jump to next instruction
7542
7543
7544/* ------------------------------ */
7545 .balign 128
7546.L_op_iget_char_quick: /* 0xf1 */
7547/* File: arm/op_iget_char_quick.S */
7548/* File: arm/op_iget_quick.S */
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7549 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7550 /* op vA, vB, offset@CCCC */
7551 mov r2, rINST, lsr #12 @ r2<- B
7552 FETCH r1, 1 @ r1<- field byte offset
7553 GET_VREG r3, r2 @ r3<- object we're operating on
7554 ubfx r2, rINST, #8, #4 @ r2<- A
7555 cmp r3, #0 @ check object for null
7556 beq common_errNullObject @ object was null
7557 ldrh r0, [r3, r1] @ r0<- obj.field
7558 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7559 SET_VREG r0, r2 @ fp[A]<- r0
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7560 GET_INST_OPCODE ip @ extract opcode from rINST
7561 GOTO_OPCODE ip @ jump to next instruction
7562
7563
7564/* ------------------------------ */
7565 .balign 128
7566.L_op_iget_short_quick: /* 0xf2 */
7567/* File: arm/op_iget_short_quick.S */
7568/* File: arm/op_iget_quick.S */
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]7569 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7570 /* op vA, vB, offset@CCCC */
7571 mov r2, rINST, lsr #12 @ r2<- B
7572 FETCH r1, 1 @ r1<- field byte offset
7573 GET_VREG r3, r2 @ r3<- object we're operating on
7574 ubfx r2, rINST, #8, #4 @ r2<- A
7575 cmp r3, #0 @ check object for null
7576 beq common_errNullObject @ object was null
7577 ldrsh r0, [r3, r1] @ r0<- obj.field
7578 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7579 SET_VREG r0, r2 @ fp[A]<- r0
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]7580 GET_INST_OPCODE ip @ extract opcode from rINST
7581 GOTO_OPCODE ip @ jump to next instruction
7582
7583
7584/* ------------------------------ */
7585 .balign 128
7586.L_op_invoke_lambda: /* 0xf3 */
7587/* Transfer stub to alternate interpreter */
7588 b MterpFallback
7589
7590
7591/* ------------------------------ */
7592 .balign 128
7593.L_op_unused_f4: /* 0xf4 */
7594/* File: arm/op_unused_f4.S */
7595/* File: arm/unused.S */
7596/*
7597 * Bail to reference interpreter to throw.
7598 */
7599 b MterpFallback
7600
7601
7602/* ------------------------------ */
7603 .balign 128
7604.L_op_capture_variable: /* 0xf5 */
7605/* Transfer stub to alternate interpreter */
7606 b MterpFallback
7607
7608
7609/* ------------------------------ */
7610 .balign 128
7611.L_op_create_lambda: /* 0xf6 */
7612/* Transfer stub to alternate interpreter */
7613 b MterpFallback
7614
7615
7616/* ------------------------------ */
7617 .balign 128
7618.L_op_liberate_variable: /* 0xf7 */
7619/* Transfer stub to alternate interpreter */
7620 b MterpFallback
7621
7622
7623/* ------------------------------ */
7624 .balign 128
7625.L_op_box_lambda: /* 0xf8 */
7626/* Transfer stub to alternate interpreter */
7627 b MterpFallback
7628
7629
7630/* ------------------------------ */
7631 .balign 128
7632.L_op_unbox_lambda: /* 0xf9 */
7633/* Transfer stub to alternate interpreter */
7634 b MterpFallback
7635
7636
7637/* ------------------------------ */
7638 .balign 128
7639.L_op_unused_fa: /* 0xfa */
7640/* File: arm/op_unused_fa.S */
7641/* File: arm/unused.S */
7642/*
7643 * Bail to reference interpreter to throw.
7644 */
7645 b MterpFallback
7646
7647
7648/* ------------------------------ */
7649 .balign 128
7650.L_op_unused_fb: /* 0xfb */
7651/* File: arm/op_unused_fb.S */
7652/* File: arm/unused.S */
7653/*
7654 * Bail to reference interpreter to throw.
7655 */
7656 b MterpFallback
7657
7658
7659/* ------------------------------ */
7660 .balign 128
7661.L_op_unused_fc: /* 0xfc */
7662/* File: arm/op_unused_fc.S */
7663/* File: arm/unused.S */
7664/*
7665 * Bail to reference interpreter to throw.
7666 */
7667 b MterpFallback
7668
7669
7670/* ------------------------------ */
7671 .balign 128
7672.L_op_unused_fd: /* 0xfd */
7673/* File: arm/op_unused_fd.S */
7674/* File: arm/unused.S */
7675/*
7676 * Bail to reference interpreter to throw.
7677 */
7678 b MterpFallback
7679
7680
7681/* ------------------------------ */
7682 .balign 128
7683.L_op_unused_fe: /* 0xfe */
7684/* File: arm/op_unused_fe.S */
7685/* File: arm/unused.S */
7686/*
7687 * Bail to reference interpreter to throw.
7688 */
7689 b MterpFallback
7690
7691
7692/* ------------------------------ */
7693 .balign 128
7694.L_op_unused_ff: /* 0xff */
7695/* File: arm/op_unused_ff.S */
7696/* File: arm/unused.S */
7697/*
7698 * Bail to reference interpreter to throw.
7699 */
7700 b MterpFallback
7701
7702
7703 .balign 128
7704 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart
7705 .global artMterpAsmInstructionEnd
7706artMterpAsmInstructionEnd:
7707
7708/*
7709 * ===========================================================================
7710 * Sister implementations
7711 * ===========================================================================
7712 */
7713 .global artMterpAsmSisterStart
7714 .type artMterpAsmSisterStart, %function
7715 .text
7716 .balign 4
7717artMterpAsmSisterStart:
7718
7719/* continuation for op_cmp_long */
7720
7721.Lop_cmp_long_less:
7722 mvn r1, #0 @ r1<- -1
7723 @ Want to cond code the next mov so we can avoid branch, but don't see it;
7724 @ instead, we just replicate the tail end.
7725 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7726 SET_VREG r1, r9 @ vAA<- r1
7727 GET_INST_OPCODE ip @ extract opcode from rINST
7728 GOTO_OPCODE ip @ jump to next instruction
7729
7730.Lop_cmp_long_greater:
7731 mov r1, #1 @ r1<- 1
7732 @ fall through to _finish
7733
7734.Lop_cmp_long_finish:
7735 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
7736 SET_VREG r1, r9 @ vAA<- r1
7737 GET_INST_OPCODE ip @ extract opcode from rINST
7738 GOTO_OPCODE ip @ jump to next instruction
7739
7740/* continuation for op_float_to_long */
7741/*
7742 * Convert the float in r0 to a long in r0/r1.
7743 *
7744 * We have to clip values to long min/max per the specification. The
7745 * expected common case is a "reasonable" value that converts directly
7746 * to modest integer. The EABI convert function isn't doing this for us.
7747 */
7748f2l_doconv:
7749 stmfd sp!, {r4, lr}
7750 mov r1, #0x5f000000 @ (float)maxlong
7751 mov r4, r0
7752 bl __aeabi_fcmpge @ is arg >= maxlong?
7753 cmp r0, #0 @ nonzero == yes
7754 mvnne r0, #0 @ return maxlong (7fffffff)
7755 mvnne r1, #0x80000000
7756 ldmnefd sp!, {r4, pc}
7757
7758 mov r0, r4 @ recover arg
7759 mov r1, #0xdf000000 @ (float)minlong
7760 bl __aeabi_fcmple @ is arg <= minlong?
7761 cmp r0, #0 @ nonzero == yes
7762 movne r0, #0 @ return minlong (80000000)
7763 movne r1, #0x80000000
7764 ldmnefd sp!, {r4, pc}
7765
7766 mov r0, r4 @ recover arg
7767 mov r1, r4
7768 bl __aeabi_fcmpeq @ is arg == self?
7769 cmp r0, #0 @ zero == no
7770 moveq r1, #0 @ return zero for NaN
7771 ldmeqfd sp!, {r4, pc}
7772
7773 mov r0, r4 @ recover arg
7774 bl __aeabi_f2lz @ convert float to long
7775 ldmfd sp!, {r4, pc}
7776
7777/* continuation for op_double_to_long */
7778/*
7779 * Convert the double in r0/r1 to a long in r0/r1.
7780 *
7781 * We have to clip values to long min/max per the specification. The
7782 * expected common case is a "reasonable" value that converts directly
7783 * to modest integer. The EABI convert function isn't doing this for us.
7784 */
7785d2l_doconv:
7786 stmfd sp!, {r4, r5, lr} @ save regs
7787 mov r3, #0x43000000 @ maxlong, as a double (high word)
7788 add r3, #0x00e00000 @ 0x43e00000
7789 mov r2, #0 @ maxlong, as a double (low word)
7790 sub sp, sp, #4 @ align for EABI
7791 mov r4, r0 @ save a copy of r0
7792 mov r5, r1 @ and r1
7793 bl __aeabi_dcmpge @ is arg >= maxlong?
7794 cmp r0, #0 @ nonzero == yes
7795 mvnne r0, #0 @ return maxlong (7fffffffffffffff)
7796 mvnne r1, #0x80000000
7797 bne 1f
7798
7799 mov r0, r4 @ recover arg
7800 mov r1, r5
7801 mov r3, #0xc3000000 @ minlong, as a double (high word)
7802 add r3, #0x00e00000 @ 0xc3e00000
7803 mov r2, #0 @ minlong, as a double (low word)
7804 bl __aeabi_dcmple @ is arg <= minlong?
7805 cmp r0, #0 @ nonzero == yes
7806 movne r0, #0 @ return minlong (8000000000000000)
7807 movne r1, #0x80000000
7808 bne 1f
7809
7810 mov r0, r4 @ recover arg
7811 mov r1, r5
7812 mov r2, r4 @ compare against self
7813 mov r3, r5
7814 bl __aeabi_dcmpeq @ is arg == self?
7815 cmp r0, #0 @ zero == no
7816 moveq r1, #0 @ return zero for NaN
7817 beq 1f
7818
7819 mov r0, r4 @ recover arg
7820 mov r1, r5
7821 bl __aeabi_d2lz @ convert double to long
7822
78231:
7824 add sp, sp, #4
7825 ldmfd sp!, {r4, r5, pc}
7826
7827 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart
7828 .global artMterpAsmSisterEnd
7829artMterpAsmSisterEnd:
7830
7831
7832 .global artMterpAsmAltInstructionStart
7833 .type artMterpAsmAltInstructionStart, %function
7834 .text
7835
7836artMterpAsmAltInstructionStart = .L_ALT_op_nop
7837/* ------------------------------ */
7838 .balign 128
7839.L_ALT_op_nop: /* 0x00 */
7840/* File: arm/alt_stub.S */
7841/*
7842 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7843 * any interesting requests and then jump to the real instruction
7844 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7845 */
7846 .extern MterpCheckBefore
7847 EXPORT_PC
7848 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7849 adrl lr, artMterpAsmInstructionStart + (0 * 128) @ Addr of primary handler.
7850 mov r0, rSELF
7851 add r1, rFP, #OFF_FP_SHADOWFRAME
7852 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7853
7854/* ------------------------------ */
7855 .balign 128
7856.L_ALT_op_move: /* 0x01 */
7857/* File: arm/alt_stub.S */
7858/*
7859 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7860 * any interesting requests and then jump to the real instruction
7861 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7862 */
7863 .extern MterpCheckBefore
7864 EXPORT_PC
7865 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7866 adrl lr, artMterpAsmInstructionStart + (1 * 128) @ Addr of primary handler.
7867 mov r0, rSELF
7868 add r1, rFP, #OFF_FP_SHADOWFRAME
7869 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7870
7871/* ------------------------------ */
7872 .balign 128
7873.L_ALT_op_move_from16: /* 0x02 */
7874/* File: arm/alt_stub.S */
7875/*
7876 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7877 * any interesting requests and then jump to the real instruction
7878 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7879 */
7880 .extern MterpCheckBefore
7881 EXPORT_PC
7882 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7883 adrl lr, artMterpAsmInstructionStart + (2 * 128) @ Addr of primary handler.
7884 mov r0, rSELF
7885 add r1, rFP, #OFF_FP_SHADOWFRAME
7886 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7887
7888/* ------------------------------ */
7889 .balign 128
7890.L_ALT_op_move_16: /* 0x03 */
7891/* File: arm/alt_stub.S */
7892/*
7893 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7894 * any interesting requests and then jump to the real instruction
7895 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7896 */
7897 .extern MterpCheckBefore
7898 EXPORT_PC
7899 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7900 adrl lr, artMterpAsmInstructionStart + (3 * 128) @ Addr of primary handler.
7901 mov r0, rSELF
7902 add r1, rFP, #OFF_FP_SHADOWFRAME
7903 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7904
7905/* ------------------------------ */
7906 .balign 128
7907.L_ALT_op_move_wide: /* 0x04 */
7908/* File: arm/alt_stub.S */
7909/*
7910 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7911 * any interesting requests and then jump to the real instruction
7912 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7913 */
7914 .extern MterpCheckBefore
7915 EXPORT_PC
7916 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7917 adrl lr, artMterpAsmInstructionStart + (4 * 128) @ Addr of primary handler.
7918 mov r0, rSELF
7919 add r1, rFP, #OFF_FP_SHADOWFRAME
7920 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7921
7922/* ------------------------------ */
7923 .balign 128
7924.L_ALT_op_move_wide_from16: /* 0x05 */
7925/* File: arm/alt_stub.S */
7926/*
7927 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7928 * any interesting requests and then jump to the real instruction
7929 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7930 */
7931 .extern MterpCheckBefore
7932 EXPORT_PC
7933 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7934 adrl lr, artMterpAsmInstructionStart + (5 * 128) @ Addr of primary handler.
7935 mov r0, rSELF
7936 add r1, rFP, #OFF_FP_SHADOWFRAME
7937 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7938
7939/* ------------------------------ */
7940 .balign 128
7941.L_ALT_op_move_wide_16: /* 0x06 */
7942/* File: arm/alt_stub.S */
7943/*
7944 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7945 * any interesting requests and then jump to the real instruction
7946 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7947 */
7948 .extern MterpCheckBefore
7949 EXPORT_PC
7950 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7951 adrl lr, artMterpAsmInstructionStart + (6 * 128) @ Addr of primary handler.
7952 mov r0, rSELF
7953 add r1, rFP, #OFF_FP_SHADOWFRAME
7954 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7955
7956/* ------------------------------ */
7957 .balign 128
7958.L_ALT_op_move_object: /* 0x07 */
7959/* File: arm/alt_stub.S */
7960/*
7961 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7962 * any interesting requests and then jump to the real instruction
7963 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7964 */
7965 .extern MterpCheckBefore
7966 EXPORT_PC
7967 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7968 adrl lr, artMterpAsmInstructionStart + (7 * 128) @ Addr of primary handler.
7969 mov r0, rSELF
7970 add r1, rFP, #OFF_FP_SHADOWFRAME
7971 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7972
7973/* ------------------------------ */
7974 .balign 128
7975.L_ALT_op_move_object_from16: /* 0x08 */
7976/* File: arm/alt_stub.S */
7977/*
7978 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7979 * any interesting requests and then jump to the real instruction
7980 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7981 */
7982 .extern MterpCheckBefore
7983 EXPORT_PC
7984 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
7985 adrl lr, artMterpAsmInstructionStart + (8 * 128) @ Addr of primary handler.
7986 mov r0, rSELF
7987 add r1, rFP, #OFF_FP_SHADOWFRAME
7988 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
7989
7990/* ------------------------------ */
7991 .balign 128
7992.L_ALT_op_move_object_16: /* 0x09 */
7993/* File: arm/alt_stub.S */
7994/*
7995 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7996 * any interesting requests and then jump to the real instruction
7997 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7998 */
7999 .extern MterpCheckBefore
8000 EXPORT_PC
8001 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8002 adrl lr, artMterpAsmInstructionStart + (9 * 128) @ Addr of primary handler.
8003 mov r0, rSELF
8004 add r1, rFP, #OFF_FP_SHADOWFRAME
8005 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8006
8007/* ------------------------------ */
8008 .balign 128
8009.L_ALT_op_move_result: /* 0x0a */
8010/* File: arm/alt_stub.S */
8011/*
8012 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8013 * any interesting requests and then jump to the real instruction
8014 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8015 */
8016 .extern MterpCheckBefore
8017 EXPORT_PC
8018 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8019 adrl lr, artMterpAsmInstructionStart + (10 * 128) @ Addr of primary handler.
8020 mov r0, rSELF
8021 add r1, rFP, #OFF_FP_SHADOWFRAME
8022 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8023
8024/* ------------------------------ */
8025 .balign 128
8026.L_ALT_op_move_result_wide: /* 0x0b */
8027/* File: arm/alt_stub.S */
8028/*
8029 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8030 * any interesting requests and then jump to the real instruction
8031 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8032 */
8033 .extern MterpCheckBefore
8034 EXPORT_PC
8035 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8036 adrl lr, artMterpAsmInstructionStart + (11 * 128) @ Addr of primary handler.
8037 mov r0, rSELF
8038 add r1, rFP, #OFF_FP_SHADOWFRAME
8039 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8040
8041/* ------------------------------ */
8042 .balign 128
8043.L_ALT_op_move_result_object: /* 0x0c */
8044/* File: arm/alt_stub.S */
8045/*
8046 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8047 * any interesting requests and then jump to the real instruction
8048 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8049 */
8050 .extern MterpCheckBefore
8051 EXPORT_PC
8052 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8053 adrl lr, artMterpAsmInstructionStart + (12 * 128) @ Addr of primary handler.
8054 mov r0, rSELF
8055 add r1, rFP, #OFF_FP_SHADOWFRAME
8056 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8057
8058/* ------------------------------ */
8059 .balign 128
8060.L_ALT_op_move_exception: /* 0x0d */
8061/* File: arm/alt_stub.S */
8062/*
8063 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8064 * any interesting requests and then jump to the real instruction
8065 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8066 */
8067 .extern MterpCheckBefore
8068 EXPORT_PC
8069 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8070 adrl lr, artMterpAsmInstructionStart + (13 * 128) @ Addr of primary handler.
8071 mov r0, rSELF
8072 add r1, rFP, #OFF_FP_SHADOWFRAME
8073 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8074
8075/* ------------------------------ */
8076 .balign 128
8077.L_ALT_op_return_void: /* 0x0e */
8078/* File: arm/alt_stub.S */
8079/*
8080 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8081 * any interesting requests and then jump to the real instruction
8082 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8083 */
8084 .extern MterpCheckBefore
8085 EXPORT_PC
8086 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8087 adrl lr, artMterpAsmInstructionStart + (14 * 128) @ Addr of primary handler.
8088 mov r0, rSELF
8089 add r1, rFP, #OFF_FP_SHADOWFRAME
8090 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8091
8092/* ------------------------------ */
8093 .balign 128
8094.L_ALT_op_return: /* 0x0f */
8095/* File: arm/alt_stub.S */
8096/*
8097 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8098 * any interesting requests and then jump to the real instruction
8099 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8100 */
8101 .extern MterpCheckBefore
8102 EXPORT_PC
8103 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8104 adrl lr, artMterpAsmInstructionStart + (15 * 128) @ Addr of primary handler.
8105 mov r0, rSELF
8106 add r1, rFP, #OFF_FP_SHADOWFRAME
8107 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8108
8109/* ------------------------------ */
8110 .balign 128
8111.L_ALT_op_return_wide: /* 0x10 */
8112/* File: arm/alt_stub.S */
8113/*
8114 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8115 * any interesting requests and then jump to the real instruction
8116 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8117 */
8118 .extern MterpCheckBefore
8119 EXPORT_PC
8120 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8121 adrl lr, artMterpAsmInstructionStart + (16 * 128) @ Addr of primary handler.
8122 mov r0, rSELF
8123 add r1, rFP, #OFF_FP_SHADOWFRAME
8124 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8125
8126/* ------------------------------ */
8127 .balign 128
8128.L_ALT_op_return_object: /* 0x11 */
8129/* File: arm/alt_stub.S */
8130/*
8131 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8132 * any interesting requests and then jump to the real instruction
8133 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8134 */
8135 .extern MterpCheckBefore
8136 EXPORT_PC
8137 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8138 adrl lr, artMterpAsmInstructionStart + (17 * 128) @ Addr of primary handler.
8139 mov r0, rSELF
8140 add r1, rFP, #OFF_FP_SHADOWFRAME
8141 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8142
8143/* ------------------------------ */
8144 .balign 128
8145.L_ALT_op_const_4: /* 0x12 */
8146/* File: arm/alt_stub.S */
8147/*
8148 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8149 * any interesting requests and then jump to the real instruction
8150 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8151 */
8152 .extern MterpCheckBefore
8153 EXPORT_PC
8154 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8155 adrl lr, artMterpAsmInstructionStart + (18 * 128) @ Addr of primary handler.
8156 mov r0, rSELF
8157 add r1, rFP, #OFF_FP_SHADOWFRAME
8158 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8159
8160/* ------------------------------ */
8161 .balign 128
8162.L_ALT_op_const_16: /* 0x13 */
8163/* File: arm/alt_stub.S */
8164/*
8165 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8166 * any interesting requests and then jump to the real instruction
8167 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8168 */
8169 .extern MterpCheckBefore
8170 EXPORT_PC
8171 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8172 adrl lr, artMterpAsmInstructionStart + (19 * 128) @ Addr of primary handler.
8173 mov r0, rSELF
8174 add r1, rFP, #OFF_FP_SHADOWFRAME
8175 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8176
8177/* ------------------------------ */
8178 .balign 128
8179.L_ALT_op_const: /* 0x14 */
8180/* File: arm/alt_stub.S */
8181/*
8182 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8183 * any interesting requests and then jump to the real instruction
8184 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8185 */
8186 .extern MterpCheckBefore
8187 EXPORT_PC
8188 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8189 adrl lr, artMterpAsmInstructionStart + (20 * 128) @ Addr of primary handler.
8190 mov r0, rSELF
8191 add r1, rFP, #OFF_FP_SHADOWFRAME
8192 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8193
8194/* ------------------------------ */
8195 .balign 128
8196.L_ALT_op_const_high16: /* 0x15 */
8197/* File: arm/alt_stub.S */
8198/*
8199 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8200 * any interesting requests and then jump to the real instruction
8201 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8202 */
8203 .extern MterpCheckBefore
8204 EXPORT_PC
8205 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8206 adrl lr, artMterpAsmInstructionStart + (21 * 128) @ Addr of primary handler.
8207 mov r0, rSELF
8208 add r1, rFP, #OFF_FP_SHADOWFRAME
8209 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8210
8211/* ------------------------------ */
8212 .balign 128
8213.L_ALT_op_const_wide_16: /* 0x16 */
8214/* File: arm/alt_stub.S */
8215/*
8216 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8217 * any interesting requests and then jump to the real instruction
8218 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8219 */
8220 .extern MterpCheckBefore
8221 EXPORT_PC
8222 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8223 adrl lr, artMterpAsmInstructionStart + (22 * 128) @ Addr of primary handler.
8224 mov r0, rSELF
8225 add r1, rFP, #OFF_FP_SHADOWFRAME
8226 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8227
8228/* ------------------------------ */
8229 .balign 128
8230.L_ALT_op_const_wide_32: /* 0x17 */
8231/* File: arm/alt_stub.S */
8232/*
8233 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8234 * any interesting requests and then jump to the real instruction
8235 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8236 */
8237 .extern MterpCheckBefore
8238 EXPORT_PC
8239 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8240 adrl lr, artMterpAsmInstructionStart + (23 * 128) @ Addr of primary handler.
8241 mov r0, rSELF
8242 add r1, rFP, #OFF_FP_SHADOWFRAME
8243 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8244
8245/* ------------------------------ */
8246 .balign 128
8247.L_ALT_op_const_wide: /* 0x18 */
8248/* File: arm/alt_stub.S */
8249/*
8250 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8251 * any interesting requests and then jump to the real instruction
8252 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8253 */
8254 .extern MterpCheckBefore
8255 EXPORT_PC
8256 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8257 adrl lr, artMterpAsmInstructionStart + (24 * 128) @ Addr of primary handler.
8258 mov r0, rSELF
8259 add r1, rFP, #OFF_FP_SHADOWFRAME
8260 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8261
8262/* ------------------------------ */
8263 .balign 128
8264.L_ALT_op_const_wide_high16: /* 0x19 */
8265/* File: arm/alt_stub.S */
8266/*
8267 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8268 * any interesting requests and then jump to the real instruction
8269 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8270 */
8271 .extern MterpCheckBefore
8272 EXPORT_PC
8273 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8274 adrl lr, artMterpAsmInstructionStart + (25 * 128) @ Addr of primary handler.
8275 mov r0, rSELF
8276 add r1, rFP, #OFF_FP_SHADOWFRAME
8277 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8278
8279/* ------------------------------ */
8280 .balign 128
8281.L_ALT_op_const_string: /* 0x1a */
8282/* File: arm/alt_stub.S */
8283/*
8284 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8285 * any interesting requests and then jump to the real instruction
8286 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8287 */
8288 .extern MterpCheckBefore
8289 EXPORT_PC
8290 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8291 adrl lr, artMterpAsmInstructionStart + (26 * 128) @ Addr of primary handler.
8292 mov r0, rSELF
8293 add r1, rFP, #OFF_FP_SHADOWFRAME
8294 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8295
8296/* ------------------------------ */
8297 .balign 128
8298.L_ALT_op_const_string_jumbo: /* 0x1b */
8299/* File: arm/alt_stub.S */
8300/*
8301 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8302 * any interesting requests and then jump to the real instruction
8303 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8304 */
8305 .extern MterpCheckBefore
8306 EXPORT_PC
8307 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8308 adrl lr, artMterpAsmInstructionStart + (27 * 128) @ Addr of primary handler.
8309 mov r0, rSELF
8310 add r1, rFP, #OFF_FP_SHADOWFRAME
8311 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8312
8313/* ------------------------------ */
8314 .balign 128
8315.L_ALT_op_const_class: /* 0x1c */
8316/* File: arm/alt_stub.S */
8317/*
8318 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8319 * any interesting requests and then jump to the real instruction
8320 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8321 */
8322 .extern MterpCheckBefore
8323 EXPORT_PC
8324 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8325 adrl lr, artMterpAsmInstructionStart + (28 * 128) @ Addr of primary handler.
8326 mov r0, rSELF
8327 add r1, rFP, #OFF_FP_SHADOWFRAME
8328 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8329
8330/* ------------------------------ */
8331 .balign 128
8332.L_ALT_op_monitor_enter: /* 0x1d */
8333/* File: arm/alt_stub.S */
8334/*
8335 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8336 * any interesting requests and then jump to the real instruction
8337 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8338 */
8339 .extern MterpCheckBefore
8340 EXPORT_PC
8341 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8342 adrl lr, artMterpAsmInstructionStart + (29 * 128) @ Addr of primary handler.
8343 mov r0, rSELF
8344 add r1, rFP, #OFF_FP_SHADOWFRAME
8345 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8346
8347/* ------------------------------ */
8348 .balign 128
8349.L_ALT_op_monitor_exit: /* 0x1e */
8350/* File: arm/alt_stub.S */
8351/*
8352 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8353 * any interesting requests and then jump to the real instruction
8354 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8355 */
8356 .extern MterpCheckBefore
8357 EXPORT_PC
8358 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8359 adrl lr, artMterpAsmInstructionStart + (30 * 128) @ Addr of primary handler.
8360 mov r0, rSELF
8361 add r1, rFP, #OFF_FP_SHADOWFRAME
8362 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8363
8364/* ------------------------------ */
8365 .balign 128
8366.L_ALT_op_check_cast: /* 0x1f */
8367/* File: arm/alt_stub.S */
8368/*
8369 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8370 * any interesting requests and then jump to the real instruction
8371 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8372 */
8373 .extern MterpCheckBefore
8374 EXPORT_PC
8375 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8376 adrl lr, artMterpAsmInstructionStart + (31 * 128) @ Addr of primary handler.
8377 mov r0, rSELF
8378 add r1, rFP, #OFF_FP_SHADOWFRAME
8379 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8380
8381/* ------------------------------ */
8382 .balign 128
8383.L_ALT_op_instance_of: /* 0x20 */
8384/* File: arm/alt_stub.S */
8385/*
8386 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8387 * any interesting requests and then jump to the real instruction
8388 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8389 */
8390 .extern MterpCheckBefore
8391 EXPORT_PC
8392 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8393 adrl lr, artMterpAsmInstructionStart + (32 * 128) @ Addr of primary handler.
8394 mov r0, rSELF
8395 add r1, rFP, #OFF_FP_SHADOWFRAME
8396 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8397
8398/* ------------------------------ */
8399 .balign 128
8400.L_ALT_op_array_length: /* 0x21 */
8401/* File: arm/alt_stub.S */
8402/*
8403 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8404 * any interesting requests and then jump to the real instruction
8405 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8406 */
8407 .extern MterpCheckBefore
8408 EXPORT_PC
8409 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8410 adrl lr, artMterpAsmInstructionStart + (33 * 128) @ Addr of primary handler.
8411 mov r0, rSELF
8412 add r1, rFP, #OFF_FP_SHADOWFRAME
8413 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8414
8415/* ------------------------------ */
8416 .balign 128
8417.L_ALT_op_new_instance: /* 0x22 */
8418/* File: arm/alt_stub.S */
8419/*
8420 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8421 * any interesting requests and then jump to the real instruction
8422 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8423 */
8424 .extern MterpCheckBefore
8425 EXPORT_PC
8426 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8427 adrl lr, artMterpAsmInstructionStart + (34 * 128) @ Addr of primary handler.
8428 mov r0, rSELF
8429 add r1, rFP, #OFF_FP_SHADOWFRAME
8430 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8431
8432/* ------------------------------ */
8433 .balign 128
8434.L_ALT_op_new_array: /* 0x23 */
8435/* File: arm/alt_stub.S */
8436/*
8437 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8438 * any interesting requests and then jump to the real instruction
8439 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8440 */
8441 .extern MterpCheckBefore
8442 EXPORT_PC
8443 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8444 adrl lr, artMterpAsmInstructionStart + (35 * 128) @ Addr of primary handler.
8445 mov r0, rSELF
8446 add r1, rFP, #OFF_FP_SHADOWFRAME
8447 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8448
8449/* ------------------------------ */
8450 .balign 128
8451.L_ALT_op_filled_new_array: /* 0x24 */
8452/* File: arm/alt_stub.S */
8453/*
8454 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8455 * any interesting requests and then jump to the real instruction
8456 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8457 */
8458 .extern MterpCheckBefore
8459 EXPORT_PC
8460 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8461 adrl lr, artMterpAsmInstructionStart + (36 * 128) @ Addr of primary handler.
8462 mov r0, rSELF
8463 add r1, rFP, #OFF_FP_SHADOWFRAME
8464 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8465
8466/* ------------------------------ */
8467 .balign 128
8468.L_ALT_op_filled_new_array_range: /* 0x25 */
8469/* File: arm/alt_stub.S */
8470/*
8471 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8472 * any interesting requests and then jump to the real instruction
8473 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8474 */
8475 .extern MterpCheckBefore
8476 EXPORT_PC
8477 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8478 adrl lr, artMterpAsmInstructionStart + (37 * 128) @ Addr of primary handler.
8479 mov r0, rSELF
8480 add r1, rFP, #OFF_FP_SHADOWFRAME
8481 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8482
8483/* ------------------------------ */
8484 .balign 128
8485.L_ALT_op_fill_array_data: /* 0x26 */
8486/* File: arm/alt_stub.S */
8487/*
8488 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8489 * any interesting requests and then jump to the real instruction
8490 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8491 */
8492 .extern MterpCheckBefore
8493 EXPORT_PC
8494 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8495 adrl lr, artMterpAsmInstructionStart + (38 * 128) @ Addr of primary handler.
8496 mov r0, rSELF
8497 add r1, rFP, #OFF_FP_SHADOWFRAME
8498 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8499
8500/* ------------------------------ */
8501 .balign 128
8502.L_ALT_op_throw: /* 0x27 */
8503/* File: arm/alt_stub.S */
8504/*
8505 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8506 * any interesting requests and then jump to the real instruction
8507 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8508 */
8509 .extern MterpCheckBefore
8510 EXPORT_PC
8511 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8512 adrl lr, artMterpAsmInstructionStart + (39 * 128) @ Addr of primary handler.
8513 mov r0, rSELF
8514 add r1, rFP, #OFF_FP_SHADOWFRAME
8515 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8516
8517/* ------------------------------ */
8518 .balign 128
8519.L_ALT_op_goto: /* 0x28 */
8520/* File: arm/alt_stub.S */
8521/*
8522 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8523 * any interesting requests and then jump to the real instruction
8524 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8525 */
8526 .extern MterpCheckBefore
8527 EXPORT_PC
8528 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8529 adrl lr, artMterpAsmInstructionStart + (40 * 128) @ Addr of primary handler.
8530 mov r0, rSELF
8531 add r1, rFP, #OFF_FP_SHADOWFRAME
8532 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8533
8534/* ------------------------------ */
8535 .balign 128
8536.L_ALT_op_goto_16: /* 0x29 */
8537/* File: arm/alt_stub.S */
8538/*
8539 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8540 * any interesting requests and then jump to the real instruction
8541 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8542 */
8543 .extern MterpCheckBefore
8544 EXPORT_PC
8545 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8546 adrl lr, artMterpAsmInstructionStart + (41 * 128) @ Addr of primary handler.
8547 mov r0, rSELF
8548 add r1, rFP, #OFF_FP_SHADOWFRAME
8549 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8550
8551/* ------------------------------ */
8552 .balign 128
8553.L_ALT_op_goto_32: /* 0x2a */
8554/* File: arm/alt_stub.S */
8555/*
8556 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8557 * any interesting requests and then jump to the real instruction
8558 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8559 */
8560 .extern MterpCheckBefore
8561 EXPORT_PC
8562 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8563 adrl lr, artMterpAsmInstructionStart + (42 * 128) @ Addr of primary handler.
8564 mov r0, rSELF
8565 add r1, rFP, #OFF_FP_SHADOWFRAME
8566 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8567
8568/* ------------------------------ */
8569 .balign 128
8570.L_ALT_op_packed_switch: /* 0x2b */
8571/* File: arm/alt_stub.S */
8572/*
8573 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8574 * any interesting requests and then jump to the real instruction
8575 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8576 */
8577 .extern MterpCheckBefore
8578 EXPORT_PC
8579 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8580 adrl lr, artMterpAsmInstructionStart + (43 * 128) @ Addr of primary handler.
8581 mov r0, rSELF
8582 add r1, rFP, #OFF_FP_SHADOWFRAME
8583 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8584
8585/* ------------------------------ */
8586 .balign 128
8587.L_ALT_op_sparse_switch: /* 0x2c */
8588/* File: arm/alt_stub.S */
8589/*
8590 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8591 * any interesting requests and then jump to the real instruction
8592 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8593 */
8594 .extern MterpCheckBefore
8595 EXPORT_PC
8596 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8597 adrl lr, artMterpAsmInstructionStart + (44 * 128) @ Addr of primary handler.
8598 mov r0, rSELF
8599 add r1, rFP, #OFF_FP_SHADOWFRAME
8600 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8601
8602/* ------------------------------ */
8603 .balign 128
8604.L_ALT_op_cmpl_float: /* 0x2d */
8605/* File: arm/alt_stub.S */
8606/*
8607 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8608 * any interesting requests and then jump to the real instruction
8609 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8610 */
8611 .extern MterpCheckBefore
8612 EXPORT_PC
8613 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8614 adrl lr, artMterpAsmInstructionStart + (45 * 128) @ Addr of primary handler.
8615 mov r0, rSELF
8616 add r1, rFP, #OFF_FP_SHADOWFRAME
8617 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8618
8619/* ------------------------------ */
8620 .balign 128
8621.L_ALT_op_cmpg_float: /* 0x2e */
8622/* File: arm/alt_stub.S */
8623/*
8624 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8625 * any interesting requests and then jump to the real instruction
8626 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8627 */
8628 .extern MterpCheckBefore
8629 EXPORT_PC
8630 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8631 adrl lr, artMterpAsmInstructionStart + (46 * 128) @ Addr of primary handler.
8632 mov r0, rSELF
8633 add r1, rFP, #OFF_FP_SHADOWFRAME
8634 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8635
8636/* ------------------------------ */
8637 .balign 128
8638.L_ALT_op_cmpl_double: /* 0x2f */
8639/* File: arm/alt_stub.S */
8640/*
8641 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8642 * any interesting requests and then jump to the real instruction
8643 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8644 */
8645 .extern MterpCheckBefore
8646 EXPORT_PC
8647 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8648 adrl lr, artMterpAsmInstructionStart + (47 * 128) @ Addr of primary handler.
8649 mov r0, rSELF
8650 add r1, rFP, #OFF_FP_SHADOWFRAME
8651 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8652
8653/* ------------------------------ */
8654 .balign 128
8655.L_ALT_op_cmpg_double: /* 0x30 */
8656/* File: arm/alt_stub.S */
8657/*
8658 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8659 * any interesting requests and then jump to the real instruction
8660 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8661 */
8662 .extern MterpCheckBefore
8663 EXPORT_PC
8664 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8665 adrl lr, artMterpAsmInstructionStart + (48 * 128) @ Addr of primary handler.
8666 mov r0, rSELF
8667 add r1, rFP, #OFF_FP_SHADOWFRAME
8668 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8669
8670/* ------------------------------ */
8671 .balign 128
8672.L_ALT_op_cmp_long: /* 0x31 */
8673/* File: arm/alt_stub.S */
8674/*
8675 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8676 * any interesting requests and then jump to the real instruction
8677 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8678 */
8679 .extern MterpCheckBefore
8680 EXPORT_PC
8681 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8682 adrl lr, artMterpAsmInstructionStart + (49 * 128) @ Addr of primary handler.
8683 mov r0, rSELF
8684 add r1, rFP, #OFF_FP_SHADOWFRAME
8685 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8686
8687/* ------------------------------ */
8688 .balign 128
8689.L_ALT_op_if_eq: /* 0x32 */
8690/* File: arm/alt_stub.S */
8691/*
8692 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8693 * any interesting requests and then jump to the real instruction
8694 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8695 */
8696 .extern MterpCheckBefore
8697 EXPORT_PC
8698 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8699 adrl lr, artMterpAsmInstructionStart + (50 * 128) @ Addr of primary handler.
8700 mov r0, rSELF
8701 add r1, rFP, #OFF_FP_SHADOWFRAME
8702 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8703
8704/* ------------------------------ */
8705 .balign 128
8706.L_ALT_op_if_ne: /* 0x33 */
8707/* File: arm/alt_stub.S */
8708/*
8709 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8710 * any interesting requests and then jump to the real instruction
8711 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8712 */
8713 .extern MterpCheckBefore
8714 EXPORT_PC
8715 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8716 adrl lr, artMterpAsmInstructionStart + (51 * 128) @ Addr of primary handler.
8717 mov r0, rSELF
8718 add r1, rFP, #OFF_FP_SHADOWFRAME
8719 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8720
8721/* ------------------------------ */
8722 .balign 128
8723.L_ALT_op_if_lt: /* 0x34 */
8724/* File: arm/alt_stub.S */
8725/*
8726 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8727 * any interesting requests and then jump to the real instruction
8728 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8729 */
8730 .extern MterpCheckBefore
8731 EXPORT_PC
8732 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8733 adrl lr, artMterpAsmInstructionStart + (52 * 128) @ Addr of primary handler.
8734 mov r0, rSELF
8735 add r1, rFP, #OFF_FP_SHADOWFRAME
8736 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8737
8738/* ------------------------------ */
8739 .balign 128
8740.L_ALT_op_if_ge: /* 0x35 */
8741/* File: arm/alt_stub.S */
8742/*
8743 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8744 * any interesting requests and then jump to the real instruction
8745 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8746 */
8747 .extern MterpCheckBefore
8748 EXPORT_PC
8749 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8750 adrl lr, artMterpAsmInstructionStart + (53 * 128) @ Addr of primary handler.
8751 mov r0, rSELF
8752 add r1, rFP, #OFF_FP_SHADOWFRAME
8753 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8754
8755/* ------------------------------ */
8756 .balign 128
8757.L_ALT_op_if_gt: /* 0x36 */
8758/* File: arm/alt_stub.S */
8759/*
8760 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8761 * any interesting requests and then jump to the real instruction
8762 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8763 */
8764 .extern MterpCheckBefore
8765 EXPORT_PC
8766 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8767 adrl lr, artMterpAsmInstructionStart + (54 * 128) @ Addr of primary handler.
8768 mov r0, rSELF
8769 add r1, rFP, #OFF_FP_SHADOWFRAME
8770 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8771
8772/* ------------------------------ */
8773 .balign 128
8774.L_ALT_op_if_le: /* 0x37 */
8775/* File: arm/alt_stub.S */
8776/*
8777 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8778 * any interesting requests and then jump to the real instruction
8779 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8780 */
8781 .extern MterpCheckBefore
8782 EXPORT_PC
8783 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8784 adrl lr, artMterpAsmInstructionStart + (55 * 128) @ Addr of primary handler.
8785 mov r0, rSELF
8786 add r1, rFP, #OFF_FP_SHADOWFRAME
8787 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8788
8789/* ------------------------------ */
8790 .balign 128
8791.L_ALT_op_if_eqz: /* 0x38 */
8792/* File: arm/alt_stub.S */
8793/*
8794 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8795 * any interesting requests and then jump to the real instruction
8796 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8797 */
8798 .extern MterpCheckBefore
8799 EXPORT_PC
8800 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8801 adrl lr, artMterpAsmInstructionStart + (56 * 128) @ Addr of primary handler.
8802 mov r0, rSELF
8803 add r1, rFP, #OFF_FP_SHADOWFRAME
8804 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8805
8806/* ------------------------------ */
8807 .balign 128
8808.L_ALT_op_if_nez: /* 0x39 */
8809/* File: arm/alt_stub.S */
8810/*
8811 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8812 * any interesting requests and then jump to the real instruction
8813 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8814 */
8815 .extern MterpCheckBefore
8816 EXPORT_PC
8817 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8818 adrl lr, artMterpAsmInstructionStart + (57 * 128) @ Addr of primary handler.
8819 mov r0, rSELF
8820 add r1, rFP, #OFF_FP_SHADOWFRAME
8821 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8822
8823/* ------------------------------ */
8824 .balign 128
8825.L_ALT_op_if_ltz: /* 0x3a */
8826/* File: arm/alt_stub.S */
8827/*
8828 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8829 * any interesting requests and then jump to the real instruction
8830 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8831 */
8832 .extern MterpCheckBefore
8833 EXPORT_PC
8834 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8835 adrl lr, artMterpAsmInstructionStart + (58 * 128) @ Addr of primary handler.
8836 mov r0, rSELF
8837 add r1, rFP, #OFF_FP_SHADOWFRAME
8838 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8839
8840/* ------------------------------ */
8841 .balign 128
8842.L_ALT_op_if_gez: /* 0x3b */
8843/* File: arm/alt_stub.S */
8844/*
8845 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8846 * any interesting requests and then jump to the real instruction
8847 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8848 */
8849 .extern MterpCheckBefore
8850 EXPORT_PC
8851 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8852 adrl lr, artMterpAsmInstructionStart + (59 * 128) @ Addr of primary handler.
8853 mov r0, rSELF
8854 add r1, rFP, #OFF_FP_SHADOWFRAME
8855 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8856
8857/* ------------------------------ */
8858 .balign 128
8859.L_ALT_op_if_gtz: /* 0x3c */
8860/* File: arm/alt_stub.S */
8861/*
8862 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8863 * any interesting requests and then jump to the real instruction
8864 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8865 */
8866 .extern MterpCheckBefore
8867 EXPORT_PC
8868 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8869 adrl lr, artMterpAsmInstructionStart + (60 * 128) @ Addr of primary handler.
8870 mov r0, rSELF
8871 add r1, rFP, #OFF_FP_SHADOWFRAME
8872 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8873
8874/* ------------------------------ */
8875 .balign 128
8876.L_ALT_op_if_lez: /* 0x3d */
8877/* File: arm/alt_stub.S */
8878/*
8879 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8880 * any interesting requests and then jump to the real instruction
8881 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8882 */
8883 .extern MterpCheckBefore
8884 EXPORT_PC
8885 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8886 adrl lr, artMterpAsmInstructionStart + (61 * 128) @ Addr of primary handler.
8887 mov r0, rSELF
8888 add r1, rFP, #OFF_FP_SHADOWFRAME
8889 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8890
8891/* ------------------------------ */
8892 .balign 128
8893.L_ALT_op_unused_3e: /* 0x3e */
8894/* File: arm/alt_stub.S */
8895/*
8896 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8897 * any interesting requests and then jump to the real instruction
8898 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8899 */
8900 .extern MterpCheckBefore
8901 EXPORT_PC
8902 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8903 adrl lr, artMterpAsmInstructionStart + (62 * 128) @ Addr of primary handler.
8904 mov r0, rSELF
8905 add r1, rFP, #OFF_FP_SHADOWFRAME
8906 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8907
8908/* ------------------------------ */
8909 .balign 128
8910.L_ALT_op_unused_3f: /* 0x3f */
8911/* File: arm/alt_stub.S */
8912/*
8913 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8914 * any interesting requests and then jump to the real instruction
8915 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8916 */
8917 .extern MterpCheckBefore
8918 EXPORT_PC
8919 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8920 adrl lr, artMterpAsmInstructionStart + (63 * 128) @ Addr of primary handler.
8921 mov r0, rSELF
8922 add r1, rFP, #OFF_FP_SHADOWFRAME
8923 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8924
8925/* ------------------------------ */
8926 .balign 128
8927.L_ALT_op_unused_40: /* 0x40 */
8928/* File: arm/alt_stub.S */
8929/*
8930 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8931 * any interesting requests and then jump to the real instruction
8932 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8933 */
8934 .extern MterpCheckBefore
8935 EXPORT_PC
8936 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8937 adrl lr, artMterpAsmInstructionStart + (64 * 128) @ Addr of primary handler.
8938 mov r0, rSELF
8939 add r1, rFP, #OFF_FP_SHADOWFRAME
8940 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8941
8942/* ------------------------------ */
8943 .balign 128
8944.L_ALT_op_unused_41: /* 0x41 */
8945/* File: arm/alt_stub.S */
8946/*
8947 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8948 * any interesting requests and then jump to the real instruction
8949 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8950 */
8951 .extern MterpCheckBefore
8952 EXPORT_PC
8953 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8954 adrl lr, artMterpAsmInstructionStart + (65 * 128) @ Addr of primary handler.
8955 mov r0, rSELF
8956 add r1, rFP, #OFF_FP_SHADOWFRAME
8957 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8958
8959/* ------------------------------ */
8960 .balign 128
8961.L_ALT_op_unused_42: /* 0x42 */
8962/* File: arm/alt_stub.S */
8963/*
8964 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8965 * any interesting requests and then jump to the real instruction
8966 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8967 */
8968 .extern MterpCheckBefore
8969 EXPORT_PC
8970 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8971 adrl lr, artMterpAsmInstructionStart + (66 * 128) @ Addr of primary handler.
8972 mov r0, rSELF
8973 add r1, rFP, #OFF_FP_SHADOWFRAME
8974 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8975
8976/* ------------------------------ */
8977 .balign 128
8978.L_ALT_op_unused_43: /* 0x43 */
8979/* File: arm/alt_stub.S */
8980/*
8981 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8982 * any interesting requests and then jump to the real instruction
8983 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8984 */
8985 .extern MterpCheckBefore
8986 EXPORT_PC
8987 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
8988 adrl lr, artMterpAsmInstructionStart + (67 * 128) @ Addr of primary handler.
8989 mov r0, rSELF
8990 add r1, rFP, #OFF_FP_SHADOWFRAME
8991 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
8992
8993/* ------------------------------ */
8994 .balign 128
8995.L_ALT_op_aget: /* 0x44 */
8996/* File: arm/alt_stub.S */
8997/*
8998 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8999 * any interesting requests and then jump to the real instruction
9000 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9001 */
9002 .extern MterpCheckBefore
9003 EXPORT_PC
9004 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9005 adrl lr, artMterpAsmInstructionStart + (68 * 128) @ Addr of primary handler.
9006 mov r0, rSELF
9007 add r1, rFP, #OFF_FP_SHADOWFRAME
9008 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9009
9010/* ------------------------------ */
9011 .balign 128
9012.L_ALT_op_aget_wide: /* 0x45 */
9013/* File: arm/alt_stub.S */
9014/*
9015 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9016 * any interesting requests and then jump to the real instruction
9017 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9018 */
9019 .extern MterpCheckBefore
9020 EXPORT_PC
9021 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9022 adrl lr, artMterpAsmInstructionStart + (69 * 128) @ Addr of primary handler.
9023 mov r0, rSELF
9024 add r1, rFP, #OFF_FP_SHADOWFRAME
9025 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9026
9027/* ------------------------------ */
9028 .balign 128
9029.L_ALT_op_aget_object: /* 0x46 */
9030/* File: arm/alt_stub.S */
9031/*
9032 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9033 * any interesting requests and then jump to the real instruction
9034 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9035 */
9036 .extern MterpCheckBefore
9037 EXPORT_PC
9038 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9039 adrl lr, artMterpAsmInstructionStart + (70 * 128) @ Addr of primary handler.
9040 mov r0, rSELF
9041 add r1, rFP, #OFF_FP_SHADOWFRAME
9042 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9043
9044/* ------------------------------ */
9045 .balign 128
9046.L_ALT_op_aget_boolean: /* 0x47 */
9047/* File: arm/alt_stub.S */
9048/*
9049 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9050 * any interesting requests and then jump to the real instruction
9051 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9052 */
9053 .extern MterpCheckBefore
9054 EXPORT_PC
9055 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9056 adrl lr, artMterpAsmInstructionStart + (71 * 128) @ Addr of primary handler.
9057 mov r0, rSELF
9058 add r1, rFP, #OFF_FP_SHADOWFRAME
9059 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9060
9061/* ------------------------------ */
9062 .balign 128
9063.L_ALT_op_aget_byte: /* 0x48 */
9064/* File: arm/alt_stub.S */
9065/*
9066 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9067 * any interesting requests and then jump to the real instruction
9068 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9069 */
9070 .extern MterpCheckBefore
9071 EXPORT_PC
9072 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9073 adrl lr, artMterpAsmInstructionStart + (72 * 128) @ Addr of primary handler.
9074 mov r0, rSELF
9075 add r1, rFP, #OFF_FP_SHADOWFRAME
9076 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9077
9078/* ------------------------------ */
9079 .balign 128
9080.L_ALT_op_aget_char: /* 0x49 */
9081/* File: arm/alt_stub.S */
9082/*
9083 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9084 * any interesting requests and then jump to the real instruction
9085 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9086 */
9087 .extern MterpCheckBefore
9088 EXPORT_PC
9089 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9090 adrl lr, artMterpAsmInstructionStart + (73 * 128) @ Addr of primary handler.
9091 mov r0, rSELF
9092 add r1, rFP, #OFF_FP_SHADOWFRAME
9093 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9094
9095/* ------------------------------ */
9096 .balign 128
9097.L_ALT_op_aget_short: /* 0x4a */
9098/* File: arm/alt_stub.S */
9099/*
9100 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9101 * any interesting requests and then jump to the real instruction
9102 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9103 */
9104 .extern MterpCheckBefore
9105 EXPORT_PC
9106 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9107 adrl lr, artMterpAsmInstructionStart + (74 * 128) @ Addr of primary handler.
9108 mov r0, rSELF
9109 add r1, rFP, #OFF_FP_SHADOWFRAME
9110 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9111
9112/* ------------------------------ */
9113 .balign 128
9114.L_ALT_op_aput: /* 0x4b */
9115/* File: arm/alt_stub.S */
9116/*
9117 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9118 * any interesting requests and then jump to the real instruction
9119 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9120 */
9121 .extern MterpCheckBefore
9122 EXPORT_PC
9123 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9124 adrl lr, artMterpAsmInstructionStart + (75 * 128) @ Addr of primary handler.
9125 mov r0, rSELF
9126 add r1, rFP, #OFF_FP_SHADOWFRAME
9127 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9128
9129/* ------------------------------ */
9130 .balign 128
9131.L_ALT_op_aput_wide: /* 0x4c */
9132/* File: arm/alt_stub.S */
9133/*
9134 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9135 * any interesting requests and then jump to the real instruction
9136 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9137 */
9138 .extern MterpCheckBefore
9139 EXPORT_PC
9140 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9141 adrl lr, artMterpAsmInstructionStart + (76 * 128) @ Addr of primary handler.
9142 mov r0, rSELF
9143 add r1, rFP, #OFF_FP_SHADOWFRAME
9144 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9145
9146/* ------------------------------ */
9147 .balign 128
9148.L_ALT_op_aput_object: /* 0x4d */
9149/* File: arm/alt_stub.S */
9150/*
9151 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9152 * any interesting requests and then jump to the real instruction
9153 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9154 */
9155 .extern MterpCheckBefore
9156 EXPORT_PC
9157 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9158 adrl lr, artMterpAsmInstructionStart + (77 * 128) @ Addr of primary handler.
9159 mov r0, rSELF
9160 add r1, rFP, #OFF_FP_SHADOWFRAME
9161 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9162
9163/* ------------------------------ */
9164 .balign 128
9165.L_ALT_op_aput_boolean: /* 0x4e */
9166/* File: arm/alt_stub.S */
9167/*
9168 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9169 * any interesting requests and then jump to the real instruction
9170 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9171 */
9172 .extern MterpCheckBefore
9173 EXPORT_PC
9174 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9175 adrl lr, artMterpAsmInstructionStart + (78 * 128) @ Addr of primary handler.
9176 mov r0, rSELF
9177 add r1, rFP, #OFF_FP_SHADOWFRAME
9178 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9179
9180/* ------------------------------ */
9181 .balign 128
9182.L_ALT_op_aput_byte: /* 0x4f */
9183/* File: arm/alt_stub.S */
9184/*
9185 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9186 * any interesting requests and then jump to the real instruction
9187 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9188 */
9189 .extern MterpCheckBefore
9190 EXPORT_PC
9191 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9192 adrl lr, artMterpAsmInstructionStart + (79 * 128) @ Addr of primary handler.
9193 mov r0, rSELF
9194 add r1, rFP, #OFF_FP_SHADOWFRAME
9195 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9196
9197/* ------------------------------ */
9198 .balign 128
9199.L_ALT_op_aput_char: /* 0x50 */
9200/* File: arm/alt_stub.S */
9201/*
9202 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9203 * any interesting requests and then jump to the real instruction
9204 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9205 */
9206 .extern MterpCheckBefore
9207 EXPORT_PC
9208 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9209 adrl lr, artMterpAsmInstructionStart + (80 * 128) @ Addr of primary handler.
9210 mov r0, rSELF
9211 add r1, rFP, #OFF_FP_SHADOWFRAME
9212 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9213
9214/* ------------------------------ */
9215 .balign 128
9216.L_ALT_op_aput_short: /* 0x51 */
9217/* File: arm/alt_stub.S */
9218/*
9219 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9220 * any interesting requests and then jump to the real instruction
9221 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9222 */
9223 .extern MterpCheckBefore
9224 EXPORT_PC
9225 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9226 adrl lr, artMterpAsmInstructionStart + (81 * 128) @ Addr of primary handler.
9227 mov r0, rSELF
9228 add r1, rFP, #OFF_FP_SHADOWFRAME
9229 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9230
9231/* ------------------------------ */
9232 .balign 128
9233.L_ALT_op_iget: /* 0x52 */
9234/* File: arm/alt_stub.S */
9235/*
9236 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9237 * any interesting requests and then jump to the real instruction
9238 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9239 */
9240 .extern MterpCheckBefore
9241 EXPORT_PC
9242 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9243 adrl lr, artMterpAsmInstructionStart + (82 * 128) @ Addr of primary handler.
9244 mov r0, rSELF
9245 add r1, rFP, #OFF_FP_SHADOWFRAME
9246 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9247
9248/* ------------------------------ */
9249 .balign 128
9250.L_ALT_op_iget_wide: /* 0x53 */
9251/* File: arm/alt_stub.S */
9252/*
9253 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9254 * any interesting requests and then jump to the real instruction
9255 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9256 */
9257 .extern MterpCheckBefore
9258 EXPORT_PC
9259 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9260 adrl lr, artMterpAsmInstructionStart + (83 * 128) @ Addr of primary handler.
9261 mov r0, rSELF
9262 add r1, rFP, #OFF_FP_SHADOWFRAME
9263 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9264
9265/* ------------------------------ */
9266 .balign 128
9267.L_ALT_op_iget_object: /* 0x54 */
9268/* File: arm/alt_stub.S */
9269/*
9270 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9271 * any interesting requests and then jump to the real instruction
9272 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9273 */
9274 .extern MterpCheckBefore
9275 EXPORT_PC
9276 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9277 adrl lr, artMterpAsmInstructionStart + (84 * 128) @ Addr of primary handler.
9278 mov r0, rSELF
9279 add r1, rFP, #OFF_FP_SHADOWFRAME
9280 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9281
9282/* ------------------------------ */
9283 .balign 128
9284.L_ALT_op_iget_boolean: /* 0x55 */
9285/* File: arm/alt_stub.S */
9286/*
9287 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9288 * any interesting requests and then jump to the real instruction
9289 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9290 */
9291 .extern MterpCheckBefore
9292 EXPORT_PC
9293 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9294 adrl lr, artMterpAsmInstructionStart + (85 * 128) @ Addr of primary handler.
9295 mov r0, rSELF
9296 add r1, rFP, #OFF_FP_SHADOWFRAME
9297 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9298
9299/* ------------------------------ */
9300 .balign 128
9301.L_ALT_op_iget_byte: /* 0x56 */
9302/* File: arm/alt_stub.S */
9303/*
9304 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9305 * any interesting requests and then jump to the real instruction
9306 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9307 */
9308 .extern MterpCheckBefore
9309 EXPORT_PC
9310 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9311 adrl lr, artMterpAsmInstructionStart + (86 * 128) @ Addr of primary handler.
9312 mov r0, rSELF
9313 add r1, rFP, #OFF_FP_SHADOWFRAME
9314 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9315
9316/* ------------------------------ */
9317 .balign 128
9318.L_ALT_op_iget_char: /* 0x57 */
9319/* File: arm/alt_stub.S */
9320/*
9321 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9322 * any interesting requests and then jump to the real instruction
9323 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9324 */
9325 .extern MterpCheckBefore
9326 EXPORT_PC
9327 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9328 adrl lr, artMterpAsmInstructionStart + (87 * 128) @ Addr of primary handler.
9329 mov r0, rSELF
9330 add r1, rFP, #OFF_FP_SHADOWFRAME
9331 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9332
9333/* ------------------------------ */
9334 .balign 128
9335.L_ALT_op_iget_short: /* 0x58 */
9336/* File: arm/alt_stub.S */
9337/*
9338 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9339 * any interesting requests and then jump to the real instruction
9340 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9341 */
9342 .extern MterpCheckBefore
9343 EXPORT_PC
9344 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9345 adrl lr, artMterpAsmInstructionStart + (88 * 128) @ Addr of primary handler.
9346 mov r0, rSELF
9347 add r1, rFP, #OFF_FP_SHADOWFRAME
9348 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9349
9350/* ------------------------------ */
9351 .balign 128
9352.L_ALT_op_iput: /* 0x59 */
9353/* File: arm/alt_stub.S */
9354/*
9355 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9356 * any interesting requests and then jump to the real instruction
9357 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9358 */
9359 .extern MterpCheckBefore
9360 EXPORT_PC
9361 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9362 adrl lr, artMterpAsmInstructionStart + (89 * 128) @ Addr of primary handler.
9363 mov r0, rSELF
9364 add r1, rFP, #OFF_FP_SHADOWFRAME
9365 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9366
9367/* ------------------------------ */
9368 .balign 128
9369.L_ALT_op_iput_wide: /* 0x5a */
9370/* File: arm/alt_stub.S */
9371/*
9372 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9373 * any interesting requests and then jump to the real instruction
9374 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9375 */
9376 .extern MterpCheckBefore
9377 EXPORT_PC
9378 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9379 adrl lr, artMterpAsmInstructionStart + (90 * 128) @ Addr of primary handler.
9380 mov r0, rSELF
9381 add r1, rFP, #OFF_FP_SHADOWFRAME
9382 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9383
9384/* ------------------------------ */
9385 .balign 128
9386.L_ALT_op_iput_object: /* 0x5b */
9387/* File: arm/alt_stub.S */
9388/*
9389 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9390 * any interesting requests and then jump to the real instruction
9391 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9392 */
9393 .extern MterpCheckBefore
9394 EXPORT_PC
9395 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9396 adrl lr, artMterpAsmInstructionStart + (91 * 128) @ Addr of primary handler.
9397 mov r0, rSELF
9398 add r1, rFP, #OFF_FP_SHADOWFRAME
9399 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9400
9401/* ------------------------------ */
9402 .balign 128
9403.L_ALT_op_iput_boolean: /* 0x5c */
9404/* File: arm/alt_stub.S */
9405/*
9406 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9407 * any interesting requests and then jump to the real instruction
9408 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9409 */
9410 .extern MterpCheckBefore
9411 EXPORT_PC
9412 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9413 adrl lr, artMterpAsmInstructionStart + (92 * 128) @ Addr of primary handler.
9414 mov r0, rSELF
9415 add r1, rFP, #OFF_FP_SHADOWFRAME
9416 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9417
9418/* ------------------------------ */
9419 .balign 128
9420.L_ALT_op_iput_byte: /* 0x5d */
9421/* File: arm/alt_stub.S */
9422/*
9423 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9424 * any interesting requests and then jump to the real instruction
9425 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9426 */
9427 .extern MterpCheckBefore
9428 EXPORT_PC
9429 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9430 adrl lr, artMterpAsmInstructionStart + (93 * 128) @ Addr of primary handler.
9431 mov r0, rSELF
9432 add r1, rFP, #OFF_FP_SHADOWFRAME
9433 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9434
9435/* ------------------------------ */
9436 .balign 128
9437.L_ALT_op_iput_char: /* 0x5e */
9438/* File: arm/alt_stub.S */
9439/*
9440 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9441 * any interesting requests and then jump to the real instruction
9442 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9443 */
9444 .extern MterpCheckBefore
9445 EXPORT_PC
9446 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9447 adrl lr, artMterpAsmInstructionStart + (94 * 128) @ Addr of primary handler.
9448 mov r0, rSELF
9449 add r1, rFP, #OFF_FP_SHADOWFRAME
9450 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9451
9452/* ------------------------------ */
9453 .balign 128
9454.L_ALT_op_iput_short: /* 0x5f */
9455/* File: arm/alt_stub.S */
9456/*
9457 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9458 * any interesting requests and then jump to the real instruction
9459 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9460 */
9461 .extern MterpCheckBefore
9462 EXPORT_PC
9463 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9464 adrl lr, artMterpAsmInstructionStart + (95 * 128) @ Addr of primary handler.
9465 mov r0, rSELF
9466 add r1, rFP, #OFF_FP_SHADOWFRAME
9467 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9468
9469/* ------------------------------ */
9470 .balign 128
9471.L_ALT_op_sget: /* 0x60 */
9472/* File: arm/alt_stub.S */
9473/*
9474 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9475 * any interesting requests and then jump to the real instruction
9476 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9477 */
9478 .extern MterpCheckBefore
9479 EXPORT_PC
9480 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9481 adrl lr, artMterpAsmInstructionStart + (96 * 128) @ Addr of primary handler.
9482 mov r0, rSELF
9483 add r1, rFP, #OFF_FP_SHADOWFRAME
9484 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9485
9486/* ------------------------------ */
9487 .balign 128
9488.L_ALT_op_sget_wide: /* 0x61 */
9489/* File: arm/alt_stub.S */
9490/*
9491 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9492 * any interesting requests and then jump to the real instruction
9493 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9494 */
9495 .extern MterpCheckBefore
9496 EXPORT_PC
9497 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9498 adrl lr, artMterpAsmInstructionStart + (97 * 128) @ Addr of primary handler.
9499 mov r0, rSELF
9500 add r1, rFP, #OFF_FP_SHADOWFRAME
9501 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9502
9503/* ------------------------------ */
9504 .balign 128
9505.L_ALT_op_sget_object: /* 0x62 */
9506/* File: arm/alt_stub.S */
9507/*
9508 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9509 * any interesting requests and then jump to the real instruction
9510 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9511 */
9512 .extern MterpCheckBefore
9513 EXPORT_PC
9514 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9515 adrl lr, artMterpAsmInstructionStart + (98 * 128) @ Addr of primary handler.
9516 mov r0, rSELF
9517 add r1, rFP, #OFF_FP_SHADOWFRAME
9518 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9519
9520/* ------------------------------ */
9521 .balign 128
9522.L_ALT_op_sget_boolean: /* 0x63 */
9523/* File: arm/alt_stub.S */
9524/*
9525 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9526 * any interesting requests and then jump to the real instruction
9527 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9528 */
9529 .extern MterpCheckBefore
9530 EXPORT_PC
9531 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9532 adrl lr, artMterpAsmInstructionStart + (99 * 128) @ Addr of primary handler.
9533 mov r0, rSELF
9534 add r1, rFP, #OFF_FP_SHADOWFRAME
9535 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9536
9537/* ------------------------------ */
9538 .balign 128
9539.L_ALT_op_sget_byte: /* 0x64 */
9540/* File: arm/alt_stub.S */
9541/*
9542 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9543 * any interesting requests and then jump to the real instruction
9544 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9545 */
9546 .extern MterpCheckBefore
9547 EXPORT_PC
9548 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9549 adrl lr, artMterpAsmInstructionStart + (100 * 128) @ Addr of primary handler.
9550 mov r0, rSELF
9551 add r1, rFP, #OFF_FP_SHADOWFRAME
9552 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9553
9554/* ------------------------------ */
9555 .balign 128
9556.L_ALT_op_sget_char: /* 0x65 */
9557/* File: arm/alt_stub.S */
9558/*
9559 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9560 * any interesting requests and then jump to the real instruction
9561 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9562 */
9563 .extern MterpCheckBefore
9564 EXPORT_PC
9565 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9566 adrl lr, artMterpAsmInstructionStart + (101 * 128) @ Addr of primary handler.
9567 mov r0, rSELF
9568 add r1, rFP, #OFF_FP_SHADOWFRAME
9569 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9570
9571/* ------------------------------ */
9572 .balign 128
9573.L_ALT_op_sget_short: /* 0x66 */
9574/* File: arm/alt_stub.S */
9575/*
9576 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9577 * any interesting requests and then jump to the real instruction
9578 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9579 */
9580 .extern MterpCheckBefore
9581 EXPORT_PC
9582 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9583 adrl lr, artMterpAsmInstructionStart + (102 * 128) @ Addr of primary handler.
9584 mov r0, rSELF
9585 add r1, rFP, #OFF_FP_SHADOWFRAME
9586 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9587
9588/* ------------------------------ */
9589 .balign 128
9590.L_ALT_op_sput: /* 0x67 */
9591/* File: arm/alt_stub.S */
9592/*
9593 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9594 * any interesting requests and then jump to the real instruction
9595 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9596 */
9597 .extern MterpCheckBefore
9598 EXPORT_PC
9599 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9600 adrl lr, artMterpAsmInstructionStart + (103 * 128) @ Addr of primary handler.
9601 mov r0, rSELF
9602 add r1, rFP, #OFF_FP_SHADOWFRAME
9603 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9604
9605/* ------------------------------ */
9606 .balign 128
9607.L_ALT_op_sput_wide: /* 0x68 */
9608/* File: arm/alt_stub.S */
9609/*
9610 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9611 * any interesting requests and then jump to the real instruction
9612 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9613 */
9614 .extern MterpCheckBefore
9615 EXPORT_PC
9616 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9617 adrl lr, artMterpAsmInstructionStart + (104 * 128) @ Addr of primary handler.
9618 mov r0, rSELF
9619 add r1, rFP, #OFF_FP_SHADOWFRAME
9620 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9621
9622/* ------------------------------ */
9623 .balign 128
9624.L_ALT_op_sput_object: /* 0x69 */
9625/* File: arm/alt_stub.S */
9626/*
9627 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9628 * any interesting requests and then jump to the real instruction
9629 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9630 */
9631 .extern MterpCheckBefore
9632 EXPORT_PC
9633 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9634 adrl lr, artMterpAsmInstructionStart + (105 * 128) @ Addr of primary handler.
9635 mov r0, rSELF
9636 add r1, rFP, #OFF_FP_SHADOWFRAME
9637 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9638
9639/* ------------------------------ */
9640 .balign 128
9641.L_ALT_op_sput_boolean: /* 0x6a */
9642/* File: arm/alt_stub.S */
9643/*
9644 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9645 * any interesting requests and then jump to the real instruction
9646 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9647 */
9648 .extern MterpCheckBefore
9649 EXPORT_PC
9650 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9651 adrl lr, artMterpAsmInstructionStart + (106 * 128) @ Addr of primary handler.
9652 mov r0, rSELF
9653 add r1, rFP, #OFF_FP_SHADOWFRAME
9654 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9655
9656/* ------------------------------ */
9657 .balign 128
9658.L_ALT_op_sput_byte: /* 0x6b */
9659/* File: arm/alt_stub.S */
9660/*
9661 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9662 * any interesting requests and then jump to the real instruction
9663 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9664 */
9665 .extern MterpCheckBefore
9666 EXPORT_PC
9667 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9668 adrl lr, artMterpAsmInstructionStart + (107 * 128) @ Addr of primary handler.
9669 mov r0, rSELF
9670 add r1, rFP, #OFF_FP_SHADOWFRAME
9671 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9672
9673/* ------------------------------ */
9674 .balign 128
9675.L_ALT_op_sput_char: /* 0x6c */
9676/* File: arm/alt_stub.S */
9677/*
9678 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9679 * any interesting requests and then jump to the real instruction
9680 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9681 */
9682 .extern MterpCheckBefore
9683 EXPORT_PC
9684 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9685 adrl lr, artMterpAsmInstructionStart + (108 * 128) @ Addr of primary handler.
9686 mov r0, rSELF
9687 add r1, rFP, #OFF_FP_SHADOWFRAME
9688 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9689
9690/* ------------------------------ */
9691 .balign 128
9692.L_ALT_op_sput_short: /* 0x6d */
9693/* File: arm/alt_stub.S */
9694/*
9695 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9696 * any interesting requests and then jump to the real instruction
9697 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9698 */
9699 .extern MterpCheckBefore
9700 EXPORT_PC
9701 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9702 adrl lr, artMterpAsmInstructionStart + (109 * 128) @ Addr of primary handler.
9703 mov r0, rSELF
9704 add r1, rFP, #OFF_FP_SHADOWFRAME
9705 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9706
9707/* ------------------------------ */
9708 .balign 128
9709.L_ALT_op_invoke_virtual: /* 0x6e */
9710/* File: arm/alt_stub.S */
9711/*
9712 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9713 * any interesting requests and then jump to the real instruction
9714 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9715 */
9716 .extern MterpCheckBefore
9717 EXPORT_PC
9718 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9719 adrl lr, artMterpAsmInstructionStart + (110 * 128) @ Addr of primary handler.
9720 mov r0, rSELF
9721 add r1, rFP, #OFF_FP_SHADOWFRAME
9722 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9723
9724/* ------------------------------ */
9725 .balign 128
9726.L_ALT_op_invoke_super: /* 0x6f */
9727/* File: arm/alt_stub.S */
9728/*
9729 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9730 * any interesting requests and then jump to the real instruction
9731 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9732 */
9733 .extern MterpCheckBefore
9734 EXPORT_PC
9735 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9736 adrl lr, artMterpAsmInstructionStart + (111 * 128) @ Addr of primary handler.
9737 mov r0, rSELF
9738 add r1, rFP, #OFF_FP_SHADOWFRAME
9739 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9740
9741/* ------------------------------ */
9742 .balign 128
9743.L_ALT_op_invoke_direct: /* 0x70 */
9744/* File: arm/alt_stub.S */
9745/*
9746 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9747 * any interesting requests and then jump to the real instruction
9748 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9749 */
9750 .extern MterpCheckBefore
9751 EXPORT_PC
9752 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9753 adrl lr, artMterpAsmInstructionStart + (112 * 128) @ Addr of primary handler.
9754 mov r0, rSELF
9755 add r1, rFP, #OFF_FP_SHADOWFRAME
9756 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9757
9758/* ------------------------------ */
9759 .balign 128
9760.L_ALT_op_invoke_static: /* 0x71 */
9761/* File: arm/alt_stub.S */
9762/*
9763 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9764 * any interesting requests and then jump to the real instruction
9765 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9766 */
9767 .extern MterpCheckBefore
9768 EXPORT_PC
9769 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9770 adrl lr, artMterpAsmInstructionStart + (113 * 128) @ Addr of primary handler.
9771 mov r0, rSELF
9772 add r1, rFP, #OFF_FP_SHADOWFRAME
9773 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9774
9775/* ------------------------------ */
9776 .balign 128
9777.L_ALT_op_invoke_interface: /* 0x72 */
9778/* File: arm/alt_stub.S */
9779/*
9780 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9781 * any interesting requests and then jump to the real instruction
9782 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9783 */
9784 .extern MterpCheckBefore
9785 EXPORT_PC
9786 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9787 adrl lr, artMterpAsmInstructionStart + (114 * 128) @ Addr of primary handler.
9788 mov r0, rSELF
9789 add r1, rFP, #OFF_FP_SHADOWFRAME
9790 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9791
9792/* ------------------------------ */
9793 .balign 128
9794.L_ALT_op_return_void_no_barrier: /* 0x73 */
9795/* File: arm/alt_stub.S */
9796/*
9797 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9798 * any interesting requests and then jump to the real instruction
9799 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9800 */
9801 .extern MterpCheckBefore
9802 EXPORT_PC
9803 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9804 adrl lr, artMterpAsmInstructionStart + (115 * 128) @ Addr of primary handler.
9805 mov r0, rSELF
9806 add r1, rFP, #OFF_FP_SHADOWFRAME
9807 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9808
9809/* ------------------------------ */
9810 .balign 128
9811.L_ALT_op_invoke_virtual_range: /* 0x74 */
9812/* File: arm/alt_stub.S */
9813/*
9814 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9815 * any interesting requests and then jump to the real instruction
9816 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9817 */
9818 .extern MterpCheckBefore
9819 EXPORT_PC
9820 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9821 adrl lr, artMterpAsmInstructionStart + (116 * 128) @ Addr of primary handler.
9822 mov r0, rSELF
9823 add r1, rFP, #OFF_FP_SHADOWFRAME
9824 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9825
9826/* ------------------------------ */
9827 .balign 128
9828.L_ALT_op_invoke_super_range: /* 0x75 */
9829/* File: arm/alt_stub.S */
9830/*
9831 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9832 * any interesting requests and then jump to the real instruction
9833 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9834 */
9835 .extern MterpCheckBefore
9836 EXPORT_PC
9837 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9838 adrl lr, artMterpAsmInstructionStart + (117 * 128) @ Addr of primary handler.
9839 mov r0, rSELF
9840 add r1, rFP, #OFF_FP_SHADOWFRAME
9841 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9842
9843/* ------------------------------ */
9844 .balign 128
9845.L_ALT_op_invoke_direct_range: /* 0x76 */
9846/* File: arm/alt_stub.S */
9847/*
9848 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9849 * any interesting requests and then jump to the real instruction
9850 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9851 */
9852 .extern MterpCheckBefore
9853 EXPORT_PC
9854 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9855 adrl lr, artMterpAsmInstructionStart + (118 * 128) @ Addr of primary handler.
9856 mov r0, rSELF
9857 add r1, rFP, #OFF_FP_SHADOWFRAME
9858 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9859
9860/* ------------------------------ */
9861 .balign 128
9862.L_ALT_op_invoke_static_range: /* 0x77 */
9863/* File: arm/alt_stub.S */
9864/*
9865 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9866 * any interesting requests and then jump to the real instruction
9867 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9868 */
9869 .extern MterpCheckBefore
9870 EXPORT_PC
9871 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9872 adrl lr, artMterpAsmInstructionStart + (119 * 128) @ Addr of primary handler.
9873 mov r0, rSELF
9874 add r1, rFP, #OFF_FP_SHADOWFRAME
9875 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9876
9877/* ------------------------------ */
9878 .balign 128
9879.L_ALT_op_invoke_interface_range: /* 0x78 */
9880/* File: arm/alt_stub.S */
9881/*
9882 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9883 * any interesting requests and then jump to the real instruction
9884 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9885 */
9886 .extern MterpCheckBefore
9887 EXPORT_PC
9888 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9889 adrl lr, artMterpAsmInstructionStart + (120 * 128) @ Addr of primary handler.
9890 mov r0, rSELF
9891 add r1, rFP, #OFF_FP_SHADOWFRAME
9892 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9893
9894/* ------------------------------ */
9895 .balign 128
9896.L_ALT_op_unused_79: /* 0x79 */
9897/* File: arm/alt_stub.S */
9898/*
9899 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9900 * any interesting requests and then jump to the real instruction
9901 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9902 */
9903 .extern MterpCheckBefore
9904 EXPORT_PC
9905 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9906 adrl lr, artMterpAsmInstructionStart + (121 * 128) @ Addr of primary handler.
9907 mov r0, rSELF
9908 add r1, rFP, #OFF_FP_SHADOWFRAME
9909 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9910
9911/* ------------------------------ */
9912 .balign 128
9913.L_ALT_op_unused_7a: /* 0x7a */
9914/* File: arm/alt_stub.S */
9915/*
9916 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9917 * any interesting requests and then jump to the real instruction
9918 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9919 */
9920 .extern MterpCheckBefore
9921 EXPORT_PC
9922 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9923 adrl lr, artMterpAsmInstructionStart + (122 * 128) @ Addr of primary handler.
9924 mov r0, rSELF
9925 add r1, rFP, #OFF_FP_SHADOWFRAME
9926 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9927
9928/* ------------------------------ */
9929 .balign 128
9930.L_ALT_op_neg_int: /* 0x7b */
9931/* File: arm/alt_stub.S */
9932/*
9933 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9934 * any interesting requests and then jump to the real instruction
9935 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9936 */
9937 .extern MterpCheckBefore
9938 EXPORT_PC
9939 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9940 adrl lr, artMterpAsmInstructionStart + (123 * 128) @ Addr of primary handler.
9941 mov r0, rSELF
9942 add r1, rFP, #OFF_FP_SHADOWFRAME
9943 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9944
9945/* ------------------------------ */
9946 .balign 128
9947.L_ALT_op_not_int: /* 0x7c */
9948/* File: arm/alt_stub.S */
9949/*
9950 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9951 * any interesting requests and then jump to the real instruction
9952 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9953 */
9954 .extern MterpCheckBefore
9955 EXPORT_PC
9956 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9957 adrl lr, artMterpAsmInstructionStart + (124 * 128) @ Addr of primary handler.
9958 mov r0, rSELF
9959 add r1, rFP, #OFF_FP_SHADOWFRAME
9960 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9961
9962/* ------------------------------ */
9963 .balign 128
9964.L_ALT_op_neg_long: /* 0x7d */
9965/* File: arm/alt_stub.S */
9966/*
9967 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9968 * any interesting requests and then jump to the real instruction
9969 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9970 */
9971 .extern MterpCheckBefore
9972 EXPORT_PC
9973 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9974 adrl lr, artMterpAsmInstructionStart + (125 * 128) @ Addr of primary handler.
9975 mov r0, rSELF
9976 add r1, rFP, #OFF_FP_SHADOWFRAME
9977 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9978
9979/* ------------------------------ */
9980 .balign 128
9981.L_ALT_op_not_long: /* 0x7e */
9982/* File: arm/alt_stub.S */
9983/*
9984 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9985 * any interesting requests and then jump to the real instruction
9986 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9987 */
9988 .extern MterpCheckBefore
9989 EXPORT_PC
9990 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
9991 adrl lr, artMterpAsmInstructionStart + (126 * 128) @ Addr of primary handler.
9992 mov r0, rSELF
9993 add r1, rFP, #OFF_FP_SHADOWFRAME
9994 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
9995
9996/* ------------------------------ */
9997 .balign 128
9998.L_ALT_op_neg_float: /* 0x7f */
9999/* File: arm/alt_stub.S */
10000/*
10001 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10002 * any interesting requests and then jump to the real instruction
10003 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10004 */
10005 .extern MterpCheckBefore
10006 EXPORT_PC
10007 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10008 adrl lr, artMterpAsmInstructionStart + (127 * 128) @ Addr of primary handler.
10009 mov r0, rSELF
10010 add r1, rFP, #OFF_FP_SHADOWFRAME
10011 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10012
10013/* ------------------------------ */
10014 .balign 128
10015.L_ALT_op_neg_double: /* 0x80 */
10016/* File: arm/alt_stub.S */
10017/*
10018 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10019 * any interesting requests and then jump to the real instruction
10020 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10021 */
10022 .extern MterpCheckBefore
10023 EXPORT_PC
10024 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10025 adrl lr, artMterpAsmInstructionStart + (128 * 128) @ Addr of primary handler.
10026 mov r0, rSELF
10027 add r1, rFP, #OFF_FP_SHADOWFRAME
10028 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10029
10030/* ------------------------------ */
10031 .balign 128
10032.L_ALT_op_int_to_long: /* 0x81 */
10033/* File: arm/alt_stub.S */
10034/*
10035 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10036 * any interesting requests and then jump to the real instruction
10037 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10038 */
10039 .extern MterpCheckBefore
10040 EXPORT_PC
10041 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10042 adrl lr, artMterpAsmInstructionStart + (129 * 128) @ Addr of primary handler.
10043 mov r0, rSELF
10044 add r1, rFP, #OFF_FP_SHADOWFRAME
10045 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10046
10047/* ------------------------------ */
10048 .balign 128
10049.L_ALT_op_int_to_float: /* 0x82 */
10050/* File: arm/alt_stub.S */
10051/*
10052 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10053 * any interesting requests and then jump to the real instruction
10054 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10055 */
10056 .extern MterpCheckBefore
10057 EXPORT_PC
10058 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10059 adrl lr, artMterpAsmInstructionStart + (130 * 128) @ Addr of primary handler.
10060 mov r0, rSELF
10061 add r1, rFP, #OFF_FP_SHADOWFRAME
10062 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10063
10064/* ------------------------------ */
10065 .balign 128
10066.L_ALT_op_int_to_double: /* 0x83 */
10067/* File: arm/alt_stub.S */
10068/*
10069 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10070 * any interesting requests and then jump to the real instruction
10071 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10072 */
10073 .extern MterpCheckBefore
10074 EXPORT_PC
10075 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10076 adrl lr, artMterpAsmInstructionStart + (131 * 128) @ Addr of primary handler.
10077 mov r0, rSELF
10078 add r1, rFP, #OFF_FP_SHADOWFRAME
10079 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10080
10081/* ------------------------------ */
10082 .balign 128
10083.L_ALT_op_long_to_int: /* 0x84 */
10084/* File: arm/alt_stub.S */
10085/*
10086 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10087 * any interesting requests and then jump to the real instruction
10088 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10089 */
10090 .extern MterpCheckBefore
10091 EXPORT_PC
10092 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10093 adrl lr, artMterpAsmInstructionStart + (132 * 128) @ Addr of primary handler.
10094 mov r0, rSELF
10095 add r1, rFP, #OFF_FP_SHADOWFRAME
10096 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10097
10098/* ------------------------------ */
10099 .balign 128
10100.L_ALT_op_long_to_float: /* 0x85 */
10101/* File: arm/alt_stub.S */
10102/*
10103 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10104 * any interesting requests and then jump to the real instruction
10105 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10106 */
10107 .extern MterpCheckBefore
10108 EXPORT_PC
10109 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10110 adrl lr, artMterpAsmInstructionStart + (133 * 128) @ Addr of primary handler.
10111 mov r0, rSELF
10112 add r1, rFP, #OFF_FP_SHADOWFRAME
10113 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10114
10115/* ------------------------------ */
10116 .balign 128
10117.L_ALT_op_long_to_double: /* 0x86 */
10118/* File: arm/alt_stub.S */
10119/*
10120 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10121 * any interesting requests and then jump to the real instruction
10122 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10123 */
10124 .extern MterpCheckBefore
10125 EXPORT_PC
10126 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10127 adrl lr, artMterpAsmInstructionStart + (134 * 128) @ Addr of primary handler.
10128 mov r0, rSELF
10129 add r1, rFP, #OFF_FP_SHADOWFRAME
10130 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10131
10132/* ------------------------------ */
10133 .balign 128
10134.L_ALT_op_float_to_int: /* 0x87 */
10135/* File: arm/alt_stub.S */
10136/*
10137 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10138 * any interesting requests and then jump to the real instruction
10139 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10140 */
10141 .extern MterpCheckBefore
10142 EXPORT_PC
10143 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10144 adrl lr, artMterpAsmInstructionStart + (135 * 128) @ Addr of primary handler.
10145 mov r0, rSELF
10146 add r1, rFP, #OFF_FP_SHADOWFRAME
10147 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10148
10149/* ------------------------------ */
10150 .balign 128
10151.L_ALT_op_float_to_long: /* 0x88 */
10152/* File: arm/alt_stub.S */
10153/*
10154 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10155 * any interesting requests and then jump to the real instruction
10156 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10157 */
10158 .extern MterpCheckBefore
10159 EXPORT_PC
10160 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10161 adrl lr, artMterpAsmInstructionStart + (136 * 128) @ Addr of primary handler.
10162 mov r0, rSELF
10163 add r1, rFP, #OFF_FP_SHADOWFRAME
10164 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10165
10166/* ------------------------------ */
10167 .balign 128
10168.L_ALT_op_float_to_double: /* 0x89 */
10169/* File: arm/alt_stub.S */
10170/*
10171 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10172 * any interesting requests and then jump to the real instruction
10173 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10174 */
10175 .extern MterpCheckBefore
10176 EXPORT_PC
10177 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10178 adrl lr, artMterpAsmInstructionStart + (137 * 128) @ Addr of primary handler.
10179 mov r0, rSELF
10180 add r1, rFP, #OFF_FP_SHADOWFRAME
10181 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10182
10183/* ------------------------------ */
10184 .balign 128
10185.L_ALT_op_double_to_int: /* 0x8a */
10186/* File: arm/alt_stub.S */
10187/*
10188 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10189 * any interesting requests and then jump to the real instruction
10190 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10191 */
10192 .extern MterpCheckBefore
10193 EXPORT_PC
10194 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10195 adrl lr, artMterpAsmInstructionStart + (138 * 128) @ Addr of primary handler.
10196 mov r0, rSELF
10197 add r1, rFP, #OFF_FP_SHADOWFRAME
10198 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10199
10200/* ------------------------------ */
10201 .balign 128
10202.L_ALT_op_double_to_long: /* 0x8b */
10203/* File: arm/alt_stub.S */
10204/*
10205 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10206 * any interesting requests and then jump to the real instruction
10207 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10208 */
10209 .extern MterpCheckBefore
10210 EXPORT_PC
10211 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10212 adrl lr, artMterpAsmInstructionStart + (139 * 128) @ Addr of primary handler.
10213 mov r0, rSELF
10214 add r1, rFP, #OFF_FP_SHADOWFRAME
10215 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10216
10217/* ------------------------------ */
10218 .balign 128
10219.L_ALT_op_double_to_float: /* 0x8c */
10220/* File: arm/alt_stub.S */
10221/*
10222 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10223 * any interesting requests and then jump to the real instruction
10224 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10225 */
10226 .extern MterpCheckBefore
10227 EXPORT_PC
10228 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10229 adrl lr, artMterpAsmInstructionStart + (140 * 128) @ Addr of primary handler.
10230 mov r0, rSELF
10231 add r1, rFP, #OFF_FP_SHADOWFRAME
10232 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10233
10234/* ------------------------------ */
10235 .balign 128
10236.L_ALT_op_int_to_byte: /* 0x8d */
10237/* File: arm/alt_stub.S */
10238/*
10239 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10240 * any interesting requests and then jump to the real instruction
10241 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10242 */
10243 .extern MterpCheckBefore
10244 EXPORT_PC
10245 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10246 adrl lr, artMterpAsmInstructionStart + (141 * 128) @ Addr of primary handler.
10247 mov r0, rSELF
10248 add r1, rFP, #OFF_FP_SHADOWFRAME
10249 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10250
10251/* ------------------------------ */
10252 .balign 128
10253.L_ALT_op_int_to_char: /* 0x8e */
10254/* File: arm/alt_stub.S */
10255/*
10256 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10257 * any interesting requests and then jump to the real instruction
10258 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10259 */
10260 .extern MterpCheckBefore
10261 EXPORT_PC
10262 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10263 adrl lr, artMterpAsmInstructionStart + (142 * 128) @ Addr of primary handler.
10264 mov r0, rSELF
10265 add r1, rFP, #OFF_FP_SHADOWFRAME
10266 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10267
10268/* ------------------------------ */
10269 .balign 128
10270.L_ALT_op_int_to_short: /* 0x8f */
10271/* File: arm/alt_stub.S */
10272/*
10273 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10274 * any interesting requests and then jump to the real instruction
10275 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10276 */
10277 .extern MterpCheckBefore
10278 EXPORT_PC
10279 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10280 adrl lr, artMterpAsmInstructionStart + (143 * 128) @ Addr of primary handler.
10281 mov r0, rSELF
10282 add r1, rFP, #OFF_FP_SHADOWFRAME
10283 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10284
10285/* ------------------------------ */
10286 .balign 128
10287.L_ALT_op_add_int: /* 0x90 */
10288/* File: arm/alt_stub.S */
10289/*
10290 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10291 * any interesting requests and then jump to the real instruction
10292 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10293 */
10294 .extern MterpCheckBefore
10295 EXPORT_PC
10296 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10297 adrl lr, artMterpAsmInstructionStart + (144 * 128) @ Addr of primary handler.
10298 mov r0, rSELF
10299 add r1, rFP, #OFF_FP_SHADOWFRAME
10300 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10301
10302/* ------------------------------ */
10303 .balign 128
10304.L_ALT_op_sub_int: /* 0x91 */
10305/* File: arm/alt_stub.S */
10306/*
10307 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10308 * any interesting requests and then jump to the real instruction
10309 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10310 */
10311 .extern MterpCheckBefore
10312 EXPORT_PC
10313 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10314 adrl lr, artMterpAsmInstructionStart + (145 * 128) @ Addr of primary handler.
10315 mov r0, rSELF
10316 add r1, rFP, #OFF_FP_SHADOWFRAME
10317 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10318
10319/* ------------------------------ */
10320 .balign 128
10321.L_ALT_op_mul_int: /* 0x92 */
10322/* File: arm/alt_stub.S */
10323/*
10324 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10325 * any interesting requests and then jump to the real instruction
10326 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10327 */
10328 .extern MterpCheckBefore
10329 EXPORT_PC
10330 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10331 adrl lr, artMterpAsmInstructionStart + (146 * 128) @ Addr of primary handler.
10332 mov r0, rSELF
10333 add r1, rFP, #OFF_FP_SHADOWFRAME
10334 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10335
10336/* ------------------------------ */
10337 .balign 128
10338.L_ALT_op_div_int: /* 0x93 */
10339/* File: arm/alt_stub.S */
10340/*
10341 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10342 * any interesting requests and then jump to the real instruction
10343 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10344 */
10345 .extern MterpCheckBefore
10346 EXPORT_PC
10347 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10348 adrl lr, artMterpAsmInstructionStart + (147 * 128) @ Addr of primary handler.
10349 mov r0, rSELF
10350 add r1, rFP, #OFF_FP_SHADOWFRAME
10351 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10352
10353/* ------------------------------ */
10354 .balign 128
10355.L_ALT_op_rem_int: /* 0x94 */
10356/* File: arm/alt_stub.S */
10357/*
10358 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10359 * any interesting requests and then jump to the real instruction
10360 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10361 */
10362 .extern MterpCheckBefore
10363 EXPORT_PC
10364 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10365 adrl lr, artMterpAsmInstructionStart + (148 * 128) @ Addr of primary handler.
10366 mov r0, rSELF
10367 add r1, rFP, #OFF_FP_SHADOWFRAME
10368 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10369
10370/* ------------------------------ */
10371 .balign 128
10372.L_ALT_op_and_int: /* 0x95 */
10373/* File: arm/alt_stub.S */
10374/*
10375 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10376 * any interesting requests and then jump to the real instruction
10377 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10378 */
10379 .extern MterpCheckBefore
10380 EXPORT_PC
10381 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10382 adrl lr, artMterpAsmInstructionStart + (149 * 128) @ Addr of primary handler.
10383 mov r0, rSELF
10384 add r1, rFP, #OFF_FP_SHADOWFRAME
10385 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10386
10387/* ------------------------------ */
10388 .balign 128
10389.L_ALT_op_or_int: /* 0x96 */
10390/* File: arm/alt_stub.S */
10391/*
10392 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10393 * any interesting requests and then jump to the real instruction
10394 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10395 */
10396 .extern MterpCheckBefore
10397 EXPORT_PC
10398 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10399 adrl lr, artMterpAsmInstructionStart + (150 * 128) @ Addr of primary handler.
10400 mov r0, rSELF
10401 add r1, rFP, #OFF_FP_SHADOWFRAME
10402 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10403
10404/* ------------------------------ */
10405 .balign 128
10406.L_ALT_op_xor_int: /* 0x97 */
10407/* File: arm/alt_stub.S */
10408/*
10409 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10410 * any interesting requests and then jump to the real instruction
10411 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10412 */
10413 .extern MterpCheckBefore
10414 EXPORT_PC
10415 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10416 adrl lr, artMterpAsmInstructionStart + (151 * 128) @ Addr of primary handler.
10417 mov r0, rSELF
10418 add r1, rFP, #OFF_FP_SHADOWFRAME
10419 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10420
10421/* ------------------------------ */
10422 .balign 128
10423.L_ALT_op_shl_int: /* 0x98 */
10424/* File: arm/alt_stub.S */
10425/*
10426 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10427 * any interesting requests and then jump to the real instruction
10428 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10429 */
10430 .extern MterpCheckBefore
10431 EXPORT_PC
10432 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10433 adrl lr, artMterpAsmInstructionStart + (152 * 128) @ Addr of primary handler.
10434 mov r0, rSELF
10435 add r1, rFP, #OFF_FP_SHADOWFRAME
10436 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10437
10438/* ------------------------------ */
10439 .balign 128
10440.L_ALT_op_shr_int: /* 0x99 */
10441/* File: arm/alt_stub.S */
10442/*
10443 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10444 * any interesting requests and then jump to the real instruction
10445 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10446 */
10447 .extern MterpCheckBefore
10448 EXPORT_PC
10449 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10450 adrl lr, artMterpAsmInstructionStart + (153 * 128) @ Addr of primary handler.
10451 mov r0, rSELF
10452 add r1, rFP, #OFF_FP_SHADOWFRAME
10453 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10454
10455/* ------------------------------ */
10456 .balign 128
10457.L_ALT_op_ushr_int: /* 0x9a */
10458/* File: arm/alt_stub.S */
10459/*
10460 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10461 * any interesting requests and then jump to the real instruction
10462 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10463 */
10464 .extern MterpCheckBefore
10465 EXPORT_PC
10466 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10467 adrl lr, artMterpAsmInstructionStart + (154 * 128) @ Addr of primary handler.
10468 mov r0, rSELF
10469 add r1, rFP, #OFF_FP_SHADOWFRAME
10470 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10471
10472/* ------------------------------ */
10473 .balign 128
10474.L_ALT_op_add_long: /* 0x9b */
10475/* File: arm/alt_stub.S */
10476/*
10477 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10478 * any interesting requests and then jump to the real instruction
10479 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10480 */
10481 .extern MterpCheckBefore
10482 EXPORT_PC
10483 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10484 adrl lr, artMterpAsmInstructionStart + (155 * 128) @ Addr of primary handler.
10485 mov r0, rSELF
10486 add r1, rFP, #OFF_FP_SHADOWFRAME
10487 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10488
10489/* ------------------------------ */
10490 .balign 128
10491.L_ALT_op_sub_long: /* 0x9c */
10492/* File: arm/alt_stub.S */
10493/*
10494 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10495 * any interesting requests and then jump to the real instruction
10496 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10497 */
10498 .extern MterpCheckBefore
10499 EXPORT_PC
10500 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10501 adrl lr, artMterpAsmInstructionStart + (156 * 128) @ Addr of primary handler.
10502 mov r0, rSELF
10503 add r1, rFP, #OFF_FP_SHADOWFRAME
10504 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10505
10506/* ------------------------------ */
10507 .balign 128
10508.L_ALT_op_mul_long: /* 0x9d */
10509/* File: arm/alt_stub.S */
10510/*
10511 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10512 * any interesting requests and then jump to the real instruction
10513 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10514 */
10515 .extern MterpCheckBefore
10516 EXPORT_PC
10517 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10518 adrl lr, artMterpAsmInstructionStart + (157 * 128) @ Addr of primary handler.
10519 mov r0, rSELF
10520 add r1, rFP, #OFF_FP_SHADOWFRAME
10521 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10522
10523/* ------------------------------ */
10524 .balign 128
10525.L_ALT_op_div_long: /* 0x9e */
10526/* File: arm/alt_stub.S */
10527/*
10528 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10529 * any interesting requests and then jump to the real instruction
10530 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10531 */
10532 .extern MterpCheckBefore
10533 EXPORT_PC
10534 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10535 adrl lr, artMterpAsmInstructionStart + (158 * 128) @ Addr of primary handler.
10536 mov r0, rSELF
10537 add r1, rFP, #OFF_FP_SHADOWFRAME
10538 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10539
10540/* ------------------------------ */
10541 .balign 128
10542.L_ALT_op_rem_long: /* 0x9f */
10543/* File: arm/alt_stub.S */
10544/*
10545 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10546 * any interesting requests and then jump to the real instruction
10547 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10548 */
10549 .extern MterpCheckBefore
10550 EXPORT_PC
10551 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10552 adrl lr, artMterpAsmInstructionStart + (159 * 128) @ Addr of primary handler.
10553 mov r0, rSELF
10554 add r1, rFP, #OFF_FP_SHADOWFRAME
10555 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10556
10557/* ------------------------------ */
10558 .balign 128
10559.L_ALT_op_and_long: /* 0xa0 */
10560/* File: arm/alt_stub.S */
10561/*
10562 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10563 * any interesting requests and then jump to the real instruction
10564 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10565 */
10566 .extern MterpCheckBefore
10567 EXPORT_PC
10568 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10569 adrl lr, artMterpAsmInstructionStart + (160 * 128) @ Addr of primary handler.
10570 mov r0, rSELF
10571 add r1, rFP, #OFF_FP_SHADOWFRAME
10572 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10573
10574/* ------------------------------ */
10575 .balign 128
10576.L_ALT_op_or_long: /* 0xa1 */
10577/* File: arm/alt_stub.S */
10578/*
10579 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10580 * any interesting requests and then jump to the real instruction
10581 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10582 */
10583 .extern MterpCheckBefore
10584 EXPORT_PC
10585 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10586 adrl lr, artMterpAsmInstructionStart + (161 * 128) @ Addr of primary handler.
10587 mov r0, rSELF
10588 add r1, rFP, #OFF_FP_SHADOWFRAME
10589 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10590
10591/* ------------------------------ */
10592 .balign 128
10593.L_ALT_op_xor_long: /* 0xa2 */
10594/* File: arm/alt_stub.S */
10595/*
10596 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10597 * any interesting requests and then jump to the real instruction
10598 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10599 */
10600 .extern MterpCheckBefore
10601 EXPORT_PC
10602 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10603 adrl lr, artMterpAsmInstructionStart + (162 * 128) @ Addr of primary handler.
10604 mov r0, rSELF
10605 add r1, rFP, #OFF_FP_SHADOWFRAME
10606 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10607
10608/* ------------------------------ */
10609 .balign 128
10610.L_ALT_op_shl_long: /* 0xa3 */
10611/* File: arm/alt_stub.S */
10612/*
10613 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10614 * any interesting requests and then jump to the real instruction
10615 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10616 */
10617 .extern MterpCheckBefore
10618 EXPORT_PC
10619 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10620 adrl lr, artMterpAsmInstructionStart + (163 * 128) @ Addr of primary handler.
10621 mov r0, rSELF
10622 add r1, rFP, #OFF_FP_SHADOWFRAME
10623 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10624
10625/* ------------------------------ */
10626 .balign 128
10627.L_ALT_op_shr_long: /* 0xa4 */
10628/* File: arm/alt_stub.S */
10629/*
10630 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10631 * any interesting requests and then jump to the real instruction
10632 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10633 */
10634 .extern MterpCheckBefore
10635 EXPORT_PC
10636 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10637 adrl lr, artMterpAsmInstructionStart + (164 * 128) @ Addr of primary handler.
10638 mov r0, rSELF
10639 add r1, rFP, #OFF_FP_SHADOWFRAME
10640 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10641
10642/* ------------------------------ */
10643 .balign 128
10644.L_ALT_op_ushr_long: /* 0xa5 */
10645/* File: arm/alt_stub.S */
10646/*
10647 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10648 * any interesting requests and then jump to the real instruction
10649 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10650 */
10651 .extern MterpCheckBefore
10652 EXPORT_PC
10653 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10654 adrl lr, artMterpAsmInstructionStart + (165 * 128) @ Addr of primary handler.
10655 mov r0, rSELF
10656 add r1, rFP, #OFF_FP_SHADOWFRAME
10657 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10658
10659/* ------------------------------ */
10660 .balign 128
10661.L_ALT_op_add_float: /* 0xa6 */
10662/* File: arm/alt_stub.S */
10663/*
10664 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10665 * any interesting requests and then jump to the real instruction
10666 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10667 */
10668 .extern MterpCheckBefore
10669 EXPORT_PC
10670 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10671 adrl lr, artMterpAsmInstructionStart + (166 * 128) @ Addr of primary handler.
10672 mov r0, rSELF
10673 add r1, rFP, #OFF_FP_SHADOWFRAME
10674 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10675
10676/* ------------------------------ */
10677 .balign 128
10678.L_ALT_op_sub_float: /* 0xa7 */
10679/* File: arm/alt_stub.S */
10680/*
10681 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10682 * any interesting requests and then jump to the real instruction
10683 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10684 */
10685 .extern MterpCheckBefore
10686 EXPORT_PC
10687 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10688 adrl lr, artMterpAsmInstructionStart + (167 * 128) @ Addr of primary handler.
10689 mov r0, rSELF
10690 add r1, rFP, #OFF_FP_SHADOWFRAME
10691 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10692
10693/* ------------------------------ */
10694 .balign 128
10695.L_ALT_op_mul_float: /* 0xa8 */
10696/* File: arm/alt_stub.S */
10697/*
10698 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10699 * any interesting requests and then jump to the real instruction
10700 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10701 */
10702 .extern MterpCheckBefore
10703 EXPORT_PC
10704 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10705 adrl lr, artMterpAsmInstructionStart + (168 * 128) @ Addr of primary handler.
10706 mov r0, rSELF
10707 add r1, rFP, #OFF_FP_SHADOWFRAME
10708 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10709
10710/* ------------------------------ */
10711 .balign 128
10712.L_ALT_op_div_float: /* 0xa9 */
10713/* File: arm/alt_stub.S */
10714/*
10715 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10716 * any interesting requests and then jump to the real instruction
10717 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10718 */
10719 .extern MterpCheckBefore
10720 EXPORT_PC
10721 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10722 adrl lr, artMterpAsmInstructionStart + (169 * 128) @ Addr of primary handler.
10723 mov r0, rSELF
10724 add r1, rFP, #OFF_FP_SHADOWFRAME
10725 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10726
10727/* ------------------------------ */
10728 .balign 128
10729.L_ALT_op_rem_float: /* 0xaa */
10730/* File: arm/alt_stub.S */
10731/*
10732 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10733 * any interesting requests and then jump to the real instruction
10734 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10735 */
10736 .extern MterpCheckBefore
10737 EXPORT_PC
10738 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10739 adrl lr, artMterpAsmInstructionStart + (170 * 128) @ Addr of primary handler.
10740 mov r0, rSELF
10741 add r1, rFP, #OFF_FP_SHADOWFRAME
10742 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10743
10744/* ------------------------------ */
10745 .balign 128
10746.L_ALT_op_add_double: /* 0xab */
10747/* File: arm/alt_stub.S */
10748/*
10749 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10750 * any interesting requests and then jump to the real instruction
10751 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10752 */
10753 .extern MterpCheckBefore
10754 EXPORT_PC
10755 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10756 adrl lr, artMterpAsmInstructionStart + (171 * 128) @ Addr of primary handler.
10757 mov r0, rSELF
10758 add r1, rFP, #OFF_FP_SHADOWFRAME
10759 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10760
10761/* ------------------------------ */
10762 .balign 128
10763.L_ALT_op_sub_double: /* 0xac */
10764/* File: arm/alt_stub.S */
10765/*
10766 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10767 * any interesting requests and then jump to the real instruction
10768 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10769 */
10770 .extern MterpCheckBefore
10771 EXPORT_PC
10772 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10773 adrl lr, artMterpAsmInstructionStart + (172 * 128) @ Addr of primary handler.
10774 mov r0, rSELF
10775 add r1, rFP, #OFF_FP_SHADOWFRAME
10776 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10777
10778/* ------------------------------ */
10779 .balign 128
10780.L_ALT_op_mul_double: /* 0xad */
10781/* File: arm/alt_stub.S */
10782/*
10783 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10784 * any interesting requests and then jump to the real instruction
10785 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10786 */
10787 .extern MterpCheckBefore
10788 EXPORT_PC
10789 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10790 adrl lr, artMterpAsmInstructionStart + (173 * 128) @ Addr of primary handler.
10791 mov r0, rSELF
10792 add r1, rFP, #OFF_FP_SHADOWFRAME
10793 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10794
10795/* ------------------------------ */
10796 .balign 128
10797.L_ALT_op_div_double: /* 0xae */
10798/* File: arm/alt_stub.S */
10799/*
10800 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10801 * any interesting requests and then jump to the real instruction
10802 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10803 */
10804 .extern MterpCheckBefore
10805 EXPORT_PC
10806 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10807 adrl lr, artMterpAsmInstructionStart + (174 * 128) @ Addr of primary handler.
10808 mov r0, rSELF
10809 add r1, rFP, #OFF_FP_SHADOWFRAME
10810 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10811
10812/* ------------------------------ */
10813 .balign 128
10814.L_ALT_op_rem_double: /* 0xaf */
10815/* File: arm/alt_stub.S */
10816/*
10817 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10818 * any interesting requests and then jump to the real instruction
10819 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10820 */
10821 .extern MterpCheckBefore
10822 EXPORT_PC
10823 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10824 adrl lr, artMterpAsmInstructionStart + (175 * 128) @ Addr of primary handler.
10825 mov r0, rSELF
10826 add r1, rFP, #OFF_FP_SHADOWFRAME
10827 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10828
10829/* ------------------------------ */
10830 .balign 128
10831.L_ALT_op_add_int_2addr: /* 0xb0 */
10832/* File: arm/alt_stub.S */
10833/*
10834 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10835 * any interesting requests and then jump to the real instruction
10836 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10837 */
10838 .extern MterpCheckBefore
10839 EXPORT_PC
10840 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10841 adrl lr, artMterpAsmInstructionStart + (176 * 128) @ Addr of primary handler.
10842 mov r0, rSELF
10843 add r1, rFP, #OFF_FP_SHADOWFRAME
10844 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10845
10846/* ------------------------------ */
10847 .balign 128
10848.L_ALT_op_sub_int_2addr: /* 0xb1 */
10849/* File: arm/alt_stub.S */
10850/*
10851 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10852 * any interesting requests and then jump to the real instruction
10853 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10854 */
10855 .extern MterpCheckBefore
10856 EXPORT_PC
10857 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10858 adrl lr, artMterpAsmInstructionStart + (177 * 128) @ Addr of primary handler.
10859 mov r0, rSELF
10860 add r1, rFP, #OFF_FP_SHADOWFRAME
10861 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10862
10863/* ------------------------------ */
10864 .balign 128
10865.L_ALT_op_mul_int_2addr: /* 0xb2 */
10866/* File: arm/alt_stub.S */
10867/*
10868 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10869 * any interesting requests and then jump to the real instruction
10870 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10871 */
10872 .extern MterpCheckBefore
10873 EXPORT_PC
10874 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10875 adrl lr, artMterpAsmInstructionStart + (178 * 128) @ Addr of primary handler.
10876 mov r0, rSELF
10877 add r1, rFP, #OFF_FP_SHADOWFRAME
10878 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10879
10880/* ------------------------------ */
10881 .balign 128
10882.L_ALT_op_div_int_2addr: /* 0xb3 */
10883/* File: arm/alt_stub.S */
10884/*
10885 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10886 * any interesting requests and then jump to the real instruction
10887 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10888 */
10889 .extern MterpCheckBefore
10890 EXPORT_PC
10891 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10892 adrl lr, artMterpAsmInstructionStart + (179 * 128) @ Addr of primary handler.
10893 mov r0, rSELF
10894 add r1, rFP, #OFF_FP_SHADOWFRAME
10895 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10896
10897/* ------------------------------ */
10898 .balign 128
10899.L_ALT_op_rem_int_2addr: /* 0xb4 */
10900/* File: arm/alt_stub.S */
10901/*
10902 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10903 * any interesting requests and then jump to the real instruction
10904 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10905 */
10906 .extern MterpCheckBefore
10907 EXPORT_PC
10908 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10909 adrl lr, artMterpAsmInstructionStart + (180 * 128) @ Addr of primary handler.
10910 mov r0, rSELF
10911 add r1, rFP, #OFF_FP_SHADOWFRAME
10912 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10913
10914/* ------------------------------ */
10915 .balign 128
10916.L_ALT_op_and_int_2addr: /* 0xb5 */
10917/* File: arm/alt_stub.S */
10918/*
10919 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10920 * any interesting requests and then jump to the real instruction
10921 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10922 */
10923 .extern MterpCheckBefore
10924 EXPORT_PC
10925 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10926 adrl lr, artMterpAsmInstructionStart + (181 * 128) @ Addr of primary handler.
10927 mov r0, rSELF
10928 add r1, rFP, #OFF_FP_SHADOWFRAME
10929 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10930
10931/* ------------------------------ */
10932 .balign 128
10933.L_ALT_op_or_int_2addr: /* 0xb6 */
10934/* File: arm/alt_stub.S */
10935/*
10936 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10937 * any interesting requests and then jump to the real instruction
10938 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10939 */
10940 .extern MterpCheckBefore
10941 EXPORT_PC
10942 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10943 adrl lr, artMterpAsmInstructionStart + (182 * 128) @ Addr of primary handler.
10944 mov r0, rSELF
10945 add r1, rFP, #OFF_FP_SHADOWFRAME
10946 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10947
10948/* ------------------------------ */
10949 .balign 128
10950.L_ALT_op_xor_int_2addr: /* 0xb7 */
10951/* File: arm/alt_stub.S */
10952/*
10953 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10954 * any interesting requests and then jump to the real instruction
10955 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10956 */
10957 .extern MterpCheckBefore
10958 EXPORT_PC
10959 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10960 adrl lr, artMterpAsmInstructionStart + (183 * 128) @ Addr of primary handler.
10961 mov r0, rSELF
10962 add r1, rFP, #OFF_FP_SHADOWFRAME
10963 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10964
10965/* ------------------------------ */
10966 .balign 128
10967.L_ALT_op_shl_int_2addr: /* 0xb8 */
10968/* File: arm/alt_stub.S */
10969/*
10970 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10971 * any interesting requests and then jump to the real instruction
10972 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10973 */
10974 .extern MterpCheckBefore
10975 EXPORT_PC
10976 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10977 adrl lr, artMterpAsmInstructionStart + (184 * 128) @ Addr of primary handler.
10978 mov r0, rSELF
10979 add r1, rFP, #OFF_FP_SHADOWFRAME
10980 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10981
10982/* ------------------------------ */
10983 .balign 128
10984.L_ALT_op_shr_int_2addr: /* 0xb9 */
10985/* File: arm/alt_stub.S */
10986/*
10987 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10988 * any interesting requests and then jump to the real instruction
10989 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10990 */
10991 .extern MterpCheckBefore
10992 EXPORT_PC
10993 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
10994 adrl lr, artMterpAsmInstructionStart + (185 * 128) @ Addr of primary handler.
10995 mov r0, rSELF
10996 add r1, rFP, #OFF_FP_SHADOWFRAME
10997 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
10998
10999/* ------------------------------ */
11000 .balign 128
11001.L_ALT_op_ushr_int_2addr: /* 0xba */
11002/* File: arm/alt_stub.S */
11003/*
11004 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11005 * any interesting requests and then jump to the real instruction
11006 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11007 */
11008 .extern MterpCheckBefore
11009 EXPORT_PC
11010 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11011 adrl lr, artMterpAsmInstructionStart + (186 * 128) @ Addr of primary handler.
11012 mov r0, rSELF
11013 add r1, rFP, #OFF_FP_SHADOWFRAME
11014 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11015
11016/* ------------------------------ */
11017 .balign 128
11018.L_ALT_op_add_long_2addr: /* 0xbb */
11019/* File: arm/alt_stub.S */
11020/*
11021 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11022 * any interesting requests and then jump to the real instruction
11023 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11024 */
11025 .extern MterpCheckBefore
11026 EXPORT_PC
11027 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11028 adrl lr, artMterpAsmInstructionStart + (187 * 128) @ Addr of primary handler.
11029 mov r0, rSELF
11030 add r1, rFP, #OFF_FP_SHADOWFRAME
11031 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11032
11033/* ------------------------------ */
11034 .balign 128
11035.L_ALT_op_sub_long_2addr: /* 0xbc */
11036/* File: arm/alt_stub.S */
11037/*
11038 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11039 * any interesting requests and then jump to the real instruction
11040 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11041 */
11042 .extern MterpCheckBefore
11043 EXPORT_PC
11044 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11045 adrl lr, artMterpAsmInstructionStart + (188 * 128) @ Addr of primary handler.
11046 mov r0, rSELF
11047 add r1, rFP, #OFF_FP_SHADOWFRAME
11048 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11049
11050/* ------------------------------ */
11051 .balign 128
11052.L_ALT_op_mul_long_2addr: /* 0xbd */
11053/* File: arm/alt_stub.S */
11054/*
11055 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11056 * any interesting requests and then jump to the real instruction
11057 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11058 */
11059 .extern MterpCheckBefore
11060 EXPORT_PC
11061 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11062 adrl lr, artMterpAsmInstructionStart + (189 * 128) @ Addr of primary handler.
11063 mov r0, rSELF
11064 add r1, rFP, #OFF_FP_SHADOWFRAME
11065 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11066
11067/* ------------------------------ */
11068 .balign 128
11069.L_ALT_op_div_long_2addr: /* 0xbe */
11070/* File: arm/alt_stub.S */
11071/*
11072 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11073 * any interesting requests and then jump to the real instruction
11074 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11075 */
11076 .extern MterpCheckBefore
11077 EXPORT_PC
11078 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11079 adrl lr, artMterpAsmInstructionStart + (190 * 128) @ Addr of primary handler.
11080 mov r0, rSELF
11081 add r1, rFP, #OFF_FP_SHADOWFRAME
11082 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11083
11084/* ------------------------------ */
11085 .balign 128
11086.L_ALT_op_rem_long_2addr: /* 0xbf */
11087/* File: arm/alt_stub.S */
11088/*
11089 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11090 * any interesting requests and then jump to the real instruction
11091 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11092 */
11093 .extern MterpCheckBefore
11094 EXPORT_PC
11095 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11096 adrl lr, artMterpAsmInstructionStart + (191 * 128) @ Addr of primary handler.
11097 mov r0, rSELF
11098 add r1, rFP, #OFF_FP_SHADOWFRAME
11099 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11100
11101/* ------------------------------ */
11102 .balign 128
11103.L_ALT_op_and_long_2addr: /* 0xc0 */
11104/* File: arm/alt_stub.S */
11105/*
11106 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11107 * any interesting requests and then jump to the real instruction
11108 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11109 */
11110 .extern MterpCheckBefore
11111 EXPORT_PC
11112 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11113 adrl lr, artMterpAsmInstructionStart + (192 * 128) @ Addr of primary handler.
11114 mov r0, rSELF
11115 add r1, rFP, #OFF_FP_SHADOWFRAME
11116 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11117
11118/* ------------------------------ */
11119 .balign 128
11120.L_ALT_op_or_long_2addr: /* 0xc1 */
11121/* File: arm/alt_stub.S */
11122/*
11123 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11124 * any interesting requests and then jump to the real instruction
11125 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11126 */
11127 .extern MterpCheckBefore
11128 EXPORT_PC
11129 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11130 adrl lr, artMterpAsmInstructionStart + (193 * 128) @ Addr of primary handler.
11131 mov r0, rSELF
11132 add r1, rFP, #OFF_FP_SHADOWFRAME
11133 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11134
11135/* ------------------------------ */
11136 .balign 128
11137.L_ALT_op_xor_long_2addr: /* 0xc2 */
11138/* File: arm/alt_stub.S */
11139/*
11140 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11141 * any interesting requests and then jump to the real instruction
11142 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11143 */
11144 .extern MterpCheckBefore
11145 EXPORT_PC
11146 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11147 adrl lr, artMterpAsmInstructionStart + (194 * 128) @ Addr of primary handler.
11148 mov r0, rSELF
11149 add r1, rFP, #OFF_FP_SHADOWFRAME
11150 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11151
11152/* ------------------------------ */
11153 .balign 128
11154.L_ALT_op_shl_long_2addr: /* 0xc3 */
11155/* File: arm/alt_stub.S */
11156/*
11157 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11158 * any interesting requests and then jump to the real instruction
11159 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11160 */
11161 .extern MterpCheckBefore
11162 EXPORT_PC
11163 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11164 adrl lr, artMterpAsmInstructionStart + (195 * 128) @ Addr of primary handler.
11165 mov r0, rSELF
11166 add r1, rFP, #OFF_FP_SHADOWFRAME
11167 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11168
11169/* ------------------------------ */
11170 .balign 128
11171.L_ALT_op_shr_long_2addr: /* 0xc4 */
11172/* File: arm/alt_stub.S */
11173/*
11174 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11175 * any interesting requests and then jump to the real instruction
11176 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11177 */
11178 .extern MterpCheckBefore
11179 EXPORT_PC
11180 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11181 adrl lr, artMterpAsmInstructionStart + (196 * 128) @ Addr of primary handler.
11182 mov r0, rSELF
11183 add r1, rFP, #OFF_FP_SHADOWFRAME
11184 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11185
11186/* ------------------------------ */
11187 .balign 128
11188.L_ALT_op_ushr_long_2addr: /* 0xc5 */
11189/* File: arm/alt_stub.S */
11190/*
11191 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11192 * any interesting requests and then jump to the real instruction
11193 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11194 */
11195 .extern MterpCheckBefore
11196 EXPORT_PC
11197 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11198 adrl lr, artMterpAsmInstructionStart + (197 * 128) @ Addr of primary handler.
11199 mov r0, rSELF
11200 add r1, rFP, #OFF_FP_SHADOWFRAME
11201 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11202
11203/* ------------------------------ */
11204 .balign 128
11205.L_ALT_op_add_float_2addr: /* 0xc6 */
11206/* File: arm/alt_stub.S */
11207/*
11208 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11209 * any interesting requests and then jump to the real instruction
11210 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11211 */
11212 .extern MterpCheckBefore
11213 EXPORT_PC
11214 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11215 adrl lr, artMterpAsmInstructionStart + (198 * 128) @ Addr of primary handler.
11216 mov r0, rSELF
11217 add r1, rFP, #OFF_FP_SHADOWFRAME
11218 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11219
11220/* ------------------------------ */
11221 .balign 128
11222.L_ALT_op_sub_float_2addr: /* 0xc7 */
11223/* File: arm/alt_stub.S */
11224/*
11225 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11226 * any interesting requests and then jump to the real instruction
11227 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11228 */
11229 .extern MterpCheckBefore
11230 EXPORT_PC
11231 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11232 adrl lr, artMterpAsmInstructionStart + (199 * 128) @ Addr of primary handler.
11233 mov r0, rSELF
11234 add r1, rFP, #OFF_FP_SHADOWFRAME
11235 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11236
11237/* ------------------------------ */
11238 .balign 128
11239.L_ALT_op_mul_float_2addr: /* 0xc8 */
11240/* File: arm/alt_stub.S */
11241/*
11242 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11243 * any interesting requests and then jump to the real instruction
11244 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11245 */
11246 .extern MterpCheckBefore
11247 EXPORT_PC
11248 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11249 adrl lr, artMterpAsmInstructionStart + (200 * 128) @ Addr of primary handler.
11250 mov r0, rSELF
11251 add r1, rFP, #OFF_FP_SHADOWFRAME
11252 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11253
11254/* ------------------------------ */
11255 .balign 128
11256.L_ALT_op_div_float_2addr: /* 0xc9 */
11257/* File: arm/alt_stub.S */
11258/*
11259 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11260 * any interesting requests and then jump to the real instruction
11261 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11262 */
11263 .extern MterpCheckBefore
11264 EXPORT_PC
11265 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11266 adrl lr, artMterpAsmInstructionStart + (201 * 128) @ Addr of primary handler.
11267 mov r0, rSELF
11268 add r1, rFP, #OFF_FP_SHADOWFRAME
11269 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11270
11271/* ------------------------------ */
11272 .balign 128
11273.L_ALT_op_rem_float_2addr: /* 0xca */
11274/* File: arm/alt_stub.S */
11275/*
11276 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11277 * any interesting requests and then jump to the real instruction
11278 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11279 */
11280 .extern MterpCheckBefore
11281 EXPORT_PC
11282 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11283 adrl lr, artMterpAsmInstructionStart + (202 * 128) @ Addr of primary handler.
11284 mov r0, rSELF
11285 add r1, rFP, #OFF_FP_SHADOWFRAME
11286 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11287
11288/* ------------------------------ */
11289 .balign 128
11290.L_ALT_op_add_double_2addr: /* 0xcb */
11291/* File: arm/alt_stub.S */
11292/*
11293 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11294 * any interesting requests and then jump to the real instruction
11295 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11296 */
11297 .extern MterpCheckBefore
11298 EXPORT_PC
11299 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11300 adrl lr, artMterpAsmInstructionStart + (203 * 128) @ Addr of primary handler.
11301 mov r0, rSELF
11302 add r1, rFP, #OFF_FP_SHADOWFRAME
11303 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11304
11305/* ------------------------------ */
11306 .balign 128
11307.L_ALT_op_sub_double_2addr: /* 0xcc */
11308/* File: arm/alt_stub.S */
11309/*
11310 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11311 * any interesting requests and then jump to the real instruction
11312 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11313 */
11314 .extern MterpCheckBefore
11315 EXPORT_PC
11316 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11317 adrl lr, artMterpAsmInstructionStart + (204 * 128) @ Addr of primary handler.
11318 mov r0, rSELF
11319 add r1, rFP, #OFF_FP_SHADOWFRAME
11320 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11321
11322/* ------------------------------ */
11323 .balign 128
11324.L_ALT_op_mul_double_2addr: /* 0xcd */
11325/* File: arm/alt_stub.S */
11326/*
11327 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11328 * any interesting requests and then jump to the real instruction
11329 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11330 */
11331 .extern MterpCheckBefore
11332 EXPORT_PC
11333 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11334 adrl lr, artMterpAsmInstructionStart + (205 * 128) @ Addr of primary handler.
11335 mov r0, rSELF
11336 add r1, rFP, #OFF_FP_SHADOWFRAME
11337 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11338
11339/* ------------------------------ */
11340 .balign 128
11341.L_ALT_op_div_double_2addr: /* 0xce */
11342/* File: arm/alt_stub.S */
11343/*
11344 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11345 * any interesting requests and then jump to the real instruction
11346 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11347 */
11348 .extern MterpCheckBefore
11349 EXPORT_PC
11350 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11351 adrl lr, artMterpAsmInstructionStart + (206 * 128) @ Addr of primary handler.
11352 mov r0, rSELF
11353 add r1, rFP, #OFF_FP_SHADOWFRAME
11354 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11355
11356/* ------------------------------ */
11357 .balign 128
11358.L_ALT_op_rem_double_2addr: /* 0xcf */
11359/* File: arm/alt_stub.S */
11360/*
11361 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11362 * any interesting requests and then jump to the real instruction
11363 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11364 */
11365 .extern MterpCheckBefore
11366 EXPORT_PC
11367 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11368 adrl lr, artMterpAsmInstructionStart + (207 * 128) @ Addr of primary handler.
11369 mov r0, rSELF
11370 add r1, rFP, #OFF_FP_SHADOWFRAME
11371 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11372
11373/* ------------------------------ */
11374 .balign 128
11375.L_ALT_op_add_int_lit16: /* 0xd0 */
11376/* File: arm/alt_stub.S */
11377/*
11378 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11379 * any interesting requests and then jump to the real instruction
11380 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11381 */
11382 .extern MterpCheckBefore
11383 EXPORT_PC
11384 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11385 adrl lr, artMterpAsmInstructionStart + (208 * 128) @ Addr of primary handler.
11386 mov r0, rSELF
11387 add r1, rFP, #OFF_FP_SHADOWFRAME
11388 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11389
11390/* ------------------------------ */
11391 .balign 128
11392.L_ALT_op_rsub_int: /* 0xd1 */
11393/* File: arm/alt_stub.S */
11394/*
11395 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11396 * any interesting requests and then jump to the real instruction
11397 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11398 */
11399 .extern MterpCheckBefore
11400 EXPORT_PC
11401 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11402 adrl lr, artMterpAsmInstructionStart + (209 * 128) @ Addr of primary handler.
11403 mov r0, rSELF
11404 add r1, rFP, #OFF_FP_SHADOWFRAME
11405 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11406
11407/* ------------------------------ */
11408 .balign 128
11409.L_ALT_op_mul_int_lit16: /* 0xd2 */
11410/* File: arm/alt_stub.S */
11411/*
11412 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11413 * any interesting requests and then jump to the real instruction
11414 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11415 */
11416 .extern MterpCheckBefore
11417 EXPORT_PC
11418 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11419 adrl lr, artMterpAsmInstructionStart + (210 * 128) @ Addr of primary handler.
11420 mov r0, rSELF
11421 add r1, rFP, #OFF_FP_SHADOWFRAME
11422 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11423
11424/* ------------------------------ */
11425 .balign 128
11426.L_ALT_op_div_int_lit16: /* 0xd3 */
11427/* File: arm/alt_stub.S */
11428/*
11429 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11430 * any interesting requests and then jump to the real instruction
11431 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11432 */
11433 .extern MterpCheckBefore
11434 EXPORT_PC
11435 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11436 adrl lr, artMterpAsmInstructionStart + (211 * 128) @ Addr of primary handler.
11437 mov r0, rSELF
11438 add r1, rFP, #OFF_FP_SHADOWFRAME
11439 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11440
11441/* ------------------------------ */
11442 .balign 128
11443.L_ALT_op_rem_int_lit16: /* 0xd4 */
11444/* File: arm/alt_stub.S */
11445/*
11446 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11447 * any interesting requests and then jump to the real instruction
11448 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11449 */
11450 .extern MterpCheckBefore
11451 EXPORT_PC
11452 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11453 adrl lr, artMterpAsmInstructionStart + (212 * 128) @ Addr of primary handler.
11454 mov r0, rSELF
11455 add r1, rFP, #OFF_FP_SHADOWFRAME
11456 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11457
11458/* ------------------------------ */
11459 .balign 128
11460.L_ALT_op_and_int_lit16: /* 0xd5 */
11461/* File: arm/alt_stub.S */
11462/*
11463 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11464 * any interesting requests and then jump to the real instruction
11465 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11466 */
11467 .extern MterpCheckBefore
11468 EXPORT_PC
11469 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11470 adrl lr, artMterpAsmInstructionStart + (213 * 128) @ Addr of primary handler.
11471 mov r0, rSELF
11472 add r1, rFP, #OFF_FP_SHADOWFRAME
11473 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11474
11475/* ------------------------------ */
11476 .balign 128
11477.L_ALT_op_or_int_lit16: /* 0xd6 */
11478/* File: arm/alt_stub.S */
11479/*
11480 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11481 * any interesting requests and then jump to the real instruction
11482 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11483 */
11484 .extern MterpCheckBefore
11485 EXPORT_PC
11486 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11487 adrl lr, artMterpAsmInstructionStart + (214 * 128) @ Addr of primary handler.
11488 mov r0, rSELF
11489 add r1, rFP, #OFF_FP_SHADOWFRAME
11490 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11491
11492/* ------------------------------ */
11493 .balign 128
11494.L_ALT_op_xor_int_lit16: /* 0xd7 */
11495/* File: arm/alt_stub.S */
11496/*
11497 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11498 * any interesting requests and then jump to the real instruction
11499 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11500 */
11501 .extern MterpCheckBefore
11502 EXPORT_PC
11503 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11504 adrl lr, artMterpAsmInstructionStart + (215 * 128) @ Addr of primary handler.
11505 mov r0, rSELF
11506 add r1, rFP, #OFF_FP_SHADOWFRAME
11507 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11508
11509/* ------------------------------ */
11510 .balign 128
11511.L_ALT_op_add_int_lit8: /* 0xd8 */
11512/* File: arm/alt_stub.S */
11513/*
11514 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11515 * any interesting requests and then jump to the real instruction
11516 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11517 */
11518 .extern MterpCheckBefore
11519 EXPORT_PC
11520 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11521 adrl lr, artMterpAsmInstructionStart + (216 * 128) @ Addr of primary handler.
11522 mov r0, rSELF
11523 add r1, rFP, #OFF_FP_SHADOWFRAME
11524 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11525
11526/* ------------------------------ */
11527 .balign 128
11528.L_ALT_op_rsub_int_lit8: /* 0xd9 */
11529/* File: arm/alt_stub.S */
11530/*
11531 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11532 * any interesting requests and then jump to the real instruction
11533 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11534 */
11535 .extern MterpCheckBefore
11536 EXPORT_PC
11537 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11538 adrl lr, artMterpAsmInstructionStart + (217 * 128) @ Addr of primary handler.
11539 mov r0, rSELF
11540 add r1, rFP, #OFF_FP_SHADOWFRAME
11541 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11542
11543/* ------------------------------ */
11544 .balign 128
11545.L_ALT_op_mul_int_lit8: /* 0xda */
11546/* File: arm/alt_stub.S */
11547/*
11548 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11549 * any interesting requests and then jump to the real instruction
11550 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11551 */
11552 .extern MterpCheckBefore
11553 EXPORT_PC
11554 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11555 adrl lr, artMterpAsmInstructionStart + (218 * 128) @ Addr of primary handler.
11556 mov r0, rSELF
11557 add r1, rFP, #OFF_FP_SHADOWFRAME
11558 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11559
11560/* ------------------------------ */
11561 .balign 128
11562.L_ALT_op_div_int_lit8: /* 0xdb */
11563/* File: arm/alt_stub.S */
11564/*
11565 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11566 * any interesting requests and then jump to the real instruction
11567 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11568 */
11569 .extern MterpCheckBefore
11570 EXPORT_PC
11571 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11572 adrl lr, artMterpAsmInstructionStart + (219 * 128) @ Addr of primary handler.
11573 mov r0, rSELF
11574 add r1, rFP, #OFF_FP_SHADOWFRAME
11575 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11576
11577/* ------------------------------ */
11578 .balign 128
11579.L_ALT_op_rem_int_lit8: /* 0xdc */
11580/* File: arm/alt_stub.S */
11581/*
11582 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11583 * any interesting requests and then jump to the real instruction
11584 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11585 */
11586 .extern MterpCheckBefore
11587 EXPORT_PC
11588 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11589 adrl lr, artMterpAsmInstructionStart + (220 * 128) @ Addr of primary handler.
11590 mov r0, rSELF
11591 add r1, rFP, #OFF_FP_SHADOWFRAME
11592 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11593
11594/* ------------------------------ */
11595 .balign 128
11596.L_ALT_op_and_int_lit8: /* 0xdd */
11597/* File: arm/alt_stub.S */
11598/*
11599 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11600 * any interesting requests and then jump to the real instruction
11601 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11602 */
11603 .extern MterpCheckBefore
11604 EXPORT_PC
11605 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11606 adrl lr, artMterpAsmInstructionStart + (221 * 128) @ Addr of primary handler.
11607 mov r0, rSELF
11608 add r1, rFP, #OFF_FP_SHADOWFRAME
11609 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11610
11611/* ------------------------------ */
11612 .balign 128
11613.L_ALT_op_or_int_lit8: /* 0xde */
11614/* File: arm/alt_stub.S */
11615/*
11616 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11617 * any interesting requests and then jump to the real instruction
11618 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11619 */
11620 .extern MterpCheckBefore
11621 EXPORT_PC
11622 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11623 adrl lr, artMterpAsmInstructionStart + (222 * 128) @ Addr of primary handler.
11624 mov r0, rSELF
11625 add r1, rFP, #OFF_FP_SHADOWFRAME
11626 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11627
11628/* ------------------------------ */
11629 .balign 128
11630.L_ALT_op_xor_int_lit8: /* 0xdf */
11631/* File: arm/alt_stub.S */
11632/*
11633 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11634 * any interesting requests and then jump to the real instruction
11635 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11636 */
11637 .extern MterpCheckBefore
11638 EXPORT_PC
11639 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11640 adrl lr, artMterpAsmInstructionStart + (223 * 128) @ Addr of primary handler.
11641 mov r0, rSELF
11642 add r1, rFP, #OFF_FP_SHADOWFRAME
11643 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11644
11645/* ------------------------------ */
11646 .balign 128
11647.L_ALT_op_shl_int_lit8: /* 0xe0 */
11648/* File: arm/alt_stub.S */
11649/*
11650 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11651 * any interesting requests and then jump to the real instruction
11652 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11653 */
11654 .extern MterpCheckBefore
11655 EXPORT_PC
11656 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11657 adrl lr, artMterpAsmInstructionStart + (224 * 128) @ Addr of primary handler.
11658 mov r0, rSELF
11659 add r1, rFP, #OFF_FP_SHADOWFRAME
11660 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11661
11662/* ------------------------------ */
11663 .balign 128
11664.L_ALT_op_shr_int_lit8: /* 0xe1 */
11665/* File: arm/alt_stub.S */
11666/*
11667 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11668 * any interesting requests and then jump to the real instruction
11669 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11670 */
11671 .extern MterpCheckBefore
11672 EXPORT_PC
11673 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11674 adrl lr, artMterpAsmInstructionStart + (225 * 128) @ Addr of primary handler.
11675 mov r0, rSELF
11676 add r1, rFP, #OFF_FP_SHADOWFRAME
11677 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11678
11679/* ------------------------------ */
11680 .balign 128
11681.L_ALT_op_ushr_int_lit8: /* 0xe2 */
11682/* File: arm/alt_stub.S */
11683/*
11684 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11685 * any interesting requests and then jump to the real instruction
11686 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11687 */
11688 .extern MterpCheckBefore
11689 EXPORT_PC
11690 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11691 adrl lr, artMterpAsmInstructionStart + (226 * 128) @ Addr of primary handler.
11692 mov r0, rSELF
11693 add r1, rFP, #OFF_FP_SHADOWFRAME
11694 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11695
11696/* ------------------------------ */
11697 .balign 128
11698.L_ALT_op_iget_quick: /* 0xe3 */
11699/* File: arm/alt_stub.S */
11700/*
11701 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11702 * any interesting requests and then jump to the real instruction
11703 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11704 */
11705 .extern MterpCheckBefore
11706 EXPORT_PC
11707 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11708 adrl lr, artMterpAsmInstructionStart + (227 * 128) @ Addr of primary handler.
11709 mov r0, rSELF
11710 add r1, rFP, #OFF_FP_SHADOWFRAME
11711 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11712
11713/* ------------------------------ */
11714 .balign 128
11715.L_ALT_op_iget_wide_quick: /* 0xe4 */
11716/* File: arm/alt_stub.S */
11717/*
11718 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11719 * any interesting requests and then jump to the real instruction
11720 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11721 */
11722 .extern MterpCheckBefore
11723 EXPORT_PC
11724 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11725 adrl lr, artMterpAsmInstructionStart + (228 * 128) @ Addr of primary handler.
11726 mov r0, rSELF
11727 add r1, rFP, #OFF_FP_SHADOWFRAME
11728 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11729
11730/* ------------------------------ */
11731 .balign 128
11732.L_ALT_op_iget_object_quick: /* 0xe5 */
11733/* File: arm/alt_stub.S */
11734/*
11735 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11736 * any interesting requests and then jump to the real instruction
11737 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11738 */
11739 .extern MterpCheckBefore
11740 EXPORT_PC
11741 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11742 adrl lr, artMterpAsmInstructionStart + (229 * 128) @ Addr of primary handler.
11743 mov r0, rSELF
11744 add r1, rFP, #OFF_FP_SHADOWFRAME
11745 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11746
11747/* ------------------------------ */
11748 .balign 128
11749.L_ALT_op_iput_quick: /* 0xe6 */
11750/* File: arm/alt_stub.S */
11751/*
11752 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11753 * any interesting requests and then jump to the real instruction
11754 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11755 */
11756 .extern MterpCheckBefore
11757 EXPORT_PC
11758 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11759 adrl lr, artMterpAsmInstructionStart + (230 * 128) @ Addr of primary handler.
11760 mov r0, rSELF
11761 add r1, rFP, #OFF_FP_SHADOWFRAME
11762 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11763
11764/* ------------------------------ */
11765 .balign 128
11766.L_ALT_op_iput_wide_quick: /* 0xe7 */
11767/* File: arm/alt_stub.S */
11768/*
11769 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11770 * any interesting requests and then jump to the real instruction
11771 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11772 */
11773 .extern MterpCheckBefore
11774 EXPORT_PC
11775 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11776 adrl lr, artMterpAsmInstructionStart + (231 * 128) @ Addr of primary handler.
11777 mov r0, rSELF
11778 add r1, rFP, #OFF_FP_SHADOWFRAME
11779 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11780
11781/* ------------------------------ */
11782 .balign 128
11783.L_ALT_op_iput_object_quick: /* 0xe8 */
11784/* File: arm/alt_stub.S */
11785/*
11786 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11787 * any interesting requests and then jump to the real instruction
11788 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11789 */
11790 .extern MterpCheckBefore
11791 EXPORT_PC
11792 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11793 adrl lr, artMterpAsmInstructionStart + (232 * 128) @ Addr of primary handler.
11794 mov r0, rSELF
11795 add r1, rFP, #OFF_FP_SHADOWFRAME
11796 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11797
11798/* ------------------------------ */
11799 .balign 128
11800.L_ALT_op_invoke_virtual_quick: /* 0xe9 */
11801/* File: arm/alt_stub.S */
11802/*
11803 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11804 * any interesting requests and then jump to the real instruction
11805 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11806 */
11807 .extern MterpCheckBefore
11808 EXPORT_PC
11809 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11810 adrl lr, artMterpAsmInstructionStart + (233 * 128) @ Addr of primary handler.
11811 mov r0, rSELF
11812 add r1, rFP, #OFF_FP_SHADOWFRAME
11813 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11814
11815/* ------------------------------ */
11816 .balign 128
11817.L_ALT_op_invoke_virtual_range_quick: /* 0xea */
11818/* File: arm/alt_stub.S */
11819/*
11820 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11821 * any interesting requests and then jump to the real instruction
11822 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11823 */
11824 .extern MterpCheckBefore
11825 EXPORT_PC
11826 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11827 adrl lr, artMterpAsmInstructionStart + (234 * 128) @ Addr of primary handler.
11828 mov r0, rSELF
11829 add r1, rFP, #OFF_FP_SHADOWFRAME
11830 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11831
11832/* ------------------------------ */
11833 .balign 128
11834.L_ALT_op_iput_boolean_quick: /* 0xeb */
11835/* File: arm/alt_stub.S */
11836/*
11837 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11838 * any interesting requests and then jump to the real instruction
11839 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11840 */
11841 .extern MterpCheckBefore
11842 EXPORT_PC
11843 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11844 adrl lr, artMterpAsmInstructionStart + (235 * 128) @ Addr of primary handler.
11845 mov r0, rSELF
11846 add r1, rFP, #OFF_FP_SHADOWFRAME
11847 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11848
11849/* ------------------------------ */
11850 .balign 128
11851.L_ALT_op_iput_byte_quick: /* 0xec */
11852/* File: arm/alt_stub.S */
11853/*
11854 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11855 * any interesting requests and then jump to the real instruction
11856 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11857 */
11858 .extern MterpCheckBefore
11859 EXPORT_PC
11860 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11861 adrl lr, artMterpAsmInstructionStart + (236 * 128) @ Addr of primary handler.
11862 mov r0, rSELF
11863 add r1, rFP, #OFF_FP_SHADOWFRAME
11864 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11865
11866/* ------------------------------ */
11867 .balign 128
11868.L_ALT_op_iput_char_quick: /* 0xed */
11869/* File: arm/alt_stub.S */
11870/*
11871 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11872 * any interesting requests and then jump to the real instruction
11873 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11874 */
11875 .extern MterpCheckBefore
11876 EXPORT_PC
11877 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11878 adrl lr, artMterpAsmInstructionStart + (237 * 128) @ Addr of primary handler.
11879 mov r0, rSELF
11880 add r1, rFP, #OFF_FP_SHADOWFRAME
11881 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11882
11883/* ------------------------------ */
11884 .balign 128
11885.L_ALT_op_iput_short_quick: /* 0xee */
11886/* File: arm/alt_stub.S */
11887/*
11888 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11889 * any interesting requests and then jump to the real instruction
11890 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11891 */
11892 .extern MterpCheckBefore
11893 EXPORT_PC
11894 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11895 adrl lr, artMterpAsmInstructionStart + (238 * 128) @ Addr of primary handler.
11896 mov r0, rSELF
11897 add r1, rFP, #OFF_FP_SHADOWFRAME
11898 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11899
11900/* ------------------------------ */
11901 .balign 128
11902.L_ALT_op_iget_boolean_quick: /* 0xef */
11903/* File: arm/alt_stub.S */
11904/*
11905 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11906 * any interesting requests and then jump to the real instruction
11907 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11908 */
11909 .extern MterpCheckBefore
11910 EXPORT_PC
11911 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11912 adrl lr, artMterpAsmInstructionStart + (239 * 128) @ Addr of primary handler.
11913 mov r0, rSELF
11914 add r1, rFP, #OFF_FP_SHADOWFRAME
11915 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11916
11917/* ------------------------------ */
11918 .balign 128
11919.L_ALT_op_iget_byte_quick: /* 0xf0 */
11920/* File: arm/alt_stub.S */
11921/*
11922 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11923 * any interesting requests and then jump to the real instruction
11924 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11925 */
11926 .extern MterpCheckBefore
11927 EXPORT_PC
11928 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11929 adrl lr, artMterpAsmInstructionStart + (240 * 128) @ Addr of primary handler.
11930 mov r0, rSELF
11931 add r1, rFP, #OFF_FP_SHADOWFRAME
11932 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11933
11934/* ------------------------------ */
11935 .balign 128
11936.L_ALT_op_iget_char_quick: /* 0xf1 */
11937/* File: arm/alt_stub.S */
11938/*
11939 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11940 * any interesting requests and then jump to the real instruction
11941 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11942 */
11943 .extern MterpCheckBefore
11944 EXPORT_PC
11945 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11946 adrl lr, artMterpAsmInstructionStart + (241 * 128) @ Addr of primary handler.
11947 mov r0, rSELF
11948 add r1, rFP, #OFF_FP_SHADOWFRAME
11949 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11950
11951/* ------------------------------ */
11952 .balign 128
11953.L_ALT_op_iget_short_quick: /* 0xf2 */
11954/* File: arm/alt_stub.S */
11955/*
11956 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11957 * any interesting requests and then jump to the real instruction
11958 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11959 */
11960 .extern MterpCheckBefore
11961 EXPORT_PC
11962 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11963 adrl lr, artMterpAsmInstructionStart + (242 * 128) @ Addr of primary handler.
11964 mov r0, rSELF
11965 add r1, rFP, #OFF_FP_SHADOWFRAME
11966 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11967
11968/* ------------------------------ */
11969 .balign 128
11970.L_ALT_op_invoke_lambda: /* 0xf3 */
11971/* File: arm/alt_stub.S */
11972/*
11973 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11974 * any interesting requests and then jump to the real instruction
11975 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11976 */
11977 .extern MterpCheckBefore
11978 EXPORT_PC
11979 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11980 adrl lr, artMterpAsmInstructionStart + (243 * 128) @ Addr of primary handler.
11981 mov r0, rSELF
11982 add r1, rFP, #OFF_FP_SHADOWFRAME
11983 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
11984
11985/* ------------------------------ */
11986 .balign 128
11987.L_ALT_op_unused_f4: /* 0xf4 */
11988/* File: arm/alt_stub.S */
11989/*
11990 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11991 * any interesting requests and then jump to the real instruction
11992 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11993 */
11994 .extern MterpCheckBefore
11995 EXPORT_PC
11996 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
11997 adrl lr, artMterpAsmInstructionStart + (244 * 128) @ Addr of primary handler.
11998 mov r0, rSELF
11999 add r1, rFP, #OFF_FP_SHADOWFRAME
12000 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12001
12002/* ------------------------------ */
12003 .balign 128
12004.L_ALT_op_capture_variable: /* 0xf5 */
12005/* File: arm/alt_stub.S */
12006/*
12007 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12008 * any interesting requests and then jump to the real instruction
12009 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12010 */
12011 .extern MterpCheckBefore
12012 EXPORT_PC
12013 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12014 adrl lr, artMterpAsmInstructionStart + (245 * 128) @ Addr of primary handler.
12015 mov r0, rSELF
12016 add r1, rFP, #OFF_FP_SHADOWFRAME
12017 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12018
12019/* ------------------------------ */
12020 .balign 128
12021.L_ALT_op_create_lambda: /* 0xf6 */
12022/* File: arm/alt_stub.S */
12023/*
12024 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12025 * any interesting requests and then jump to the real instruction
12026 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12027 */
12028 .extern MterpCheckBefore
12029 EXPORT_PC
12030 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12031 adrl lr, artMterpAsmInstructionStart + (246 * 128) @ Addr of primary handler.
12032 mov r0, rSELF
12033 add r1, rFP, #OFF_FP_SHADOWFRAME
12034 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12035
12036/* ------------------------------ */
12037 .balign 128
12038.L_ALT_op_liberate_variable: /* 0xf7 */
12039/* File: arm/alt_stub.S */
12040/*
12041 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12042 * any interesting requests and then jump to the real instruction
12043 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12044 */
12045 .extern MterpCheckBefore
12046 EXPORT_PC
12047 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12048 adrl lr, artMterpAsmInstructionStart + (247 * 128) @ Addr of primary handler.
12049 mov r0, rSELF
12050 add r1, rFP, #OFF_FP_SHADOWFRAME
12051 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12052
12053/* ------------------------------ */
12054 .balign 128
12055.L_ALT_op_box_lambda: /* 0xf8 */
12056/* File: arm/alt_stub.S */
12057/*
12058 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12059 * any interesting requests and then jump to the real instruction
12060 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12061 */
12062 .extern MterpCheckBefore
12063 EXPORT_PC
12064 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12065 adrl lr, artMterpAsmInstructionStart + (248 * 128) @ Addr of primary handler.
12066 mov r0, rSELF
12067 add r1, rFP, #OFF_FP_SHADOWFRAME
12068 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12069
12070/* ------------------------------ */
12071 .balign 128
12072.L_ALT_op_unbox_lambda: /* 0xf9 */
12073/* File: arm/alt_stub.S */
12074/*
12075 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12076 * any interesting requests and then jump to the real instruction
12077 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12078 */
12079 .extern MterpCheckBefore
12080 EXPORT_PC
12081 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12082 adrl lr, artMterpAsmInstructionStart + (249 * 128) @ Addr of primary handler.
12083 mov r0, rSELF
12084 add r1, rFP, #OFF_FP_SHADOWFRAME
12085 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12086
12087/* ------------------------------ */
12088 .balign 128
12089.L_ALT_op_unused_fa: /* 0xfa */
12090/* File: arm/alt_stub.S */
12091/*
12092 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12093 * any interesting requests and then jump to the real instruction
12094 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12095 */
12096 .extern MterpCheckBefore
12097 EXPORT_PC
12098 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12099 adrl lr, artMterpAsmInstructionStart + (250 * 128) @ Addr of primary handler.
12100 mov r0, rSELF
12101 add r1, rFP, #OFF_FP_SHADOWFRAME
12102 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12103
12104/* ------------------------------ */
12105 .balign 128
12106.L_ALT_op_unused_fb: /* 0xfb */
12107/* File: arm/alt_stub.S */
12108/*
12109 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12110 * any interesting requests and then jump to the real instruction
12111 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12112 */
12113 .extern MterpCheckBefore
12114 EXPORT_PC
12115 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12116 adrl lr, artMterpAsmInstructionStart + (251 * 128) @ Addr of primary handler.
12117 mov r0, rSELF
12118 add r1, rFP, #OFF_FP_SHADOWFRAME
12119 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12120
12121/* ------------------------------ */
12122 .balign 128
12123.L_ALT_op_unused_fc: /* 0xfc */
12124/* File: arm/alt_stub.S */
12125/*
12126 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12127 * any interesting requests and then jump to the real instruction
12128 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12129 */
12130 .extern MterpCheckBefore
12131 EXPORT_PC
12132 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12133 adrl lr, artMterpAsmInstructionStart + (252 * 128) @ Addr of primary handler.
12134 mov r0, rSELF
12135 add r1, rFP, #OFF_FP_SHADOWFRAME
12136 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12137
12138/* ------------------------------ */
12139 .balign 128
12140.L_ALT_op_unused_fd: /* 0xfd */
12141/* File: arm/alt_stub.S */
12142/*
12143 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12144 * any interesting requests and then jump to the real instruction
12145 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12146 */
12147 .extern MterpCheckBefore
12148 EXPORT_PC
12149 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12150 adrl lr, artMterpAsmInstructionStart + (253 * 128) @ Addr of primary handler.
12151 mov r0, rSELF
12152 add r1, rFP, #OFF_FP_SHADOWFRAME
12153 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12154
12155/* ------------------------------ */
12156 .balign 128
12157.L_ALT_op_unused_fe: /* 0xfe */
12158/* File: arm/alt_stub.S */
12159/*
12160 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12161 * any interesting requests and then jump to the real instruction
12162 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12163 */
12164 .extern MterpCheckBefore
12165 EXPORT_PC
12166 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12167 adrl lr, artMterpAsmInstructionStart + (254 * 128) @ Addr of primary handler.
12168 mov r0, rSELF
12169 add r1, rFP, #OFF_FP_SHADOWFRAME
12170 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12171
12172/* ------------------------------ */
12173 .balign 128
12174.L_ALT_op_unused_ff: /* 0xff */
12175/* File: arm/alt_stub.S */
12176/*
12177 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12178 * any interesting requests and then jump to the real instruction
12179 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12180 */
12181 .extern MterpCheckBefore
12182 EXPORT_PC
12183 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE.
12184 adrl lr, artMterpAsmInstructionStart + (255 * 128) @ Addr of primary handler.
12185 mov r0, rSELF
12186 add r1, rFP, #OFF_FP_SHADOWFRAME
12187 b MterpCheckBefore @ (self, shadow_frame) @ Tail call.
12188
12189 .balign 128
12190 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart
12191 .global artMterpAsmAltInstructionEnd
12192artMterpAsmAltInstructionEnd:
12193/* File: arm/footer.S */
12194/*
12195 * ===========================================================================
12196 * Common subroutines and data
12197 * ===========================================================================
12198 */
12199
12200 .text
12201 .align 2
12202
12203/*
12204 * We've detected a condition that will result in an exception, but the exception
12205 * has not yet been thrown. Just bail out to the reference interpreter to deal with it.
12206 * TUNING: for consistency, we may want to just go ahead and handle these here.
12207 */
12208#define MTERP_LOGGING 0
12209common_errDivideByZero:
12210 EXPORT_PC
12211#if MTERP_LOGGING
12212 mov r0, rSELF
12213 add r1, rFP, #OFF_FP_SHADOWFRAME
12214 bl MterpLogDivideByZeroException
12215#endif
12216 b MterpCommonFallback
12217
12218common_errArrayIndex:
12219 EXPORT_PC
12220#if MTERP_LOGGING
12221 mov r0, rSELF
12222 add r1, rFP, #OFF_FP_SHADOWFRAME
12223 bl MterpLogArrayIndexException
12224#endif
12225 b MterpCommonFallback
12226
12227common_errNegativeArraySize:
12228 EXPORT_PC
12229#if MTERP_LOGGING
12230 mov r0, rSELF
12231 add r1, rFP, #OFF_FP_SHADOWFRAME
12232 bl MterpLogNegativeArraySizeException
12233#endif
12234 b MterpCommonFallback
12235
12236common_errNoSuchMethod:
12237 EXPORT_PC
12238#if MTERP_LOGGING
12239 mov r0, rSELF
12240 add r1, rFP, #OFF_FP_SHADOWFRAME
12241 bl MterpLogNoSuchMethodException
12242#endif
12243 b MterpCommonFallback
12244
12245common_errNullObject:
12246 EXPORT_PC
12247#if MTERP_LOGGING
12248 mov r0, rSELF
12249 add r1, rFP, #OFF_FP_SHADOWFRAME
12250 bl MterpLogNullObjectException
12251#endif
12252 b MterpCommonFallback
12253
12254common_exceptionThrown:
12255 EXPORT_PC
12256#if MTERP_LOGGING
12257 mov r0, rSELF
12258 add r1, rFP, #OFF_FP_SHADOWFRAME
12259 bl MterpLogExceptionThrownException
12260#endif
12261 b MterpCommonFallback
12262
12263MterpSuspendFallback:
12264 EXPORT_PC
12265#if MTERP_LOGGING
12266 mov r0, rSELF
12267 add r1, rFP, #OFF_FP_SHADOWFRAME
12268 ldr r2, [rSELF, #THREAD_FLAGS_OFFSET]
12269 bl MterpLogSuspendFallback
12270#endif
12271 b MterpCommonFallback
12272
12273/*
12274 * If we're here, something is out of the ordinary. If there is a pending
12275 * exception, handle it. Otherwise, roll back and retry with the reference
12276 * interpreter.
12277 */
12278MterpPossibleException:
12279 ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET]
12280 cmp r0, #0 @ Exception pending?
12281 beq MterpFallback @ If not, fall back to reference interpreter.
12282 /* intentional fallthrough - handle pending exception. */
12283/*
12284 * On return from a runtime helper routine, we've found a pending exception.
12285 * Can we handle it here - or need to bail out to caller?
12286 *
12287 */
12288MterpException:
12289 mov r0, rSELF
12290 add r1, rFP, #OFF_FP_SHADOWFRAME
12291 bl MterpHandleException @ (self, shadow_frame)
12292 cmp r0, #0
12293 beq MterpExceptionReturn @ no local catch, back to caller.
12294 ldr r0, [rFP, #OFF_FP_CODE_ITEM]
12295 ldr r1, [rFP, #OFF_FP_DEX_PC]
12296 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET]
12297 add rPC, r0, #CODEITEM_INSNS_OFFSET
12298 add rPC, rPC, r1, lsl #1 @ generate new dex_pc_ptr
12299 str rPC, [rFP, #OFF_FP_DEX_PC_PTR]
12300 /* resume execution at catch block */
12301 FETCH_INST
12302 GET_INST_OPCODE ip
12303 GOTO_OPCODE ip
12304 /* NOTE: no fallthrough */
12305
12306/*
12307 * Check for suspend check request. Assumes rINST already loaded, rPC advanced and
12308 * still needs to get the opcode and branch to it, and flags are in lr.
12309 */
12310MterpCheckSuspendAndContinue:
12311 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh rIBASE
12312 EXPORT_PC
12313 mov r0, rSELF
12314 ands lr, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
12315 blne MterpSuspendCheck @ (self)
12316 GET_INST_OPCODE ip @ extract opcode from rINST
12317 GOTO_OPCODE ip @ jump to next instruction
12318
12319/*
buzbeea0a16102016-02-03 15:23:56 -0800[diff] [blame^]12320 * On-stack replacement pending.
12321 * Branch offset in rINST on entry.
12322 */
12323MterpOnStackReplacement:
12324#if MTERP_LOGGING
12325 mov r0, rSELF
12326 add r1, rFP, #OFF_FP_SHADOWFRAME
12327 mov r2, rINST
12328 bl MterpLogOSR
12329#endif
12330 b MterpFallback @ Let the reference interpreter deal with it.
12331/*
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]12332 * Bail out to reference interpreter.
12333 */
12334MterpFallback:
12335 EXPORT_PC
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]12336#if MTERP_LOGGING
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]12337 mov r0, rSELF
12338 add r1, rFP, #OFF_FP_SHADOWFRAME
12339 bl MterpLogFallback
buzbee76833da2016-01-13 13:06:22 -0800[diff] [blame]12340#endif
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]12341MterpCommonFallback:
12342 mov r0, #0 @ signal retry with reference interpreter.
12343 b MterpDone
12344
12345/*
12346 * We pushed some registers on the stack in ExecuteMterpImpl, then saved
12347 * SP and LR. Here we restore SP, restore the registers, and then restore
12348 * LR to PC.
12349 *
12350 * On entry:
12351 * uint32_t* rFP (should still be live, pointer to base of vregs)
12352 */
12353MterpExceptionReturn:
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]12354 mov r0, #1 @ signal return to caller.
12355 b MterpDone
12356MterpReturn:
12357 ldr r2, [rFP, #OFF_FP_RESULT_REGISTER]
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]12358 str r0, [r2]
12359 str r1, [r2, #4]
buzbee1452bee2015-03-06 14:43:04 -0800[diff] [blame]12360 mov r0, #1 @ signal return to caller.
12361MterpDone:
12362 add sp, sp, #4 @ un-align 64
12363 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return
12364
12365
12366 .fnend
12367 .size ExecuteMterpImpl, .-ExecuteMterpImpl
12368
12369