Gitiles
Code Review Sign In
review.blissroms.org / platform_art / a5954be0aac5edd892fb31a209960543d00e4500 / . / src / compiler / codegen / arm / codegen_arm.h
blob: 9342620c1dd11a6a433c95d7177c91c69f9c6ab6 [file] [log] [blame]
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_SRC_COMPILER_CODEGEN_ARM_CODEGENARM_H_
18#define ART_SRC_COMPILER_CODEGEN_ARM_CODEGENARM_H_
19
Brian Carlstrom641ce032013-01-31 15:21:37 -0800[diff] [blame]20#include "compiler/compiler_internals.h"
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]21
22namespace art {
23
24class ArmCodegen : public Codegen {
25 public:
26 // Required for target - codegen helpers.
27 virtual bool SmallLiteralDivide(CompilationUnit* cu, Instruction::Code dalvik_opcode,
28 RegLocation rl_src, RegLocation rl_dest, int lit);
29 virtual int LoadHelper(CompilationUnit* cu, int offset);
30 virtual LIR* LoadBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest,
31 OpSize size, int s_reg);
32 virtual LIR* LoadBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_dest_lo,
33 int r_dest_hi, int s_reg);
34 virtual LIR* LoadBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_dest, int scale,
35 OpSize size);
36 virtual LIR* LoadBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
37 int displacement, int r_dest, int r_dest_hi, OpSize size,
38 int s_reg);
39 virtual LIR* LoadConstantNoClobber(CompilationUnit* cu, int r_dest, int value);
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]40 virtual LIR* LoadConstantWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi, int64_t value);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]41 virtual LIR* StoreBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_src,
42 OpSize size);
43 virtual LIR* StoreBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_src_lo,
44 int r_src_hi);
45 virtual LIR* StoreBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_src, int scale,
46 OpSize size);
47 virtual LIR* StoreBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
48 int displacement, int r_src, int r_src_hi, OpSize size,
49 int s_reg);
50 virtual void MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg);
51
52 // Required for target - register utilities.
53 virtual bool IsFpReg(int reg);
54 virtual bool SameRegType(int reg1, int reg2);
55 virtual int AllocTypedTemp(CompilationUnit* cu, bool fp_hint, int reg_class);
56 virtual int AllocTypedTempPair(CompilationUnit* cu, bool fp_hint, int reg_class);
57 virtual int S2d(int low_reg, int high_reg);
58 virtual int TargetReg(SpecialTargetRegister reg);
59 virtual RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg);
60 virtual RegLocation GetReturnAlt(CompilationUnit* cu);
61 virtual RegLocation GetReturnWideAlt(CompilationUnit* cu);
62 virtual RegLocation LocCReturn();
63 virtual RegLocation LocCReturnDouble();
64 virtual RegLocation LocCReturnFloat();
65 virtual RegLocation LocCReturnWide();
66 virtual uint32_t FpRegMask();
67 virtual uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg);
68 virtual void AdjustSpillMask(CompilationUnit* cu);
69 virtual void ClobberCalleeSave(CompilationUnit *cu);
70 virtual void FlushReg(CompilationUnit* cu, int reg);
71 virtual void FlushRegWide(CompilationUnit* cu, int reg1, int reg2);
72 virtual void FreeCallTemps(CompilationUnit* cu);
73 virtual void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free);
74 virtual void LockCallTemps(CompilationUnit* cu);
75 virtual void MarkPreservedSingle(CompilationUnit* cu, int v_reg, int reg);
76 virtual void CompilerInitializeRegAlloc(CompilationUnit* cu);
77
78 // Required for target - miscellaneous.
79 virtual AssemblerStatus AssembleInstructions(CompilationUnit* cu, uintptr_t start_addr);
80 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
81 virtual void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir);
82 virtual const char* GetTargetInstFmt(int opcode);
83 virtual const char* GetTargetInstName(int opcode);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]84 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
85 virtual uint64_t GetPCUseDefEncoding();
86 virtual uint64_t GetTargetInstFlags(int opcode);
87 virtual int GetInsnSize(LIR* lir);
88 virtual bool IsUnconditionalBranch(LIR* lir);
89
90 // Required for target - Dalvik-level generators.
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]91 virtual void GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]92 RegLocation rl_src1, RegLocation rl_src2);
buzbeee6285f92012-12-06 15:57:46 -0800[diff] [blame]93 virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
94 RegLocation rl_index, RegLocation rl_src, int scale);
95 virtual void GenArrayGet(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
96 RegLocation rl_index, RegLocation rl_dest, int scale);
97 virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
98 RegLocation rl_index, RegLocation rl_src, int scale);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]99 virtual void GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode,
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]100 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift);
101 virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
102 RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]103 virtual void GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]104 RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]105 virtual void GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]106 RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]107 virtual void GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]108 RegLocation rl_dest, RegLocation rl_src1,
109 RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]110 virtual void GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]111 RegLocation rl_src1, RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]112 virtual void GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]113 RegLocation rl_src1, RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]114 virtual void GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]115 RegLocation rl_src);
116 virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier);
117 virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min);
118 virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]119 virtual void GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
120 virtual void GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]121 RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]122 virtual void GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]123 RegLocation rl_src2);
buzbeea5954be2013-02-07 10:41:40 -0800[diff] [blame^]124 virtual void GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]125 RegLocation rl_src2);
126 virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
127 int offset, ThrowKind kind);
128 virtual RegLocation GenDivRem(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int reg_hi,
129 bool is_div);
130 virtual RegLocation GenDivRemLit(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int lit,
131 bool is_div);
132 virtual void GenCmpLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
133 RegLocation rl_src2);
134 virtual void GenDivZeroCheck(CompilationUnit* cu, int reg_lo, int reg_hi);
135 virtual void GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs,
136 RegLocation rl_method);
137 virtual void GenExitSequence(CompilationUnit* cu);
138 virtual void GenFillArrayData(CompilationUnit* cu, uint32_t table_offset,
139 RegLocation rl_src);
140 virtual void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
141 bool is_double);
142 virtual void GenFusedLongCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir);
143 virtual void GenMemBarrier(CompilationUnit* cu, MemBarrierKind barrier_kind);
144 virtual void GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src);
145 virtual void GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src);
jeffhao1eab9582013-01-22 13:33:52 -0800[diff] [blame]146 virtual void GenMoveException(CompilationUnit* cu, RegLocation rl_dest);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]147 virtual void GenMultiplyByTwoBitMultiplier(CompilationUnit* cu, RegLocation rl_src,
148 RegLocation rl_result, int lit, int first_bit,
149 int second_bit);
150 virtual void GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
151 virtual void GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
152 virtual void GenPackedSwitch(CompilationUnit* cu, uint32_t table_offset,
153 RegLocation rl_src);
154 virtual void GenSparseSwitch(CompilationUnit* cu, uint32_t table_offset,
155 RegLocation rl_src);
156 virtual void GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
157 SpecialCaseHandler special_case);
158
159 // Required for target - single operation generators.
160 virtual LIR* OpUnconditionalBranch(CompilationUnit* cu, LIR* target);
161 virtual LIR* OpCmpBranch(CompilationUnit* cu, ConditionCode cond, int src1, int src2,
162 LIR* target);
163 virtual LIR* OpCmpImmBranch(CompilationUnit* cu, ConditionCode cond, int reg, int check_value,
164 LIR* target);
165 virtual LIR* OpCondBranch(CompilationUnit* cu, ConditionCode cc, LIR* target);
166 virtual LIR* OpDecAndBranch(CompilationUnit* cu, ConditionCode c_code, int reg,
167 LIR* target);
168 virtual LIR* OpFpRegCopy(CompilationUnit* cu, int r_dest, int r_src);
169 virtual LIR* OpIT(CompilationUnit* cu, ConditionCode cond, const char* guide);
170 virtual LIR* OpMem(CompilationUnit* cu, OpKind op, int rBase, int disp);
171 virtual LIR* OpPcRelLoad(CompilationUnit* cu, int reg, LIR* target);
172 virtual LIR* OpReg(CompilationUnit* cu, OpKind op, int r_dest_src);
173 virtual LIR* OpRegCopy(CompilationUnit* cu, int r_dest, int r_src);
174 virtual LIR* OpRegCopyNoInsert(CompilationUnit* cu, int r_dest, int r_src);
175 virtual LIR* OpRegImm(CompilationUnit* cu, OpKind op, int r_dest_src1, int value);
176 virtual LIR* OpRegMem(CompilationUnit* cu, OpKind op, int r_dest, int rBase, int offset);
177 virtual LIR* OpRegReg(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2);
178 virtual LIR* OpRegRegImm(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int value);
179 virtual LIR* OpRegRegReg(CompilationUnit* cu, OpKind op, int r_dest, int r_src1,
180 int r_src2);
181 virtual LIR* OpTestSuspend(CompilationUnit* cu, LIR* target);
182 virtual LIR* OpThreadMem(CompilationUnit* cu, OpKind op, int thread_offset);
183 virtual LIR* OpVldm(CompilationUnit* cu, int rBase, int count);
184 virtual LIR* OpVstm(CompilationUnit* cu, int rBase, int count);
185 virtual void OpLea(CompilationUnit* cu, int rBase, int reg1, int reg2, int scale,
186 int offset);
187 virtual void OpRegCopyWide(CompilationUnit* cu, int dest_lo, int dest_hi, int src_lo,
188 int src_hi);
189 virtual void OpTlsCmp(CompilationUnit* cu, int offset, int val);
190
191 static RegLocation ArgLoc(CompilationUnit* cu, RegLocation loc);
192 LIR* LoadBaseDispBody(CompilationUnit* cu, int rBase, int displacement, int r_dest,
193 int r_dest_hi, OpSize size, int s_reg);
194 LIR* StoreBaseDispBody(CompilationUnit* cu, int rBase, int displacement, int r_src,
195 int r_src_hi, OpSize size);
196 static void GenPrintLabel(CompilationUnit *cu, MIR* mir);
197 static LIR* OpRegRegRegShift(CompilationUnit* cu, OpKind op, int r_dest, int r_src1,
198 int r_src2, int shift);
199 static LIR* OpRegRegShift(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2,
200 int shift);
201 static const ArmEncodingMap EncodingMap[kArmLast];
202 static int EncodeShift(int code, int amount);
203 static int ModifiedImmediate(uint32_t value);
204 static ArmConditionCode ArmConditionEncoding(ConditionCode code);
buzbee4ef3e452012-12-14 13:35:28 -0800[diff] [blame]205 bool InexpensiveConstantInt(int32_t value);
206 bool InexpensiveConstantFloat(int32_t value);
207 bool InexpensiveConstantLong(int64_t value);
208 bool InexpensiveConstantDouble(int64_t value);
209
210 private:
211 void GenFusedLongCmpImmBranch(CompilationUnit* cu, BasicBlock* bb, RegLocation rl_src1,
212 int64_t val, ConditionCode ccode);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]213};
214
215} // namespace art
216
217#endif // ART_SRC_COMPILER_CODEGEN_ARM_CODEGENARM_H_