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review.blissroms.org / platform_art / b48819db07f9a0992a72173380c24249d7fc648a / . / compiler / dex / quick / mips / codegen_mips.h
blob: 9671a78497a2590c49300c9a9f683aa453e0fa9c [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700[diff] [blame]17#ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
18#define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]19
20#include "dex/compiler_internals.h"
21#include "mips_lir.h"
22
23namespace art {
24
25class MipsMir2Lir : public Mir2Lir {
26 public:
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]27 MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29 // Required for target - codegen utilities.
buzbee11b63d12013-08-27 07:34:17 -0700[diff] [blame]30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]31 RegLocation rl_dest, int lit);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]32 int LoadHelper(ThreadOffset offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
35 int s_reg);
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
38 int r_dest, int r_dest_hi, OpSize size, int s_reg);
39 LIR* LoadConstantNoClobber(int r_dest, int value);
40 LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
45 int r_src, int r_src_hi, OpSize size, int s_reg);
46 void MarkGCCard(int val_reg, int tgt_addr_reg);
47
48 // Required for target - register utilities.
49 bool IsFpReg(int reg);
50 bool SameRegType(int reg1, int reg2);
51 int AllocTypedTemp(bool fp_hint, int reg_class);
52 int AllocTypedTempPair(bool fp_hint, int reg_class);
53 int S2d(int low_reg, int high_reg);
54 int TargetReg(SpecialTargetRegister reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]55 RegLocation GetReturnAlt();
56 RegLocation GetReturnWideAlt();
57 RegLocation LocCReturn();
58 RegLocation LocCReturnDouble();
59 RegLocation LocCReturnFloat();
60 RegLocation LocCReturnWide();
61 uint32_t FpRegMask();
62 uint64_t GetRegMaskCommon(int reg);
63 void AdjustSpillMask();
64 void ClobberCalleeSave();
65 void FlushReg(int reg);
66 void FlushRegWide(int reg1, int reg2);
67 void FreeCallTemps();
68 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
69 void LockCallTemps();
70 void MarkPreservedSingle(int v_reg, int reg);
71 void CompilerInitializeRegAlloc();
72
73 // Required for target - miscellaneous.
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame^]74 void AssembleLIR();
75 int AssignInsnOffsets();
76 void AssignOffsets();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]77 AssemblerStatus AssembleInstructions(uintptr_t start_addr);
78 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame^]79 void SetupTargetResourceMasks(LIR* lir, uint64_t flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]80 const char* GetTargetInstFmt(int opcode);
81 const char* GetTargetInstName(int opcode);
82 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
83 uint64_t GetPCUseDefEncoding();
84 uint64_t GetTargetInstFlags(int opcode);
85 int GetInsnSize(LIR* lir);
86 bool IsUnconditionalBranch(LIR* lir);
87
88 // Required for target - Dalvik-level generators.
89 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
90 RegLocation rl_src1, RegLocation rl_src2);
91 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index,
92 RegLocation rl_src, int scale);
93 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
94 RegLocation rl_index, RegLocation rl_dest, int scale);
95 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
96 RegLocation rl_index, RegLocation rl_src, int scale);
97 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
98 RegLocation rl_src1, RegLocation rl_shift);
99 void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
100 void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
101 void GenAndLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
102 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
103 RegLocation rl_src1, RegLocation rl_src2);
104 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
105 RegLocation rl_src1, RegLocation rl_src2);
106 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
107 RegLocation rl_src2);
108 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
109 bool GenInlinedCas32(CallInfo* info, bool need_write_barrier);
110 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
111 bool GenInlinedSqrt(CallInfo* info);
112 void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
113 void GenOrLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
114 void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
115 void GenXorLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
116 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
117 ThrowKind kind);
118 RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
119 RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
120 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
121 void GenDivZeroCheck(int reg_lo, int reg_hi);
122 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
123 void GenExitSequence();
124 void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
125 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
126 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
127 void GenSelect(BasicBlock* bb, MIR* mir);
128 void GenMemBarrier(MemBarrierKind barrier_kind);
129 void GenMonitorEnter(int opt_flags, RegLocation rl_src);
130 void GenMonitorExit(int opt_flags, RegLocation rl_src);
131 void GenMoveException(RegLocation rl_dest);
132 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
133 int first_bit, int second_bit);
134 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
135 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
136 void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
137 void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
138 void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
139
140 // Required for target - single operation generators.
141 LIR* OpUnconditionalBranch(LIR* target);
142 LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
143 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
144 LIR* OpCondBranch(ConditionCode cc, LIR* target);
145 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
146 LIR* OpFpRegCopy(int r_dest, int r_src);
147 LIR* OpIT(ConditionCode cond, const char* guide);
148 LIR* OpMem(OpKind op, int rBase, int disp);
149 LIR* OpPcRelLoad(int reg, LIR* target);
150 LIR* OpReg(OpKind op, int r_dest_src);
151 LIR* OpRegCopy(int r_dest, int r_src);
152 LIR* OpRegCopyNoInsert(int r_dest, int r_src);
153 LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
154 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
155 LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
156 LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
157 LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
158 LIR* OpTestSuspend(LIR* target);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]159 LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]160 LIR* OpVldm(int rBase, int count);
161 LIR* OpVstm(int rBase, int count);
162 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
163 void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]164 void OpTlsCmp(ThreadOffset offset, int val);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]165
166 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
167 int s_reg);
168 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
169 void SpillCoreRegs();
170 void UnSpillCoreRegs();
171 static const MipsEncodingMap EncodingMap[kMipsLast];
172 bool InexpensiveConstantInt(int32_t value);
173 bool InexpensiveConstantFloat(int32_t value);
174 bool InexpensiveConstantLong(int64_t value);
175 bool InexpensiveConstantDouble(int64_t value);
176
177 private:
178 void ConvertShortToLongBranch(LIR* lir);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]179};
180
181} // namespace art
182
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700[diff] [blame]183#endif // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_