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review.blissroms.org / platform_art / d0379748bd05b949a8e2193b44ddf4950f9569a8 / . / src / compiler / Dataflow.cc
blob: 2ba0cc1f96bc824f308484d18812fdfb8f5cc621 [file] [log] [blame]
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "Dalvik.h"
18#include "Dataflow.h"
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]19
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]20namespace art {
21
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]22/*
23 * Main table containing data flow attributes for each bytecode. The
24 * first kNumPackedOpcodes entries are for Dalvik bytecode
25 * instructions, where extended opcode at the MIR level are appended
26 * afterwards.
27 *
28 * TODO - many optimization flags are incomplete - they will only limit the
29 * scope of optimizations but will not cause mis-optimizations.
30 */
buzbeeba938cb2012-02-03 14:47:55 -0800[diff] [blame]31const int oatDataFlowAttributes[kMirOpLast] = {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]32 // 00 NOP
33 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]34
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]35 // 01 MOVE vA, vB
36 DF_DA | DF_UB | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]37
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]38 // 02 MOVE_FROM16 vAA, vBBBB
39 DF_DA | DF_UB | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]40
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]41 // 03 MOVE_16 vAAAA, vBBBB
42 DF_DA | DF_UB | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]43
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]44 // 04 MOVE_WIDE vA, vB
45 DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]46
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]47 // 05 MOVE_WIDE_FROM16 vAA, vBBBB
48 DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]49
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]50 // 06 MOVE_WIDE_16 vAAAA, vBBBB
51 DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]52
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]53 // 07 MOVE_OBJECT vA, vB
54 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]55
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]56 // 08 MOVE_OBJECT_FROM16 vAA, vBBBB
57 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]58
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]59 // 09 MOVE_OBJECT_16 vAAAA, vBBBB
60 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]61
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]62 // 0A MOVE_RESULT vAA
63 DF_DA,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]64
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]65 // 0B MOVE_RESULT_WIDE vAA
66 DF_DA_WIDE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]67
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]68 // 0C MOVE_RESULT_OBJECT vAA
69 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]70
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]71 // 0D MOVE_EXCEPTION vAA
72 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]73
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]74 // 0E RETURN_VOID
75 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]76
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]77 // 0F RETURN vAA
78 DF_UA,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]79
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]80 // 10 RETURN_WIDE vAA
81 DF_UA_WIDE,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]82
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]83 // 11 RETURN_OBJECT vAA
84 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]85
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]86 // 12 CONST_4 vA, #+B
87 DF_DA | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]88
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]89 // 13 CONST_16 vAA, #+BBBB
90 DF_DA | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]91
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]92 // 14 CONST vAA, #+BBBBBBBB
93 DF_DA | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]94
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]95 // 15 CONST_HIGH16 VAA, #+BBBB0000
96 DF_DA | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]97
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]98 // 16 CONST_WIDE_16 vAA, #+BBBB
99 DF_DA_WIDE | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]100
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]101 // 17 CONST_WIDE_32 vAA, #+BBBBBBBB
102 DF_DA_WIDE | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]103
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]104 // 18 CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
105 DF_DA_WIDE | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]106
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]107 // 19 CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
108 DF_DA_WIDE | DF_SETS_CONST,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]109
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]110 // 1A CONST_STRING vAA, string@BBBB
111 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]112
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]113 // 1B CONST_STRING_JUMBO vAA, string@BBBBBBBB
114 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]115
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]116 // 1C CONST_CLASS vAA, type@BBBB
117 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]118
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]119 // 1D MONITOR_ENTER vAA
120 DF_UA | DF_NULL_CHK_0 | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]121
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]122 // 1E MONITOR_EXIT vAA
123 DF_UA | DF_NULL_CHK_0 | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]124
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]125 // 1F CHK_CAST vAA, type@BBBB
126 DF_UA | DF_CORE_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]127
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]128 // 20 INSTANCE_OF vA, vB, type@CCCC
129 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]130
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]131 // 21 ARRAY_LENGTH vA, vB
132 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]133
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]134 // 22 NEW_INSTANCE vAA, type@BBBB
135 DF_DA | DF_NON_NULL_DST | DF_CORE_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]136
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]137 // 23 NEW_ARRAY vA, vB, type@CCCC
138 DF_DA | DF_UB | DF_NON_NULL_DST | DF_CORE_A | DF_CORE_B | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]139
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]140 // 24 FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
141 DF_FORMAT_35C | DF_NON_NULL_RET | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]142
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]143 // 25 FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB
144 DF_FORMAT_3RC | DF_NON_NULL_RET | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]145
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]146 // 26 FILL_ARRAY_DATA vAA, +BBBBBBBB
147 DF_UA | DF_CORE_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]148
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]149 // 27 THROW vAA
150 DF_UA | DF_CORE_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]151
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]152 // 28 GOTO
153 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]154
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]155 // 29 GOTO_16
156 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]157
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]158 // 2A GOTO_32
159 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]160
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]161 // 2B PACKED_SWITCH vAA, +BBBBBBBB
162 DF_UA,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]163
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]164 // 2C SPARSE_SWITCH vAA, +BBBBBBBB
165 DF_UA,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]166
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]167 // 2D CMPL_FLOAT vAA, vBB, vCC
168 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]169
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]170 // 2E CMPG_FLOAT vAA, vBB, vCC
171 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]172
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]173 // 2F CMPL_DOUBLE vAA, vBB, vCC
174 DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]175
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]176 // 30 CMPG_DOUBLE vAA, vBB, vCC
177 DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]178
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]179 // 31 CMP_LONG vAA, vBB, vCC
180 DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]181
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]182 // 32 IF_EQ vA, vB, +CCCC
183 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]184
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]185 // 33 IF_NE vA, vB, +CCCC
186 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]187
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]188 // 34 IF_LT vA, vB, +CCCC
189 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]190
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]191 // 35 IF_GE vA, vB, +CCCC
192 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]193
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]194 // 36 IF_GT vA, vB, +CCCC
195 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]196
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]197 // 37 IF_LE vA, vB, +CCCC
198 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]199
200
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]201 // 38 IF_EQZ vAA, +BBBB
202 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]203
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]204 // 39 IF_NEZ vAA, +BBBB
205 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]206
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]207 // 3A IF_LTZ vAA, +BBBB
208 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]209
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]210 // 3B IF_GEZ vAA, +BBBB
211 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]212
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]213 // 3C IF_GTZ vAA, +BBBB
214 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]215
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]216 // 3D IF_LEZ vAA, +BBBB
217 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]218
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]219 // 3E UNUSED_3E
220 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]221
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]222 // 3F UNUSED_3F
223 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]224
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]225 // 40 UNUSED_40
226 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]227
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]228 // 41 UNUSED_41
229 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]230
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]231 // 42 UNUSED_42
232 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]233
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]234 // 43 UNUSED_43
235 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]236
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]237 // 44 AGET vAA, vBB, vCC
238 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]239
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]240 // 45 AGET_WIDE vAA, vBB, vCC
241 DF_DA_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]242
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]243 // 46 AGET_OBJECT vAA, vBB, vCC
244 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]245
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]246 // 47 AGET_BOOLEAN vAA, vBB, vCC
247 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]248
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]249 // 48 AGET_BYTE vAA, vBB, vCC
250 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]251
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]252 // 49 AGET_CHAR vAA, vBB, vCC
253 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]254
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]255 // 4A AGET_SHORT vAA, vBB, vCC
256 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]257
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]258 // 4B APUT vAA, vBB, vCC
259 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]260
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]261 // 4C APUT_WIDE vAA, vBB, vCC
262 DF_UA_WIDE | DF_UB | DF_UC | DF_NULL_CHK_2 | DF_RANGE_CHK_3 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]263
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]264 // 4D APUT_OBJECT vAA, vBB, vCC
265 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]266
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]267 // 4E APUT_BOOLEAN vAA, vBB, vCC
268 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]269
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]270 // 4F APUT_BYTE vAA, vBB, vCC
271 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]272
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]273 // 50 APUT_CHAR vAA, vBB, vCC
274 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]275
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]276 // 51 APUT_SHORT vAA, vBB, vCC
277 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]278
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]279 // 52 IGET vA, vB, field@CCCC
280 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]281
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]282 // 53 IGET_WIDE vA, vB, field@CCCC
283 DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]284
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]285 // 54 IGET_OBJECT vA, vB, field@CCCC
286 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]287
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]288 // 55 IGET_BOOLEAN vA, vB, field@CCCC
289 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]290
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]291 // 56 IGET_BYTE vA, vB, field@CCCC
292 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]293
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]294 // 57 IGET_CHAR vA, vB, field@CCCC
295 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]296
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]297 // 58 IGET_SHORT vA, vB, field@CCCC
298 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]299
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]300 // 59 IPUT vA, vB, field@CCCC
301 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]302
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]303 // 5A IPUT_WIDE vA, vB, field@CCCC
304 DF_UA_WIDE | DF_UB | DF_NULL_CHK_2 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]305
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]306 // 5B IPUT_OBJECT vA, vB, field@CCCC
307 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]308
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]309 // 5C IPUT_BOOLEAN vA, vB, field@CCCC
310 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]311
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]312 // 5D IPUT_BYTE vA, vB, field@CCCC
313 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]314
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]315 // 5E IPUT_CHAR vA, vB, field@CCCC
316 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]317
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]318 // 5F IPUT_SHORT vA, vB, field@CCCC
319 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]320
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]321 // 60 SGET vAA, field@BBBB
322 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]323
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]324 // 61 SGET_WIDE vAA, field@BBBB
325 DF_DA_WIDE | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]326
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]327 // 62 SGET_OBJECT vAA, field@BBBB
328 DF_DA | DF_CORE_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]329
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]330 // 63 SGET_BOOLEAN vAA, field@BBBB
331 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]332
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]333 // 64 SGET_BYTE vAA, field@BBBB
334 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]335
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]336 // 65 SGET_CHAR vAA, field@BBBB
337 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]338
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]339 // 66 SGET_SHORT vAA, field@BBBB
340 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]341
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]342 // 67 SPUT vAA, field@BBBB
343 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]344
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]345 // 68 SPUT_WIDE vAA, field@BBBB
346 DF_UA_WIDE | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]347
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]348 // 69 SPUT_OBJECT vAA, field@BBBB
349 DF_UA | DF_CORE_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]350
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]351 // 6A SPUT_BOOLEAN vAA, field@BBBB
352 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]353
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]354 // 6B SPUT_BYTE vAA, field@BBBB
355 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]356
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]357 // 6C SPUT_CHAR vAA, field@BBBB
358 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]359
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]360 // 6D SPUT_SHORT vAA, field@BBBB
361 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]362
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]363 // 6E INVOKE_VIRTUAL {vD, vE, vF, vG, vA}
364 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]365
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]366 // 6F INVOKE_SUPER {vD, vE, vF, vG, vA}
367 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]368
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]369 // 70 INVOKE_DIRECT {vD, vE, vF, vG, vA}
370 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]371
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]372 // 71 INVOKE_STATIC {vD, vE, vF, vG, vA}
373 DF_FORMAT_35C | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]374
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]375 // 72 INVOKE_INTERFACE {vD, vE, vF, vG, vA}
376 DF_FORMAT_35C | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]377
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]378 // 73 UNUSED_73
379 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]380
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]381 // 74 INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN}
382 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]383
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]384 // 75 INVOKE_SUPER_RANGE {vCCCC .. vNNNN}
385 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]386
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]387 // 76 INVOKE_DIRECT_RANGE {vCCCC .. vNNNN}
388 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]389
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]390 // 77 INVOKE_STATIC_RANGE {vCCCC .. vNNNN}
391 DF_FORMAT_3RC | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]392
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]393 // 78 INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN}
394 DF_FORMAT_3RC | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]395
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]396 // 79 UNUSED_79
397 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]398
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]399 // 7A UNUSED_7A
400 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]401
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]402 // 7B NEG_INT vA, vB
403 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]404
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]405 // 7C NOT_INT vA, vB
406 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]407
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]408 // 7D NEG_LONG vA, vB
409 DF_DA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]410
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]411 // 7E NOT_LONG vA, vB
412 DF_DA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]413
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]414 // 7F NEG_FLOAT vA, vB
415 DF_DA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]416
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]417 // 80 NEG_DOUBLE vA, vB
418 DF_DA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]419
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]420 // 81 INT_TO_LONG vA, vB
421 DF_DA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]422
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]423 // 82 INT_TO_FLOAT vA, vB
424 DF_DA | DF_UB | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]425
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]426 // 83 INT_TO_DOUBLE vA, vB
427 DF_DA_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]428
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]429 // 84 LONG_TO_INT vA, vB
430 DF_DA | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]431
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]432 // 85 LONG_TO_FLOAT vA, vB
433 DF_DA | DF_UB_WIDE | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]434
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]435 // 86 LONG_TO_DOUBLE vA, vB
436 DF_DA_WIDE | DF_UB_WIDE | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]437
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]438 // 87 FLOAT_TO_INT vA, vB
439 DF_DA | DF_UB | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]440
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]441 // 88 FLOAT_TO_LONG vA, vB
442 DF_DA_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]443
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]444 // 89 FLOAT_TO_DOUBLE vA, vB
445 DF_DA_WIDE | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]446
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]447 // 8A DOUBLE_TO_INT vA, vB
448 DF_DA | DF_UB_WIDE | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]449
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]450 // 8B DOUBLE_TO_LONG vA, vB
451 DF_DA_WIDE | DF_UB_WIDE | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]452
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]453 // 8C DOUBLE_TO_FLOAT vA, vB
454 DF_DA | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]455
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]456 // 8D INT_TO_BYTE vA, vB
457 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]458
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]459 // 8E INT_TO_CHAR vA, vB
460 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]461
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]462 // 8F INT_TO_SHORT vA, vB
463 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]464
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]465 // 90 ADD_INT vAA, vBB, vCC
466 DF_DA | DF_UB | DF_UC | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]467
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]468 // 91 SUB_INT vAA, vBB, vCC
469 DF_DA | DF_UB | DF_UC | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]470
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]471 // 92 MUL_INT vAA, vBB, vCC
472 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]473
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]474 // 93 DIV_INT vAA, vBB, vCC
475 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]476
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]477 // 94 REM_INT vAA, vBB, vCC
478 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]479
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]480 // 95 AND_INT vAA, vBB, vCC
481 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]482
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]483 // 96 OR_INT vAA, vBB, vCC
484 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]485
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]486 // 97 XOR_INT vAA, vBB, vCC
487 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]488
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]489 // 98 SHL_INT vAA, vBB, vCC
490 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]491
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]492 // 99 SHR_INT vAA, vBB, vCC
493 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]494
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]495 // 9A USHR_INT vAA, vBB, vCC
496 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]497
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]498 // 9B ADD_LONG vAA, vBB, vCC
499 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]500
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]501 // 9C SUB_LONG vAA, vBB, vCC
502 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]503
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]504 // 9D MUL_LONG vAA, vBB, vCC
505 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]506
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]507 // 9E DIV_LONG vAA, vBB, vCC
508 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]509
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]510 // 9F REM_LONG vAA, vBB, vCC
511 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]512
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]513 // A0 AND_LONG vAA, vBB, vCC
514 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]515
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]516 // A1 OR_LONG vAA, vBB, vCC
517 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]518
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]519 // A2 XOR_LONG vAA, vBB, vCC
520 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]521
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]522 // A3 SHL_LONG vAA, vBB, vCC
523 DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]524
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]525 // A4 SHR_LONG vAA, vBB, vCC
526 DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]527
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]528 // A5 USHR_LONG vAA, vBB, vCC
529 DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]530
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]531 // A6 ADD_FLOAT vAA, vBB, vCC
532 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]533
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]534 // A7 SUB_FLOAT vAA, vBB, vCC
535 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]536
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]537 // A8 MUL_FLOAT vAA, vBB, vCC
538 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]539
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]540 // A9 DIV_FLOAT vAA, vBB, vCC
541 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]542
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]543 // AA REM_FLOAT vAA, vBB, vCC
544 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]545
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]546 // AB ADD_DOUBLE vAA, vBB, vCC
547 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]548
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]549 // AC SUB_DOUBLE vAA, vBB, vCC
550 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]551
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]552 // AD MUL_DOUBLE vAA, vBB, vCC
553 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]554
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]555 // AE DIV_DOUBLE vAA, vBB, vCC
556 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]557
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]558 // AF REM_DOUBLE vAA, vBB, vCC
559 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]560
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]561 // B0 ADD_INT_2ADDR vA, vB
562 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]563
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]564 // B1 SUB_INT_2ADDR vA, vB
565 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]566
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]567 // B2 MUL_INT_2ADDR vA, vB
568 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]569
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]570 // B3 DIV_INT_2ADDR vA, vB
571 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]572
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]573 // B4 REM_INT_2ADDR vA, vB
574 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]575
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]576 // B5 AND_INT_2ADDR vA, vB
577 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]578
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]579 // B6 OR_INT_2ADDR vA, vB
580 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]581
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]582 // B7 XOR_INT_2ADDR vA, vB
583 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]584
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]585 // B8 SHL_INT_2ADDR vA, vB
586 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]587
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]588 // B9 SHR_INT_2ADDR vA, vB
589 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]590
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]591 // BA USHR_INT_2ADDR vA, vB
592 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]593
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]594 // BB ADD_LONG_2ADDR vA, vB
595 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]596
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]597 // BC SUB_LONG_2ADDR vA, vB
598 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]599
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]600 // BD MUL_LONG_2ADDR vA, vB
601 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]602
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]603 // BE DIV_LONG_2ADDR vA, vB
604 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]605
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]606 // BF REM_LONG_2ADDR vA, vB
607 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]608
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]609 // C0 AND_LONG_2ADDR vA, vB
610 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]611
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]612 // C1 OR_LONG_2ADDR vA, vB
613 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]614
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]615 // C2 XOR_LONG_2ADDR vA, vB
616 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]617
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]618 // C3 SHL_LONG_2ADDR vA, vB
619 DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]620
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]621 // C4 SHR_LONG_2ADDR vA, vB
622 DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]623
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]624 // C5 USHR_LONG_2ADDR vA, vB
625 DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]626
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]627 // C6 ADD_FLOAT_2ADDR vA, vB
628 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]629
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]630 // C7 SUB_FLOAT_2ADDR vA, vB
631 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]632
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]633 // C8 MUL_FLOAT_2ADDR vA, vB
634 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]635
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]636 // C9 DIV_FLOAT_2ADDR vA, vB
637 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]638
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]639 // CA REM_FLOAT_2ADDR vA, vB
640 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]641
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]642 // CB ADD_DOUBLE_2ADDR vA, vB
643 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]644
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]645 // CC SUB_DOUBLE_2ADDR vA, vB
646 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]647
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]648 // CD MUL_DOUBLE_2ADDR vA, vB
649 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]650
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]651 // CE DIV_DOUBLE_2ADDR vA, vB
652 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]653
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]654 // CF REM_DOUBLE_2ADDR vA, vB
655 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]656
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]657 // D0 ADD_INT_LIT16 vA, vB, #+CCCC
658 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]659
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]660 // D1 RSUB_INT vA, vB, #+CCCC
661 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]662
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]663 // D2 MUL_INT_LIT16 vA, vB, #+CCCC
664 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]665
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]666 // D3 DIV_INT_LIT16 vA, vB, #+CCCC
667 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]668
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]669 // D4 REM_INT_LIT16 vA, vB, #+CCCC
670 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]671
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]672 // D5 AND_INT_LIT16 vA, vB, #+CCCC
673 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]674
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]675 // D6 OR_INT_LIT16 vA, vB, #+CCCC
676 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]677
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]678 // D7 XOR_INT_LIT16 vA, vB, #+CCCC
679 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]680
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]681 // D8 ADD_INT_LIT8 vAA, vBB, #+CC
682 DF_DA | DF_UB | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]683
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]684 // D9 RSUB_INT_LIT8 vAA, vBB, #+CC
685 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]686
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]687 // DA MUL_INT_LIT8 vAA, vBB, #+CC
688 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]689
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]690 // DB DIV_INT_LIT8 vAA, vBB, #+CC
691 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]692
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]693 // DC REM_INT_LIT8 vAA, vBB, #+CC
694 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]695
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]696 // DD AND_INT_LIT8 vAA, vBB, #+CC
697 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]698
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]699 // DE OR_INT_LIT8 vAA, vBB, #+CC
700 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]701
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]702 // DF XOR_INT_LIT8 vAA, vBB, #+CC
703 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]704
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]705 // E0 SHL_INT_LIT8 vAA, vBB, #+CC
706 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]707
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]708 // E1 SHR_INT_LIT8 vAA, vBB, #+CC
709 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]710
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]711 // E2 USHR_INT_LIT8 vAA, vBB, #+CC
712 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]713
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]714 // E3 IGET_VOLATILE
715 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]716
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]717 // E4 IPUT_VOLATILE
718 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]719
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]720 // E5 SGET_VOLATILE
721 DF_DA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]722
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]723 // E6 SPUT_VOLATILE
724 DF_UA | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]725
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]726 // E7 IGET_OBJECT_VOLATILE
727 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]728
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]729 // E8 IGET_WIDE_VOLATILE
730 DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]731
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]732 // E9 IPUT_WIDE_VOLATILE
733 DF_UA_WIDE | DF_UB | DF_NULL_CHK_2 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]734
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]735 // EA SGET_WIDE_VOLATILE
736 DF_DA_WIDE | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]737
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]738 // EB SPUT_WIDE_VOLATILE
739 DF_UA_WIDE | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]740
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]741 // EC BREAKPOINT
742 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]743
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]744 // ED THROW_VERIFICATION_ERROR
745 DF_NOP | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]746
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]747 // EE EXECUTE_INLINE
748 DF_FORMAT_35C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]749
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]750 // EF EXECUTE_INLINE_RANGE
751 DF_FORMAT_3RC,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]752
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]753 // F0 INVOKE_OBJECT_INIT_RANGE
754 DF_NOP | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]755
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]756 // F1 RETURN_VOID_BARRIER
757 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]758
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]759 // F2 IGET_QUICK
760 DF_DA | DF_UB | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]761
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]762 // F3 IGET_WIDE_QUICK
763 DF_DA_WIDE | DF_UB | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]764
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]765 // F4 IGET_OBJECT_QUICK
766 DF_DA | DF_UB | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]767
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]768 // F5 IPUT_QUICK
769 DF_UA | DF_UB | DF_NULL_CHK_1,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]770
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]771 // F6 IPUT_WIDE_QUICK
772 DF_UA_WIDE | DF_UB | DF_NULL_CHK_2,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]773
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]774 // F7 IPUT_OBJECT_QUICK
775 DF_UA | DF_UB | DF_NULL_CHK_1,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]776
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]777 // F8 INVOKE_VIRTUAL_QUICK
778 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]779
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]780 // F9 INVOKE_VIRTUAL_QUICK_RANGE
781 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]782
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]783 // FA INVOKE_SUPER_QUICK
784 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]785
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]786 // FB INVOKE_SUPER_QUICK_RANGE
787 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]788
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]789 // FC IPUT_OBJECT_VOLATILE
790 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]791
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]792 // FD SGET_OBJECT_VOLATILE
793 DF_DA | DF_CORE_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]794
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]795 // FE SPUT_OBJECT_VOLATILE
796 DF_UA | DF_CORE_A | DF_UMS,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]797
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]798 // FF UNUSED_FF
799 DF_NOP,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]800
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]801 // Beginning of extended MIR opcodes
802 // 100 MIR_PHI
803 DF_PHI | DF_DA | DF_NULL_TRANSFER_N,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]804
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]805 // 101 MIR_COPY
806 DF_DA | DF_UB | DF_IS_MOVE,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]807
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]808 // 102 MIR_FUSED_CMPL_FLOAT
809 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]810
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]811 // 103 MIR_FUSED_CMPG_FLOAT
812 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]813
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]814 // 104 MIR_FUSED_CMPL_DOUBLE
815 DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]816
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]817 // 105 MIR_FUSED_CMPG_DOUBLE
818 DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]819
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]820 // 106 MIR_FUSED_CMP_LONG
821 DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]822
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]823 // 107 MIR_NOP
824 DF_NOP,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]825
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]826 // 108 MIR_NULL_RANGE_UP_CHECK
827 0,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]828
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]829 // 109 MIR_NULL_RANGE_DOWN_CHECK
830 0,
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]831
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]832 // 110 MIR_LOWER_BOUND
833 0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]834};
835
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]836/* Return the base virtual register for a SSA name */
837int SRegToVReg(const CompilationUnit* cUnit, int ssaReg)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]838{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]839 DCHECK_LT(ssaReg, (int)cUnit->ssaBaseVRegs->numUsed);
840 return GET_ELEM_N(cUnit->ssaBaseVRegs, int, ssaReg);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]841}
842
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]843int SRegToSubscript(const CompilationUnit* cUnit, int ssaReg)
844{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]845 DCHECK(ssaReg < (int)cUnit->ssaSubscripts->numUsed);
846 return GET_ELEM_N(cUnit->ssaSubscripts, int, ssaReg);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]847}
848
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]849int getSSAUseCount(CompilationUnit* cUnit, int sReg)
850{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]851 DCHECK(sReg < (int)cUnit->rawUseCounts.numUsed);
852 return cUnit->rawUseCounts.elemList[sReg];
buzbee84fd6932012-03-29 16:44:16 -0700[diff] [blame]853}
854
855
buzbeeba938cb2012-02-03 14:47:55 -0800[diff] [blame]856char* oatGetDalvikDisassembly(CompilationUnit* cUnit,
Elliott Hughesadb8c672012-03-06 16:49:32 -0800[diff] [blame]857 const DecodedInstruction& insn, const char* note)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]858{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]859 char buffer[256];
860 Instruction::Code opcode = insn.opcode;
861 int dfAttributes = oatDataFlowAttributes[opcode];
862 int flags;
863 char* ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]864
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]865 buffer[0] = 0;
866 if ((int)opcode >= (int)kMirOpFirst) {
867 if ((int)opcode == (int)kMirOpPhi) {
868 strcpy(buffer, "PHI");
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]869 } else {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]870 sprintf(buffer, "Opcode %#x", opcode);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]871 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]872 flags = 0;
873 } else {
874 strcpy(buffer, Instruction::Name(opcode));
875 flags = Instruction::Flags(opcode);
876 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]877
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]878 if (note)
879 strcat(buffer, note);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]880
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]881 /* For branches, decode the instructions to print out the branch targets */
882 if (flags & Instruction::kBranch) {
883 Instruction::Format dalvikFormat = Instruction::FormatOf(insn.opcode);
884 int offset = 0;
885 switch (dalvikFormat) {
886 case Instruction::k21t:
887 snprintf(buffer + strlen(buffer), 256, " v%d,", insn.vA);
888 offset = (int) insn.vB;
889 break;
890 case Instruction::k22t:
891 snprintf(buffer + strlen(buffer), 256, " v%d, v%d,", insn.vA, insn.vB);
892 offset = (int) insn.vC;
893 break;
894 case Instruction::k10t:
895 case Instruction::k20t:
896 case Instruction::k30t:
897 offset = (int) insn.vA;
898 break;
899 default:
900 LOG(FATAL) << "Unexpected branch format " << (int)dalvikFormat
901 << " / opcode " << (int)opcode;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]902 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]903 snprintf(buffer + strlen(buffer), 256, " (%c%x)",
904 offset > 0 ? '+' : '-',
905 offset > 0 ? offset : -offset);
906 } else if (dfAttributes & DF_FORMAT_35C) {
907 unsigned int i;
908 for (i = 0; i < insn.vA; i++) {
909 if (i != 0) strcat(buffer, ",");
910 snprintf(buffer + strlen(buffer), 256, " v%d", insn.arg[i]);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]911 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]912 }
913 else if (dfAttributes & DF_FORMAT_3RC) {
914 snprintf(buffer + strlen(buffer), 256,
915 " v%d..v%d", insn.vC, insn.vC + insn.vA - 1);
916 } else {
917 if (dfAttributes & DF_A_IS_REG) {
918 snprintf(buffer + strlen(buffer), 256, " v%d", insn.vA);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]919 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]920 if (dfAttributes & DF_B_IS_REG) {
921 snprintf(buffer + strlen(buffer), 256, ", v%d", insn.vB);
922 } else if ((int)opcode < (int)kMirOpFirst) {
923 snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn.vB);
924 }
925 if (dfAttributes & DF_C_IS_REG) {
926 snprintf(buffer + strlen(buffer), 256, ", v%d", insn.vC);
927 } else if ((int)opcode < (int)kMirOpFirst) {
928 snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn.vC);
929 }
930 }
931 int length = strlen(buffer) + 1;
932 ret = (char*)oatNew(cUnit, length, false, kAllocDFInfo);
933 memcpy(ret, buffer, length);
934 return ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]935}
936
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]937char* getSSAName(const CompilationUnit* cUnit, int ssaReg, char* name)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]938{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]939 sprintf(name, "v%d_%d", SRegToVReg(cUnit, ssaReg),
940 SRegToSubscript(cUnit, ssaReg));
941 return name;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]942}
943
944/*
945 * Dalvik instruction disassembler with optional SSA printing.
946 */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]947char* oatFullDisassembler(CompilationUnit* cUnit, const MIR* mir)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]948{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]949 char buffer[256];
950 char operand0[32], operand1[32];
951 const DecodedInstruction* insn = &mir->dalvikInsn;
952 Instruction::Code opcode = insn->opcode;
953 int dfAttributes = oatDataFlowAttributes[opcode];
954 char* ret;
955 int length;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]956
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]957 buffer[0] = 0;
958 if (static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst)) {
959 if (static_cast<int>(opcode) == static_cast<int>(kMirOpPhi)) {
960 snprintf(buffer, 256, "PHI %s = (%s",
961 getSSAName(cUnit, mir->ssaRep->defs[0], operand0),
962 getSSAName(cUnit, mir->ssaRep->uses[0], operand1));
963 int i;
964 for (i = 1; i < mir->ssaRep->numUses; i++) {
965 snprintf(buffer + strlen(buffer), 256, ", %s",
966 getSSAName(cUnit, mir->ssaRep->uses[i], operand0));
967 }
968 snprintf(buffer + strlen(buffer), 256, ")");
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]969 } else {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]970 sprintf(buffer, "Opcode %#x", opcode);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]971 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]972 goto done;
973 } else {
974 strcpy(buffer, Instruction::Name(opcode));
975 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]976
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]977 /* For branches, decode the instructions to print out the branch targets */
978 if (Instruction::Flags(insn->opcode) & Instruction::kBranch) {
979 Instruction::Format dalvikFormat = Instruction::FormatOf(insn->opcode);
980 int delta = 0;
981 switch (dalvikFormat) {
982 case Instruction::k21t:
983 snprintf(buffer + strlen(buffer), 256, " %s, ",
984 getSSAName(cUnit, mir->ssaRep->uses[0], operand0));
985 delta = (int) insn->vB;
986 break;
987 case Instruction::k22t:
988 snprintf(buffer + strlen(buffer), 256, " %s, %s, ",
989 getSSAName(cUnit, mir->ssaRep->uses[0], operand0),
990 getSSAName(cUnit, mir->ssaRep->uses[1], operand1));
991 delta = (int) insn->vC;
992 break;
993 case Instruction::k10t:
994 case Instruction::k20t:
995 case Instruction::k30t:
996 delta = (int) insn->vA;
997 break;
998 default:
999 LOG(FATAL) << "Unexpected branch format: " << (int)dalvikFormat;
1000 }
1001 snprintf(buffer + strlen(buffer), 256, " %04x",
1002 mir->offset + delta);
1003 } else if (dfAttributes & (DF_FORMAT_35C | DF_FORMAT_3RC)) {
1004 unsigned int i;
1005 for (i = 0; i < insn->vA; i++) {
1006 if (i != 0) strcat(buffer, ",");
1007 snprintf(buffer + strlen(buffer), 256, " %s",
1008 getSSAName(cUnit, mir->ssaRep->uses[i], operand0));
1009 }
1010 } else {
1011 int udIdx;
1012 if (mir->ssaRep->numDefs) {
1013
1014 for (udIdx = 0; udIdx < mir->ssaRep->numDefs; udIdx++) {
1015 snprintf(buffer + strlen(buffer), 256, " %s",
1016 getSSAName(cUnit, mir->ssaRep->defs[udIdx], operand0));
1017 }
1018 strcat(buffer, ",");
1019 }
1020 if (mir->ssaRep->numUses) {
1021 /* No leading ',' for the first use */
1022 snprintf(buffer + strlen(buffer), 256, " %s",
1023 getSSAName(cUnit, mir->ssaRep->uses[0], operand0));
1024 for (udIdx = 1; udIdx < mir->ssaRep->numUses; udIdx++) {
1025 snprintf(buffer + strlen(buffer), 256, ", %s",
1026 getSSAName(cUnit, mir->ssaRep->uses[udIdx], operand0));
1027 }
1028 }
1029 if (static_cast<int>(opcode) < static_cast<int>(kMirOpFirst)) {
1030 Instruction::Format dalvikFormat = Instruction::FormatOf(opcode);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1031 switch (dalvikFormat) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1032 case Instruction::k11n: // op vA, #+B
1033 case Instruction::k21s: // op vAA, #+BBBB
1034 case Instruction::k21h: // op vAA, #+BBBB00000[00000000]
1035 case Instruction::k31i: // op vAA, #+BBBBBBBB
1036 case Instruction::k51l: // op vAA, #+BBBBBBBBBBBBBBBB
1037 snprintf(buffer + strlen(buffer), 256, " #%#x", insn->vB);
1038 break;
1039 case Instruction::k21c: // op vAA, thing@BBBB
1040 case Instruction::k31c: // op vAA, thing@BBBBBBBB
1041 snprintf(buffer + strlen(buffer), 256, " @%#x", insn->vB);
1042 break;
1043 case Instruction::k22b: // op vAA, vBB, #+CC
1044 case Instruction::k22s: // op vA, vB, #+CCCC
1045 snprintf(buffer + strlen(buffer), 256, " #%#x", insn->vC);
1046 break;
1047 case Instruction::k22c: // op vA, vB, thing@CCCC
1048 snprintf(buffer + strlen(buffer), 256, " @%#x", insn->vC);
1049 break;
1050 /* No need for special printing */
1051 default:
1052 break;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1053 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1054 }
1055 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1056
1057done:
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1058 length = strlen(buffer) + 1;
1059 ret = (char*) oatNew(cUnit, length, false, kAllocDFInfo);
1060 memcpy(ret, buffer, length);
1061 return ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1062}
1063
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]1064char* oatGetSSAString(CompilationUnit* cUnit, SSARepresentation* ssaRep)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1065{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1066 char buffer[256];
1067 char* ret;
1068 int i;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1069
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1070 buffer[0] = 0;
1071 for (i = 0; i < ssaRep->numDefs; i++) {
1072 int ssaReg = ssaRep->defs[i];
1073 sprintf(buffer + strlen(buffer), "s%d(v%d_%d) ", ssaReg,
1074 SRegToVReg(cUnit, ssaReg), SRegToSubscript(cUnit, ssaReg));
1075 }
1076
1077 if (ssaRep->numDefs) {
1078 strcat(buffer, "<- ");
1079 }
1080
1081 for (i = 0; i < ssaRep->numUses; i++) {
1082 int len = strlen(buffer);
1083 int ssaReg = ssaRep->uses[i];
1084
1085 if (snprintf(buffer + len, 250 - len, "s%d(v%d_%d) ", ssaReg,
1086 SRegToVReg(cUnit, ssaReg),
1087 SRegToSubscript(cUnit, ssaReg))) {
1088 strcat(buffer, "...");
1089 break;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1090 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1091 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1092
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1093 int length = strlen(buffer) + 1;
1094 ret = (char*)oatNew(cUnit, length, false, kAllocDFInfo);
1095 memcpy(ret, buffer, length);
1096 return ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1097}
1098
1099/* Any register that is used before being defined is considered live-in */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1100inline void handleLiveInUse(CompilationUnit* cUnit, ArenaBitVector* useV,
1101 ArenaBitVector* defV, ArenaBitVector* liveInV,
1102 int dalvikRegId)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1103{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1104 oatSetBit(cUnit, useV, dalvikRegId);
1105 if (!oatIsBitSet(defV, dalvikRegId)) {
1106 oatSetBit(cUnit, liveInV, dalvikRegId);
1107 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1108}
1109
1110/* Mark a reg as being defined */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1111inline void handleDef(CompilationUnit* cUnit, ArenaBitVector* defV,
1112 int dalvikRegId)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1113{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1114 oatSetBit(cUnit, defV, dalvikRegId);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1115}
1116
1117/*
1118 * Find out live-in variables for natural loops. Variables that are live-in in
1119 * the main loop body are considered to be defined in the entry block.
1120 */
1121bool oatFindLocalLiveIn(CompilationUnit* cUnit, BasicBlock* bb)
1122{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1123 MIR* mir;
1124 ArenaBitVector *useV, *defV, *liveInV;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1125
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1126 if (bb->dataFlowInfo == NULL) return false;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1127
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1128 useV = bb->dataFlowInfo->useV =
1129 oatAllocBitVector(cUnit, cUnit->numDalvikRegisters, false, kBitMapUse);
1130 defV = bb->dataFlowInfo->defV =
1131 oatAllocBitVector(cUnit, cUnit->numDalvikRegisters, false, kBitMapDef);
1132 liveInV = bb->dataFlowInfo->liveInV =
1133 oatAllocBitVector(cUnit, cUnit->numDalvikRegisters, false,
1134 kBitMapLiveIn);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1135
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1136 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1137 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
1138 DecodedInstruction *dInsn = &mir->dalvikInsn;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1139
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1140 if (dfAttributes & DF_HAS_USES) {
1141 if (dfAttributes & DF_UA) {
1142 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA);
1143 } else if (dfAttributes & DF_UA_WIDE) {
1144 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA);
1145 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA+1);
1146 }
1147 if (dfAttributes & DF_UB) {
1148 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB);
1149 } else if (dfAttributes & DF_UB_WIDE) {
1150 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB);
1151 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB+1);
1152 }
1153 if (dfAttributes & DF_UC) {
1154 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC);
1155 } else if (dfAttributes & DF_UC_WIDE) {
1156 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC);
1157 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC+1);
1158 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1159 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1160 if (dfAttributes & DF_FORMAT_35C) {
1161 for (unsigned int i = 0; i < dInsn->vA; i++) {
1162 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->arg[i]);
1163 }
1164 }
1165 if (dfAttributes & DF_FORMAT_3RC) {
1166 for (unsigned int i = 0; i < dInsn->vA; i++) {
1167 handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC+i);
1168 }
1169 }
1170 if (dfAttributes & DF_HAS_DEFS) {
1171 handleDef(cUnit, defV, dInsn->vA);
1172 if (dfAttributes & DF_DA_WIDE) {
1173 handleDef(cUnit, defV, dInsn->vA+1);
1174 }
1175 }
1176 }
1177 return true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1178}
1179
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1180int addNewSReg(CompilationUnit* cUnit, int vReg)
1181{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1182 // Compiler temps always have a subscript of 0
1183 int subscript = (vReg < 0) ? 0 : ++cUnit->SSALastDefs[vReg];
1184 int ssaReg = cUnit->numSSARegs++;
1185 oatInsertGrowableList(cUnit, cUnit->ssaBaseVRegs, vReg);
1186 oatInsertGrowableList(cUnit, cUnit->ssaSubscripts, subscript);
1187 DCHECK_EQ(cUnit->ssaBaseVRegs->numUsed, cUnit->ssaSubscripts->numUsed);
1188 return ssaReg;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1189}
1190
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1191/* Find out the latest SSA register for a given Dalvik register */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1192void handleSSAUse(CompilationUnit* cUnit, int* uses, int dalvikReg,
1193 int regIndex)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1194{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1195 DCHECK((dalvikReg >= 0) && (dalvikReg < cUnit->numDalvikRegisters));
1196 uses[regIndex] = cUnit->vRegToSSAMap[dalvikReg];
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1197}
1198
1199/* Setup a new SSA register for a given Dalvik register */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1200void handleSSADef(CompilationUnit* cUnit, int* defs, int dalvikReg,
1201 int regIndex)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1202{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1203 DCHECK((dalvikReg >= 0) && (dalvikReg < cUnit->numDalvikRegisters));
1204 int ssaReg = addNewSReg(cUnit, dalvikReg);
1205 cUnit->vRegToSSAMap[dalvikReg] = ssaReg;
1206 defs[regIndex] = ssaReg;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1207}
1208
buzbeeec5adf32011-09-11 15:25:43 -0700[diff] [blame]1209/* Look up new SSA names for format_35c instructions */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1210void dataFlowSSAFormat35C(CompilationUnit* cUnit, MIR* mir)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1211{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1212 DecodedInstruction *dInsn = &mir->dalvikInsn;
1213 int numUses = dInsn->vA;
1214 int i;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1215
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1216 mir->ssaRep->numUses = numUses;
1217 mir->ssaRep->uses = (int *)oatNew(cUnit, sizeof(int) * numUses, true,
1218 kAllocDFInfo);
1219 // NOTE: will be filled in during type & size inference pass
1220 mir->ssaRep->fpUse = (bool *)oatNew(cUnit, sizeof(bool) * numUses, true,
buzbee5abfa3e2012-01-31 17:01:43 -0800[diff] [blame]1221 kAllocDFInfo);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1222
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1223 for (i = 0; i < numUses; i++) {
1224 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->arg[i], i);
1225 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1226}
1227
buzbeeec5adf32011-09-11 15:25:43 -0700[diff] [blame]1228/* Look up new SSA names for format_3rc instructions */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1229void dataFlowSSAFormat3RC(CompilationUnit* cUnit, MIR* mir)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1230{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1231 DecodedInstruction *dInsn = &mir->dalvikInsn;
1232 int numUses = dInsn->vA;
1233 int i;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1234
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1235 mir->ssaRep->numUses = numUses;
1236 mir->ssaRep->uses = (int *)oatNew(cUnit, sizeof(int) * numUses, true,
1237 kAllocDFInfo);
1238 // NOTE: will be filled in during type & size inference pass
1239 mir->ssaRep->fpUse = (bool *)oatNew(cUnit, sizeof(bool) * numUses, true,
buzbee5abfa3e2012-01-31 17:01:43 -0800[diff] [blame]1240 kAllocDFInfo);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1241
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1242 for (i = 0; i < numUses; i++) {
1243 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+i, i);
1244 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1245}
1246
1247/* Entry function to convert a block into SSA representation */
1248bool oatDoSSAConversion(CompilationUnit* cUnit, BasicBlock* bb)
1249{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1250 MIR* mir;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1251
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1252 if (bb->dataFlowInfo == NULL) return false;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1253
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1254 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1255 mir->ssaRep = (struct SSARepresentation *)
1256 oatNew(cUnit, sizeof(SSARepresentation), true, kAllocDFInfo);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1257
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1258 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1259
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1260 // If not a pseudo-op, note non-leaf or can throw
1261 if (static_cast<int>(mir->dalvikInsn.opcode) <
1262 static_cast<int>(kNumPackedOpcodes)) {
1263 int flags = Instruction::Flags(mir->dalvikInsn.opcode);
buzbeecefd1872011-09-09 09:59:52 -0700[diff] [blame]1264
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1265 if (flags & Instruction::kThrow) {
1266 cUnit->attrs &= ~METHOD_IS_THROW_FREE;
1267 }
buzbeecefd1872011-09-09 09:59:52 -0700[diff] [blame]1268
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1269 if (flags & Instruction::kInvoke) {
1270 cUnit->attrs &= ~METHOD_IS_LEAF;
1271 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1272 }
1273
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1274 int numUses = 0;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1275
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1276 if (dfAttributes & DF_FORMAT_35C) {
1277 dataFlowSSAFormat35C(cUnit, mir);
1278 continue;
buzbee5abfa3e2012-01-31 17:01:43 -0800[diff] [blame]1279 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1280
1281 if (dfAttributes & DF_FORMAT_3RC) {
1282 dataFlowSSAFormat3RC(cUnit, mir);
1283 continue;
1284 }
1285
1286 if (dfAttributes & DF_HAS_USES) {
1287 if (dfAttributes & DF_UA) {
1288 numUses++;
1289 } else if (dfAttributes & DF_UA_WIDE) {
1290 numUses += 2;
1291 }
1292 if (dfAttributes & DF_UB) {
1293 numUses++;
1294 } else if (dfAttributes & DF_UB_WIDE) {
1295 numUses += 2;
1296 }
1297 if (dfAttributes & DF_UC) {
1298 numUses++;
1299 } else if (dfAttributes & DF_UC_WIDE) {
1300 numUses += 2;
1301 }
1302 }
1303
1304 if (numUses) {
1305 mir->ssaRep->numUses = numUses;
1306 mir->ssaRep->uses = (int *)oatNew(cUnit, sizeof(int) * numUses,
1307 false, kAllocDFInfo);
1308 mir->ssaRep->fpUse = (bool *)oatNew(cUnit, sizeof(bool) * numUses,
1309 false, kAllocDFInfo);
1310 }
1311
1312 int numDefs = 0;
1313
1314 if (dfAttributes & DF_HAS_DEFS) {
1315 numDefs++;
1316 if (dfAttributes & DF_DA_WIDE) {
1317 numDefs++;
1318 }
1319 }
1320
1321 if (numDefs) {
1322 mir->ssaRep->numDefs = numDefs;
1323 mir->ssaRep->defs = (int *)oatNew(cUnit, sizeof(int) * numDefs,
1324 false, kAllocDFInfo);
1325 mir->ssaRep->fpDef = (bool *)oatNew(cUnit, sizeof(bool) * numDefs,
1326 false, kAllocDFInfo);
1327 }
1328
1329 DecodedInstruction *dInsn = &mir->dalvikInsn;
1330
1331 if (dfAttributes & DF_HAS_USES) {
1332 numUses = 0;
1333 if (dfAttributes & DF_UA) {
1334 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
1335 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA, numUses++);
1336 } else if (dfAttributes & DF_UA_WIDE) {
1337 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
1338 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA, numUses++);
1339 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
1340 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA+1, numUses++);
1341 }
1342 if (dfAttributes & DF_UB) {
1343 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
1344 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB, numUses++);
1345 } else if (dfAttributes & DF_UB_WIDE) {
1346 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
1347 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB, numUses++);
1348 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
1349 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB+1, numUses++);
1350 }
1351 if (dfAttributes & DF_UC) {
1352 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
1353 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC, numUses++);
1354 } else if (dfAttributes & DF_UC_WIDE) {
1355 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
1356 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC, numUses++);
1357 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
1358 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+1, numUses++);
1359 }
1360 }
1361 if (dfAttributes & DF_HAS_DEFS) {
1362 mir->ssaRep->fpDef[0] = dfAttributes & DF_FP_A;
1363 handleSSADef(cUnit, mir->ssaRep->defs, dInsn->vA, 0);
1364 if (dfAttributes & DF_DA_WIDE) {
1365 mir->ssaRep->fpDef[1] = dfAttributes & DF_FP_A;
1366 handleSSADef(cUnit, mir->ssaRep->defs, dInsn->vA+1, 1);
1367 }
1368 }
1369 }
1370
1371 if (!cUnit->disableDataflow) {
1372 /*
1373 * Take a snapshot of Dalvik->SSA mapping at the end of each block. The
1374 * input to PHI nodes can be derived from the snapshot of all
1375 * predecessor blocks.
1376 */
1377 bb->dataFlowInfo->vRegToSSAMap =
1378 (int *)oatNew(cUnit, sizeof(int) * cUnit->numDalvikRegisters, false,
1379 kAllocDFInfo);
1380
1381 memcpy(bb->dataFlowInfo->vRegToSSAMap, cUnit->vRegToSSAMap,
1382 sizeof(int) * cUnit->numDalvikRegisters);
1383 }
1384 return true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1385}
1386
1387/* Setup a constant value for opcodes thare have the DF_SETS_CONST attribute */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1388void setConstant(CompilationUnit* cUnit, int ssaReg, int value)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1389{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1390 oatSetBit(cUnit, cUnit->isConstantV, ssaReg);
1391 cUnit->constantValues[ssaReg] = value;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1392}
1393
1394bool oatDoConstantPropagation(CompilationUnit* cUnit, BasicBlock* bb)
1395{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1396 MIR* mir;
1397 ArenaBitVector *isConstantV = cUnit->isConstantV;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1398
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1399 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1400 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1401
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1402 DecodedInstruction *dInsn = &mir->dalvikInsn;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1403
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1404 if (!(dfAttributes & DF_HAS_DEFS)) continue;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1405
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1406 /* Handle instructions that set up constants directly */
1407 if (dfAttributes & DF_SETS_CONST) {
1408 if (dfAttributes & DF_DA) {
1409 switch (dInsn->opcode) {
1410 case Instruction::CONST_4:
1411 case Instruction::CONST_16:
1412 case Instruction::CONST:
1413 setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
1414 break;
1415 case Instruction::CONST_HIGH16:
1416 setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB << 16);
1417 break;
1418 default:
1419 break;
1420 }
1421 } else if (dfAttributes & DF_DA_WIDE) {
1422 switch (dInsn->opcode) {
1423 case Instruction::CONST_WIDE_16:
1424 case Instruction::CONST_WIDE_32:
1425 setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
1426 setConstant(cUnit, mir->ssaRep->defs[1], 0);
1427 break;
1428 case Instruction::CONST_WIDE:
1429 setConstant(cUnit, mir->ssaRep->defs[0], (int) dInsn->vB_wide);
1430 setConstant(cUnit, mir->ssaRep->defs[1],
1431 (int) (dInsn->vB_wide >> 32));
1432 break;
1433 case Instruction::CONST_WIDE_HIGH16:
1434 setConstant(cUnit, mir->ssaRep->defs[0], 0);
1435 setConstant(cUnit, mir->ssaRep->defs[1], dInsn->vB << 16);
1436 break;
1437 default:
1438 break;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1439 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1440 }
1441 /* Handle instructions that set up constants directly */
1442 } else if (dfAttributes & DF_IS_MOVE) {
1443 int i;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1444
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1445 for (i = 0; i < mir->ssaRep->numUses; i++) {
1446 if (!oatIsBitSet(isConstantV, mir->ssaRep->uses[i])) break;
1447 }
1448 /* Move a register holding a constant to another register */
1449 if (i == mir->ssaRep->numUses) {
1450 setConstant(cUnit, mir->ssaRep->defs[0],
1451 cUnit->constantValues[mir->ssaRep->uses[0]]);
1452 if (dfAttributes & DF_DA_WIDE) {
1453 setConstant(cUnit, mir->ssaRep->defs[1],
1454 cUnit->constantValues[mir->ssaRep->uses[1]]);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1455 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1456 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1457 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1458 }
1459 /* TODO: implement code to handle arithmetic operations */
1460 return true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1461}
1462
1463/* Setup the basic data structures for SSA conversion */
1464void oatInitializeSSAConversion(CompilationUnit* cUnit)
1465{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1466 int i;
1467 int numDalvikReg = cUnit->numDalvikRegisters;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1468
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1469 cUnit->ssaBaseVRegs = (GrowableList *)oatNew(cUnit, sizeof(GrowableList),
1470 false, kAllocDFInfo);
1471 cUnit->ssaSubscripts = (GrowableList *)oatNew(cUnit, sizeof(GrowableList),
1472 false, kAllocDFInfo);
1473 // Create the ssa mappings, estimating the max size
1474 oatInitGrowableList(cUnit, cUnit->ssaBaseVRegs,
1475 numDalvikReg + cUnit->defCount + 128,
1476 kListSSAtoDalvikMap);
1477 oatInitGrowableList(cUnit, cUnit->ssaSubscripts,
1478 numDalvikReg + cUnit->defCount + 128,
1479 kListSSAtoDalvikMap);
1480 /*
1481 * Initial number of SSA registers is equal to the number of Dalvik
1482 * registers.
1483 */
1484 cUnit->numSSARegs = numDalvikReg;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1485
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1486 /*
1487 * Initialize the SSA2Dalvik map list. For the first numDalvikReg elements,
1488 * the subscript is 0 so we use the ENCODE_REG_SUB macro to encode the value
1489 * into "(0 << 16) | i"
1490 */
1491 for (i = 0; i < numDalvikReg; i++) {
1492 oatInsertGrowableList(cUnit, cUnit->ssaBaseVRegs, i);
1493 oatInsertGrowableList(cUnit, cUnit->ssaSubscripts, 0);
1494 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1495
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1496 /*
1497 * Initialize the DalvikToSSAMap map. There is one entry for each
1498 * Dalvik register, and the SSA names for those are the same.
1499 */
1500 cUnit->vRegToSSAMap = (int *)oatNew(cUnit, sizeof(int) * numDalvikReg,
1501 false, kAllocDFInfo);
1502 /* Keep track of the higest def for each dalvik reg */
1503 cUnit->SSALastDefs = (int *)oatNew(cUnit, sizeof(int) * numDalvikReg,
1504 false, kAllocDFInfo);
buzbeef0cde542011-09-13 14:55:02 -0700[diff] [blame]1505
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1506 for (i = 0; i < numDalvikReg; i++) {
1507 cUnit->vRegToSSAMap[i] = i;
1508 cUnit->SSALastDefs[i] = 0;
1509 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1510
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1511 /* Add ssa reg for Method* */
1512 cUnit->methodSReg = addNewSReg(cUnit, SSA_METHOD_BASEREG);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1513
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1514 /*
1515 * Allocate the BasicBlockDataFlow structure for the entry and code blocks
1516 */
1517 GrowableListIterator iterator;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1518
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1519 oatGrowableListIteratorInit(&cUnit->blockList, &iterator);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1520
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1521 while (true) {
1522 BasicBlock* bb = (BasicBlock *) oatGrowableListIteratorNext(&iterator);
1523 if (bb == NULL) break;
1524 if (bb->hidden == true) continue;
1525 if (bb->blockType == kDalvikByteCode ||
1526 bb->blockType == kEntryBlock ||
1527 bb->blockType == kExitBlock) {
1528 bb->dataFlowInfo = (BasicBlockDataFlow *)
1529 oatNew(cUnit, sizeof(BasicBlockDataFlow), true, kAllocDFInfo);
1530 }
1531 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1532}
1533
1534/* Clear the visited flag for each BB */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1535bool oatClearVisitedFlag(struct CompilationUnit* cUnit, struct BasicBlock* bb)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1536{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1537 bb->visited = false;
1538 return true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1539}
1540
1541void oatDataFlowAnalysisDispatcher(CompilationUnit* cUnit,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1542 bool (*func)(CompilationUnit*, BasicBlock*),
1543 DataFlowAnalysisMode dfaMode,
1544 bool isIterative)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1545{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1546 bool change = true;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1547
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1548 while (change) {
1549 change = false;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1550
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1551 switch (dfaMode) {
1552 /* Scan all blocks and perform the operations specified in func */
1553 case kAllNodes:
1554 {
1555 GrowableListIterator iterator;
1556 oatGrowableListIteratorInit(&cUnit->blockList, &iterator);
1557 while (true) {
1558 BasicBlock* bb =
1559 (BasicBlock *) oatGrowableListIteratorNext(&iterator);
1560 if (bb == NULL) break;
1561 if (bb->hidden == true) continue;
1562 change |= (*func)(cUnit, bb);
1563 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1564 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1565 break;
1566 /* Scan reachable blocks and perform the ops specified in func. */
1567 case kReachableNodes:
1568 {
1569 int numReachableBlocks = cUnit->numReachableBlocks;
1570 int idx;
1571 const GrowableList *blockList = &cUnit->blockList;
1572
1573 for (idx = 0; idx < numReachableBlocks; idx++) {
1574 int blockIdx = cUnit->dfsOrder.elemList[idx];
1575 BasicBlock* bb = (BasicBlock *)
1576 oatGrowableListGetElement(blockList, blockIdx);
1577 change |= (*func)(cUnit, bb);
1578 }
1579 }
1580 break;
1581
1582 /* Scan reachable blocks by pre-order dfs and invoke func on each. */
1583 case kPreOrderDFSTraversal:
1584 {
1585 int numReachableBlocks = cUnit->numReachableBlocks;
1586 int idx;
1587 const GrowableList *blockList = &cUnit->blockList;
1588
1589 for (idx = 0; idx < numReachableBlocks; idx++) {
1590 int dfsIdx = cUnit->dfsOrder.elemList[idx];
1591 BasicBlock* bb = (BasicBlock *)
1592 oatGrowableListGetElement(blockList, dfsIdx);
1593 change |= (*func)(cUnit, bb);
1594 }
1595 }
1596 break;
1597 /* Scan reachable blocks post-order dfs and invoke func on each. */
1598 case kPostOrderDFSTraversal:
1599 {
1600 int numReachableBlocks = cUnit->numReachableBlocks;
1601 int idx;
1602 const GrowableList *blockList = &cUnit->blockList;
1603
1604 for (idx = numReachableBlocks - 1; idx >= 0; idx--) {
1605 int dfsIdx = cUnit->dfsOrder.elemList[idx];
1606 BasicBlock* bb = (BasicBlock *)
1607 oatGrowableListGetElement(blockList, dfsIdx);
1608 change |= (*func)(cUnit, bb);
1609 }
1610 }
1611 break;
1612 /* Scan reachable post-order dom tree and invoke func on each. */
1613 case kPostOrderDOMTraversal:
1614 {
1615 int numReachableBlocks = cUnit->numReachableBlocks;
1616 int idx;
1617 const GrowableList *blockList = &cUnit->blockList;
1618
1619 for (idx = 0; idx < numReachableBlocks; idx++) {
1620 int domIdx = cUnit->domPostOrderTraversal.elemList[idx];
1621 BasicBlock* bb = (BasicBlock *)
1622 oatGrowableListGetElement(blockList, domIdx);
1623 change |= (*func)(cUnit, bb);
1624 }
1625 }
1626 break;
1627 /* Scan reachable blocks reverse post-order dfs, invoke func on each */
1628 case kReversePostOrderTraversal:
1629 {
1630 int numReachableBlocks = cUnit->numReachableBlocks;
1631 int idx;
1632 const GrowableList *blockList = &cUnit->blockList;
1633
1634 for (idx = numReachableBlocks - 1; idx >= 0; idx--) {
1635 int revIdx = cUnit->dfsPostOrder.elemList[idx];
1636 BasicBlock* bb = (BasicBlock *)
1637 oatGrowableListGetElement(blockList, revIdx);
1638 change |= (*func)(cUnit, bb);
1639 }
1640 }
1641 break;
1642 default:
1643 LOG(FATAL) << "Unknown traversal mode " << (int)dfaMode;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1644 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1645 /* If isIterative is false, exit the loop after the first iteration */
1646 change &= isIterative;
1647 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1648}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1649
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1650/* Advance to next strictly dominated MIR node in an extended basic block */
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1651MIR* advanceMIR(CompilationUnit* cUnit, BasicBlock** pBb, MIR* mir,
1652 ArenaBitVector* bv, bool clearMark) {
1653 BasicBlock* bb = *pBb;
1654 if (mir != NULL) {
1655 mir = mir->next;
1656 if (mir == NULL) {
1657 bb = bb->fallThrough;
1658 if ((bb == NULL) || bb->predecessors->numUsed != 1) {
1659 mir = NULL;
1660 } else {
1661 if (bv) {
1662 oatSetBit(cUnit, bv, bb->id);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1663 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1664 *pBb = bb;
1665 mir = bb->firstMIRInsn;
1666 }
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1667 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1668 }
1669 if (mir && clearMark) {
1670 mir->optimizationFlags &= ~MIR_MARK;
1671 }
1672 return mir;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1673}
1674
buzbeefc9e6fa2012-03-23 15:14:29 -0700[diff] [blame]1675/*
1676 * To be used at an invoke mir. If the logically next mir node represents
1677 * a move-result, return it. Else, return NULL. If a move-result exists,
1678 * it is required to immediately follow the invoke with no intervening
1679 * opcodes or incoming arcs. However, if the result of the invoke is not
1680 * used, a move-result may not be present.
1681 */
1682MIR* oatFindMoveResult(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1683 bool wide)
buzbeefc9e6fa2012-03-23 15:14:29 -0700[diff] [blame]1684{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1685 BasicBlock* tbb = bb;
1686 mir = advanceMIR(cUnit, &tbb, mir, NULL, false);
1687 while (mir != NULL) {
1688 if (!wide && mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) {
1689 break;
buzbeefc9e6fa2012-03-23 15:14:29 -0700[diff] [blame]1690 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1691 if (wide && mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE) {
1692 break;
1693 }
1694 // Keep going if pseudo op, otherwise terminate
1695 if (mir->dalvikInsn.opcode <
1696 static_cast<Instruction::Code>(kNumPackedOpcodes)) {
1697 mir = NULL;
1698 } else {
1699 mir = advanceMIR(cUnit, &tbb, mir, NULL, false);
1700 }
1701 }
1702 return mir;
buzbeefc9e6fa2012-03-23 15:14:29 -0700[diff] [blame]1703}
1704
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]1705void squashDupRangeChecks(CompilationUnit* cUnit, BasicBlock** pBp, MIR* mir,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1706 int arraySreg, int indexSreg)
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]1707{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1708 while (true) {
1709 mir = advanceMIR(cUnit, pBp, mir, NULL, false);
1710 if (!mir) {
1711 break;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]1712 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1713 if ((mir->ssaRep == NULL) ||
1714 (mir->optimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
1715 continue;
1716 }
1717 int checkArray = INVALID_SREG;
1718 int checkIndex = INVALID_SREG;
1719 switch (mir->dalvikInsn.opcode) {
1720 case Instruction::AGET:
1721 case Instruction::AGET_OBJECT:
1722 case Instruction::AGET_BOOLEAN:
1723 case Instruction::AGET_BYTE:
1724 case Instruction::AGET_CHAR:
1725 case Instruction::AGET_SHORT:
1726 case Instruction::AGET_WIDE:
1727 checkArray = mir->ssaRep->uses[0];
1728 checkIndex = mir->ssaRep->uses[1];
1729 break;
1730 case Instruction::APUT:
1731 case Instruction::APUT_OBJECT:
1732 case Instruction::APUT_SHORT:
1733 case Instruction::APUT_CHAR:
1734 case Instruction::APUT_BYTE:
1735 case Instruction::APUT_BOOLEAN:
1736 checkArray = mir->ssaRep->uses[1];
1737 checkIndex = mir->ssaRep->uses[2];
1738 break;
1739 case Instruction::APUT_WIDE:
1740 checkArray = mir->ssaRep->uses[2];
1741 checkIndex = mir->ssaRep->uses[3];
1742 default:
1743 break;
1744 }
1745 if (checkArray == INVALID_SREG) {
1746 continue;
1747 }
1748 if ((arraySreg == checkArray) && (indexSreg == checkIndex)) {
1749 if (cUnit->printMe) {
1750 LOG(INFO) << "Squashing range check @ 0x" << std::hex << mir->offset;
1751 }
1752 mir->optimizationFlags |= MIR_IGNORE_RANGE_CHECK;
1753 }
1754 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]1755}
1756
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1757/* Allocate a compiler temp, return Sreg. Reuse existing if no conflict */
1758int allocCompilerTempSreg(CompilationUnit* cUnit, ArenaBitVector* bv)
1759{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1760 for (int i = 0; i < cUnit->numCompilerTemps; i++) {
1761 CompilerTemp* ct = (CompilerTemp*)cUnit->compilerTemps.elemList[i];
1762 ArenaBitVector* tBv = ct->bv;
1763 if (!oatTestBitVectors(bv, tBv)) {
1764 // Combine live maps and reuse existing temp
1765 oatUnifyBitVectors(tBv, tBv, bv);
1766 return ct->sReg;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1767 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1768 }
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1769
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1770 // Create a new compiler temp & associated live bitmap
1771 CompilerTemp* ct = (CompilerTemp*)oatNew(cUnit, sizeof(CompilerTemp),
1772 true, kAllocMisc);
1773 ArenaBitVector *nBv = oatAllocBitVector(cUnit, cUnit->numBlocks, true,
1774 kBitMapMisc);
1775 oatCopyBitVector(nBv, bv);
1776 ct->bv = nBv;
1777 ct->sReg = addNewSReg(cUnit, SSA_CTEMP_BASEREG - cUnit->numCompilerTemps);
1778 cUnit->numCompilerTemps++;
1779 oatInsertGrowableList(cUnit, &cUnit->compilerTemps, (intptr_t)ct);
1780 DCHECK_EQ(cUnit->numCompilerTemps, (int)cUnit->compilerTemps.numUsed);
1781 return ct->sReg;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1782}
1783
1784/* Creata a new MIR node for a new pseudo op. */
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1785MIR* rawMIR(CompilationUnit* cUnit, Instruction::Code opcode, int defs,
1786 int uses)
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1787{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1788 MIR* res = (MIR*)oatNew( cUnit, sizeof(MIR), true, kAllocMIR);
1789 res->ssaRep =(struct SSARepresentation *)
1790 oatNew(cUnit, sizeof(SSARepresentation), true, kAllocDFInfo);
1791 if (uses) {
1792 res->ssaRep->numUses = uses;
1793 res->ssaRep->uses = (int*)oatNew(cUnit, sizeof(int) * uses, false,
1794 kAllocDFInfo);
1795 }
1796 if (defs) {
1797 res->ssaRep->numDefs = defs;
1798 res->ssaRep->defs = (int*)oatNew(cUnit, sizeof(int) * defs, false,
1799 kAllocDFInfo);
1800 res->ssaRep->fpDef = (bool*)oatNew(cUnit, sizeof(bool) * defs, true,
1801 kAllocDFInfo);
1802 }
1803 res->dalvikInsn.opcode = opcode;
1804 return res;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1805}
1806
1807/* Do some MIR-level basic block optimizations */
1808bool basicBlockOpt(CompilationUnit* cUnit, BasicBlock* bb)
1809{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1810 int numTemps = 0;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1811
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1812 for (MIR* mir = bb->firstMIRInsn; mir; mir = mir->next) {
1813 // Look for interesting opcodes, skip otherwise
1814 Instruction::Code opcode = mir->dalvikInsn.opcode;
1815 switch (opcode) {
1816 case Instruction::AGET:
1817 case Instruction::AGET_OBJECT:
1818 case Instruction::AGET_BOOLEAN:
1819 case Instruction::AGET_BYTE:
1820 case Instruction::AGET_CHAR:
1821 case Instruction::AGET_SHORT:
1822 case Instruction::AGET_WIDE:
1823 if (!(mir->optimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
1824 int arrSreg = mir->ssaRep->uses[0];
1825 int idxSreg = mir->ssaRep->uses[1];
1826 BasicBlock* tbb = bb;
1827 squashDupRangeChecks(cUnit, &tbb, mir, arrSreg, idxSreg);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1828 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1829 break;
1830 case Instruction::APUT:
1831 case Instruction::APUT_OBJECT:
1832 case Instruction::APUT_SHORT:
1833 case Instruction::APUT_CHAR:
1834 case Instruction::APUT_BYTE:
1835 case Instruction::APUT_BOOLEAN:
1836 case Instruction::APUT_WIDE:
1837 if (!(mir->optimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
1838 int start = (opcode == Instruction::APUT_WIDE) ? 2 : 1;
1839 int arrSreg = mir->ssaRep->uses[start];
1840 int idxSreg = mir->ssaRep->uses[start + 1];
1841 BasicBlock* tbb = bb;
1842 squashDupRangeChecks(cUnit, &tbb, mir, arrSreg, idxSreg);
1843 }
1844 break;
1845 case Instruction::CMPL_FLOAT:
1846 case Instruction::CMPL_DOUBLE:
1847 case Instruction::CMPG_FLOAT:
1848 case Instruction::CMPG_DOUBLE:
1849 case Instruction::CMP_LONG:
1850 if (mir->next != NULL) {
1851 MIR* mirNext = mir->next;
1852 Instruction::Code brOpcode = mirNext->dalvikInsn.opcode;
1853 ConditionCode ccode = kCondNv;
1854 switch(brOpcode) {
1855 case Instruction::IF_EQZ:
1856 ccode = kCondEq;
1857 break;
1858 case Instruction::IF_NEZ:
1859 ccode = kCondNe;
1860 break;
1861 case Instruction::IF_LTZ:
1862 ccode = kCondLt;
1863 break;
1864 case Instruction::IF_GEZ:
1865 ccode = kCondGe;
1866 break;
1867 case Instruction::IF_GTZ:
1868 ccode = kCondGt;
1869 break;
1870 case Instruction::IF_LEZ:
1871 ccode = kCondLe;
1872 break;
1873 default:
1874 break;
1875 }
1876 // Make sure result of cmp is used by next insn and nowhere else
1877 if ((ccode != kCondNv) &&
1878 (mir->ssaRep->defs[0] == mirNext->ssaRep->uses[0]) &&
1879 (getSSAUseCount(cUnit, mir->ssaRep->defs[0]) == 1)) {
1880 mirNext->dalvikInsn.arg[0] = ccode;
1881 switch(opcode) {
1882 case Instruction::CMPL_FLOAT:
1883 mirNext->dalvikInsn.opcode =
1884 static_cast<Instruction::Code>(kMirOpFusedCmplFloat);
1885 break;
1886 case Instruction::CMPL_DOUBLE:
1887 mirNext->dalvikInsn.opcode =
1888 static_cast<Instruction::Code>(kMirOpFusedCmplDouble);
1889 break;
1890 case Instruction::CMPG_FLOAT:
1891 mirNext->dalvikInsn.opcode =
1892 static_cast<Instruction::Code>(kMirOpFusedCmpgFloat);
1893 break;
1894 case Instruction::CMPG_DOUBLE:
1895 mirNext->dalvikInsn.opcode =
1896 static_cast<Instruction::Code>(kMirOpFusedCmpgDouble);
1897 break;
1898 case Instruction::CMP_LONG:
1899 mirNext->dalvikInsn.opcode =
1900 static_cast<Instruction::Code>(kMirOpFusedCmpLong);
1901 break;
1902 default: LOG(ERROR) << "Unexpected opcode: " << (int)opcode;
1903 }
1904 mir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
1905 mirNext->ssaRep->numUses = mir->ssaRep->numUses;
1906 mirNext->ssaRep->uses = mir->ssaRep->uses;
1907 mirNext->ssaRep->fpUse = mir->ssaRep->fpUse;
1908 mirNext->ssaRep->numDefs = 0;
1909 mir->ssaRep->numUses = 0;
1910 mir->ssaRep->numDefs = 0;
1911 }
1912 }
1913 break;
1914 default:
1915 break;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1916 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1917 }
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1918
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1919 if (numTemps > cUnit->numCompilerTemps) {
1920 cUnit->numCompilerTemps = numTemps;
1921 }
1922 return true;
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]1923}
1924
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1925bool nullCheckEliminationInit(struct CompilationUnit* cUnit,
1926 struct BasicBlock* bb)
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1927{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1928 if (bb->dataFlowInfo == NULL) return false;
1929 bb->dataFlowInfo->endingNullCheckV =
1930 oatAllocBitVector(cUnit, cUnit->numSSARegs, false, kBitMapNullCheck);
1931 oatClearAllBits(bb->dataFlowInfo->endingNullCheckV);
1932 return true;
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1933}
1934
1935/* Eliminate unnecessary null checks for a basic block. */
buzbee31a4a6f2012-02-28 15:36:15 -0800[diff] [blame]1936bool eliminateNullChecks( struct CompilationUnit* cUnit, struct BasicBlock* bb)
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1937{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]1938 if (bb->dataFlowInfo == NULL) return false;
1939
1940 /*
1941 * Set initial state. Be conservative with catch
1942 * blocks and start with no assumptions about null check
1943 * status (except for "this").
1944 */
1945 if ((bb->blockType == kEntryBlock) | bb->catchEntry) {
1946 oatClearAllBits(cUnit->tempSSARegisterV);
1947 if ((cUnit->access_flags & kAccStatic) == 0) {
1948 // If non-static method, mark "this" as non-null
1949 int thisReg = cUnit->numDalvikRegisters - cUnit->numIns;
1950 oatSetBit(cUnit, cUnit->tempSSARegisterV, thisReg);
1951 }
1952 } else {
1953 // Starting state is intesection of all incoming arcs
1954 GrowableListIterator iter;
1955 oatGrowableListIteratorInit(bb->predecessors, &iter);
1956 BasicBlock* predBB = (BasicBlock*)oatGrowableListIteratorNext(&iter);
1957 DCHECK(predBB != NULL);
1958 oatCopyBitVector(cUnit->tempSSARegisterV,
1959 predBB->dataFlowInfo->endingNullCheckV);
1960 while (true) {
1961 predBB = (BasicBlock*)oatGrowableListIteratorNext(&iter);
1962 if (!predBB) break;
1963 if ((predBB->dataFlowInfo == NULL) ||
1964 (predBB->dataFlowInfo->endingNullCheckV == NULL)) {
1965 continue;
1966 }
1967 oatIntersectBitVectors(cUnit->tempSSARegisterV,
1968 cUnit->tempSSARegisterV,
1969 predBB->dataFlowInfo->endingNullCheckV);
1970 }
1971 }
1972
1973 // Walk through the instruction in the block, updating as necessary
1974 for (MIR* mir = bb->firstMIRInsn; mir; mir = mir->next) {
1975 if (mir->ssaRep == NULL) {
1976 continue;
1977 }
1978 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
1979
1980 // Mark target of NEW* as non-null
1981 if (dfAttributes & DF_NON_NULL_DST) {
1982 oatSetBit(cUnit, cUnit->tempSSARegisterV, mir->ssaRep->defs[0]);
1983 }
1984
1985 // Mark non-null returns from invoke-style NEW*
1986 if (dfAttributes & DF_NON_NULL_RET) {
1987 MIR* nextMir = mir->next;
1988 // Next should be an MOVE_RESULT_OBJECT
1989 if (nextMir &&
1990 nextMir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) {
1991 // Mark as null checked
1992 oatSetBit(cUnit, cUnit->tempSSARegisterV, nextMir->ssaRep->defs[0]);
1993 } else {
1994 if (nextMir) {
1995 LOG(WARNING) << "Unexpected opcode following new: "
1996 << (int)nextMir->dalvikInsn.opcode;
1997 } else if (bb->fallThrough) {
1998 // Look in next basic block
1999 struct BasicBlock* nextBB = bb->fallThrough;
2000 for (MIR* tmir = nextBB->firstMIRInsn; tmir;
2001 tmir =tmir->next) {
2002 if ((int)tmir->dalvikInsn.opcode >= (int)kMirOpFirst) {
2003 continue;
2004 }
2005 // First non-pseudo should be MOVE_RESULT_OBJECT
2006 if (tmir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) {
2007 // Mark as null checked
2008 oatSetBit(cUnit, cUnit->tempSSARegisterV, tmir->ssaRep->defs[0]);
2009 } else {
2010 LOG(WARNING) << "Unexpected op after new: "
2011 << (int)tmir->dalvikInsn.opcode;
2012 }
2013 break;
2014 }
2015 }
2016 }
2017 }
buzbee5abfa3e2012-01-31 17:01:43 -0800[diff] [blame]2018
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2019 /*
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2020 * Propagate nullcheck state on register copies (including
2021 * Phi pseudo copies. For the latter, nullcheck state is
2022 * the "and" of all the Phi's operands.
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2023 */
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2024 if (dfAttributes & (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N)) {
2025 int tgtSreg = mir->ssaRep->defs[0];
2026 int operands = (dfAttributes & DF_NULL_TRANSFER_0) ? 1 :
2027 mir->ssaRep->numUses;
2028 bool nullChecked = true;
2029 for (int i = 0; i < operands; i++) {
2030 nullChecked &= oatIsBitSet(cUnit->tempSSARegisterV,
2031 mir->ssaRep->uses[i]);
2032 }
2033 if (nullChecked) {
2034 oatSetBit(cUnit, cUnit->tempSSARegisterV, tgtSreg);
2035 }
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2036 }
2037
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2038 // Already nullchecked?
2039 if (dfAttributes & DF_HAS_NULL_CHKS) {
2040 int srcIdx;
2041 if (dfAttributes & DF_NULL_CHK_1) {
2042 srcIdx = 1;
2043 } else if (dfAttributes & DF_NULL_CHK_2) {
2044 srcIdx = 2;
2045 } else {
2046 srcIdx = 0;
2047 }
2048 int srcSreg = mir->ssaRep->uses[srcIdx];
2049 if (oatIsBitSet(cUnit->tempSSARegisterV, srcSreg)) {
2050 // Eliminate the null check
2051 mir->optimizationFlags |= MIR_IGNORE_NULL_CHECK;
2052 } else {
2053 // Mark sReg as null-checked
2054 oatSetBit(cUnit, cUnit->tempSSARegisterV, srcSreg);
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2055 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2056 }
2057 }
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2058
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2059 // Did anything change?
2060 bool res = oatCompareBitVectors(bb->dataFlowInfo->endingNullCheckV,
2061 cUnit->tempSSARegisterV);
2062 if (res) {
2063 oatCopyBitVector(bb->dataFlowInfo->endingNullCheckV,
2064 cUnit->tempSSARegisterV);
2065 }
2066 return res;
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2067}
2068
2069void oatMethodNullCheckElimination(CompilationUnit *cUnit)
2070{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2071 if (!(cUnit->disableOpt & (1 << kNullCheckElimination))) {
2072 DCHECK(cUnit->tempSSARegisterV != NULL);
2073 oatDataFlowAnalysisDispatcher(cUnit, nullCheckEliminationInit, kAllNodes,
2074 false /* isIterative */);
2075 oatDataFlowAnalysisDispatcher(cUnit, eliminateNullChecks,
2076 kPreOrderDFSTraversal,
2077 true /* isIterative */);
2078 }
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]2079}
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]2080
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]2081void oatMethodBasicBlockOptimization(CompilationUnit *cUnit)
2082{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2083 if (!(cUnit->disableOpt & (1 << kBBOpt))) {
2084 oatInitGrowableList(cUnit, &cUnit->compilerTemps, 6, kListMisc);
2085 DCHECK_EQ(cUnit->numCompilerTemps, 0);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]2086 if (!(cUnit->disableOpt & (1 << kBBOpt))) {
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2087 oatDataFlowAnalysisDispatcher(cUnit, basicBlockOpt,
2088 kAllNodes, false /* isIterative */);
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]2089 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2090 }
buzbeee1965672012-03-11 18:39:19 -0700[diff] [blame]2091}
2092
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2093void addLoopHeader(CompilationUnit* cUnit, BasicBlock* header,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2094 BasicBlock* backEdge)
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2095{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2096 GrowableListIterator iter;
2097 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2098 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2099 (loop != NULL); loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2100 if (loop->header == header) {
2101 oatInsertGrowableList(cUnit, &loop->incomingBackEdges,
2102 (intptr_t)backEdge);
2103 return;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2104 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2105 }
2106 LoopInfo* info = (LoopInfo*)oatNew(cUnit, sizeof(LoopInfo), true,
2107 kAllocDFInfo);
2108 info->header = header;
2109 oatInitGrowableList(cUnit, &info->incomingBackEdges, 2, kListMisc);
2110 oatInsertGrowableList(cUnit, &info->incomingBackEdges, (intptr_t)backEdge);
2111 oatInsertGrowableList(cUnit, &cUnit->loopHeaders, (intptr_t)info);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2112}
2113
2114bool findBackEdges(struct CompilationUnit* cUnit, struct BasicBlock* bb)
2115{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2116 if ((bb->dataFlowInfo == NULL) || (bb->lastMIRInsn == NULL)) {
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2117 return false;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2118 }
2119 Instruction::Code opcode = bb->lastMIRInsn->dalvikInsn.opcode;
2120 if (Instruction::Flags(opcode) & Instruction::kBranch) {
2121 if (bb->taken && (bb->taken->startOffset <= bb->startOffset)) {
2122 DCHECK(bb->dominators != NULL);
2123 if (oatIsBitSet(bb->dominators, bb->taken->id)) {
2124 if (cUnit->printMe) {
2125 LOG(INFO) << "Loop backedge from 0x"
2126 << std::hex << bb->lastMIRInsn->offset
2127 << " to 0x" << std::hex << bb->taken->startOffset;
2128 }
2129 addLoopHeader(cUnit, bb->taken, bb);
2130 }
2131 }
2132 }
2133 return false;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2134}
2135
2136void addBlocksToLoop(CompilationUnit* cUnit, ArenaBitVector* blocks,
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2137 BasicBlock* bb, int headId)
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2138{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2139 if (!oatIsBitSet(bb->dominators, headId) ||
2140 oatIsBitSet(blocks, bb->id)) {
2141 return;
2142 }
2143 oatSetBit(cUnit, blocks, bb->id);
2144 GrowableListIterator iter;
2145 oatGrowableListIteratorInit(bb->predecessors, &iter);
2146 BasicBlock* predBB;
2147 for (predBB = (BasicBlock*)oatGrowableListIteratorNext(&iter); predBB;
2148 predBB = (BasicBlock*)oatGrowableListIteratorNext(&iter)) {
2149 addBlocksToLoop(cUnit, blocks, predBB, headId);
2150 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2151}
2152
2153void oatDumpLoops(CompilationUnit *cUnit)
2154{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2155 GrowableListIterator iter;
2156 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2157 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2158 (loop != NULL); loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2159 LOG(INFO) << "Loop head block id " << loop->header->id
2160 << ", offset 0x" << std::hex << loop->header->startOffset
2161 << ", Depth: " << loop->header->nestingDepth;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2162 GrowableListIterator iter;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2163 oatGrowableListIteratorInit(&loop->incomingBackEdges, &iter);
2164 BasicBlock* edgeBB;
2165 for (edgeBB = (BasicBlock*)oatGrowableListIteratorNext(&iter); edgeBB;
2166 edgeBB = (BasicBlock*)oatGrowableListIteratorNext(&iter)) {
2167 LOG(INFO) << " Backedge block id " << edgeBB->id
2168 << ", offset 0x" << std::hex << edgeBB->startOffset;
2169 ArenaBitVectorIterator bIter;
2170 oatBitVectorIteratorInit(loop->blocks, &bIter);
2171 for (int bbId = oatBitVectorIteratorNext(&bIter); bbId != -1;
2172 bbId = oatBitVectorIteratorNext(&bIter)) {
2173 BasicBlock *bb;
2174 bb = (BasicBlock*)
2175 oatGrowableListGetElement(&cUnit->blockList, bbId);
2176 LOG(INFO) << " (" << bb->id << ", 0x" << std::hex
2177 << bb->startOffset << ")";
2178 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2179 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2180 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2181}
2182
2183void oatMethodLoopDetection(CompilationUnit *cUnit)
2184{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2185 if (cUnit->disableOpt & (1 << kPromoteRegs)) {
2186 return;
2187 }
2188 oatInitGrowableList(cUnit, &cUnit->loopHeaders, 6, kListMisc);
2189 // Find the loop headers
2190 oatDataFlowAnalysisDispatcher(cUnit, findBackEdges,
2191 kAllNodes, false /* isIterative */);
2192 GrowableListIterator iter;
2193 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2194 // Add blocks to each header
2195 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2196 loop; loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2197 loop->blocks = oatAllocBitVector(cUnit, cUnit->numBlocks, true,
2198 kBitMapMisc);
2199 oatSetBit(cUnit, loop->blocks, loop->header->id);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2200 GrowableListIterator iter;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2201 oatGrowableListIteratorInit(&loop->incomingBackEdges, &iter);
2202 BasicBlock* edgeBB;
2203 for (edgeBB = (BasicBlock*)oatGrowableListIteratorNext(&iter); edgeBB;
2204 edgeBB = (BasicBlock*)oatGrowableListIteratorNext(&iter)) {
2205 addBlocksToLoop(cUnit, loop->blocks, edgeBB, loop->header->id);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2206 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2207 }
2208 // Compute the nesting depth of each header
2209 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2210 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2211 loop; loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2212 GrowableListIterator iter2;
2213 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter2);
2214 LoopInfo* loop2;
2215 for (loop2 = (LoopInfo*)oatGrowableListIteratorNext(&iter2);
2216 loop2; loop2 = (LoopInfo*)oatGrowableListIteratorNext(&iter2)) {
2217 if (oatIsBitSet(loop2->blocks, loop->header->id)) {
2218 loop->header->nestingDepth++;
2219 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2220 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2221 }
2222 // Assign nesting depth to each block in all loops
2223 oatGrowableListIteratorInit(&cUnit->loopHeaders, &iter);
2224 for (LoopInfo* loop = (LoopInfo*)oatGrowableListIteratorNext(&iter);
2225 (loop != NULL); loop = (LoopInfo*)oatGrowableListIteratorNext(&iter)) {
2226 ArenaBitVectorIterator bIter;
2227 oatBitVectorIteratorInit(loop->blocks, &bIter);
2228 for (int bbId = oatBitVectorIteratorNext(&bIter); bbId != -1;
2229 bbId = oatBitVectorIteratorNext(&bIter)) {
2230 BasicBlock *bb;
2231 bb = (BasicBlock*) oatGrowableListGetElement(&cUnit->blockList, bbId);
2232 bb->nestingDepth = std::max(bb->nestingDepth,
2233 loop->header->nestingDepth);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2234 }
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2235 }
2236 if (cUnit->printMe) {
2237 oatDumpLoops(cUnit);
2238 }
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2239}
2240
2241/*
buzbee9c044ce2012-03-18 13:24:07 -0700[diff] [blame]2242 * This function will make a best guess at whether the invoke will
2243 * end up using Method*. It isn't critical to get it exactly right,
2244 * and attempting to do would involve more complexity than it's
2245 * worth.
2246 */
2247bool invokeUsesMethodStar(CompilationUnit* cUnit, MIR* mir)
2248{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2249 InvokeType type;
2250 Instruction::Code opcode = mir->dalvikInsn.opcode;
2251 switch (opcode) {
2252 case Instruction::INVOKE_STATIC:
2253 case Instruction::INVOKE_STATIC_RANGE:
2254 type = kStatic;
2255 break;
2256 case Instruction::INVOKE_DIRECT:
2257 case Instruction::INVOKE_DIRECT_RANGE:
2258 type = kDirect;
2259 break;
2260 case Instruction::INVOKE_VIRTUAL:
2261 case Instruction::INVOKE_VIRTUAL_RANGE:
2262 type = kVirtual;
2263 break;
2264 case Instruction::INVOKE_INTERFACE:
2265 case Instruction::INVOKE_INTERFACE_RANGE:
2266 return false;
2267 case Instruction::INVOKE_SUPER_RANGE:
2268 case Instruction::INVOKE_SUPER:
2269 type = kSuper;
2270 break;
2271 default:
2272 LOG(WARNING) << "Unexpected invoke op: " << (int)opcode;
2273 return false;
2274 }
2275 OatCompilationUnit mUnit(cUnit->class_loader, cUnit->class_linker,
2276 *cUnit->dex_file, *cUnit->dex_cache,
2277 cUnit->code_item, cUnit->method_idx,
2278 cUnit->access_flags);
2279 // TODO: add a flag so we don't counts the stats for this twice
2280 uint32_t dexMethodIdx = mir->dalvikInsn.vB;
2281 int vtableIdx;
2282 uintptr_t directCode;
2283 uintptr_t directMethod;
2284 bool fastPath =
2285 cUnit->compiler->ComputeInvokeInfo(dexMethodIdx, &mUnit, type,
2286 vtableIdx, directCode,
2287 directMethod) &&
2288 !SLOW_INVOKE_PATH;
2289 return (((type == kDirect) || (type == kStatic)) &&
2290 fastPath && ((directCode == 0) || (directMethod == 0)));
buzbee9c044ce2012-03-18 13:24:07 -0700[diff] [blame]2291}
2292
2293/*
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2294 * Count uses, weighting by loop nesting depth. This code only
2295 * counts explicitly used sRegs. A later phase will add implicit
2296 * counts for things such as Method*, null-checked references, etc.
2297 */
2298bool countUses(struct CompilationUnit* cUnit, struct BasicBlock* bb)
2299{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2300 if (bb->blockType != kDalvikByteCode) {
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2301 return false;
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2302 }
2303 for (MIR* mir = bb->firstMIRInsn; (mir != NULL); mir = mir->next) {
2304 if (mir->ssaRep == NULL) {
2305 continue;
2306 }
2307 uint32_t weight = std::min(16U, (uint32_t)bb->nestingDepth);
2308 for (int i = 0; i < mir->ssaRep->numUses; i++) {
2309 int sReg = mir->ssaRep->uses[i];
2310 DCHECK_LT(sReg, (int)cUnit->useCounts.numUsed);
2311 cUnit->rawUseCounts.elemList[sReg]++;
2312 cUnit->useCounts.elemList[sReg] += (1 << weight);
2313 }
2314 if (!(cUnit->disableOpt & (1 << kPromoteCompilerTemps))) {
2315 int dfAttributes = oatDataFlowAttributes[mir->dalvikInsn.opcode];
2316 // Implicit use of Method* ? */
2317 if (dfAttributes & DF_UMS) {
2318 /*
2319 * Some invokes will not use Method* - need to perform test similar
2320 * to that found in genInvoke() to decide whether to count refs
2321 * for Method* on invoke-class opcodes.
2322 * TODO: refactor for common test here, save results for genInvoke
2323 */
2324 int usesMethodStar = true;
2325 if ((dfAttributes & (DF_FORMAT_35C | DF_FORMAT_3RC)) &&
2326 !(dfAttributes & DF_NON_NULL_RET)) {
2327 usesMethodStar &= invokeUsesMethodStar(cUnit, mir);
2328 }
2329 if (usesMethodStar) {
2330 cUnit->rawUseCounts.elemList[cUnit->methodSReg]++;
2331 cUnit->useCounts.elemList[cUnit->methodSReg] += (1 << weight);
2332 }
2333 }
2334 }
2335 }
2336 return false;
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2337}
2338
2339void oatMethodUseCount(CompilationUnit *cUnit)
2340{
Bill Buzbeea114add2012-05-03 15:00:40 -0700[diff] [blame]2341 oatInitGrowableList(cUnit, &cUnit->useCounts, cUnit->numSSARegs + 32,
2342 kListMisc);
2343 oatInitGrowableList(cUnit, &cUnit->rawUseCounts, cUnit->numSSARegs + 32,
2344 kListMisc);
2345 // Initialize list
2346 for (int i = 0; i < cUnit->numSSARegs; i++) {
2347 oatInsertGrowableList(cUnit, &cUnit->useCounts, 0);
2348 oatInsertGrowableList(cUnit, &cUnit->rawUseCounts, 0);
2349 }
2350 if (cUnit->disableOpt & (1 << kPromoteRegs)) {
2351 return;
2352 }
2353 oatDataFlowAnalysisDispatcher(cUnit, countUses,
2354 kAllNodes, false /* isIterative */);
buzbee239c4e72012-03-16 08:42:29 -0700[diff] [blame]2355}
2356
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]2357} // namespace art