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buzbeecbd6d442012-11-17 14:11:25 -08001/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Brian Carlstromfc0e3212013-07-17 14:40:12 -070017#ifndef ART_COMPILER_DEX_COMPILER_ENUMS_H_
18#define ART_COMPILER_DEX_COMPILER_ENUMS_H_
buzbeecbd6d442012-11-17 14:11:25 -080019
20#include "dex_instruction.h"
21
22namespace art {
23
24enum RegisterClass {
25 kCoreReg,
26 kFPReg,
27 kAnyReg,
28};
29
30enum SpecialTargetRegister {
buzbee02031b12012-11-23 09:41:35 -080031 kSelf, // Thread pointer.
32 kSuspend, // Used to reduce suspend checks for some targets.
buzbeecbd6d442012-11-17 14:11:25 -080033 kLr,
34 kPc,
35 kSp,
36 kArg0,
37 kArg1,
38 kArg2,
39 kArg3,
40 kFArg0,
41 kFArg1,
42 kFArg2,
43 kFArg3,
44 kRet0,
45 kRet1,
46 kInvokeTgt,
Jeff Hao88474b42013-10-23 16:24:40 -070047 kHiddenArg,
48 kHiddenFpArg,
buzbeecbd6d442012-11-17 14:11:25 -080049 kCount
50};
51
52enum RegLocationType {
Brian Carlstrom7934ac22013-07-26 10:54:15 -070053 kLocDalvikFrame = 0, // Normal Dalvik register
buzbeecbd6d442012-11-17 14:11:25 -080054 kLocPhysReg,
55 kLocCompilerTemp,
56 kLocInvalid
57};
58
Bill Buzbeed61ba4b2014-01-13 21:44:01 +000059/**
60 * Support for vector registers. Initially used for x86 floats. This will be used
61 * to replace the assumption that a double takes up 2 single FP registers
62 */
63enum VectorLengthType {
64 kVectorNotUsed = 0, // This value is NOT in a vector register.
65 kVectorLength4, // The value occupies 4 bytes in a vector register.
66 kVectorLength8, // The value occupies 8 bytes in a vector register.
67 kVectorLength16 // The value occupies 16 bytes in a vector register (unused now).
68};
69
buzbeecbd6d442012-11-17 14:11:25 -080070enum BBType {
buzbee0d829482013-10-11 15:24:55 -070071 kNullBlock,
buzbeecbd6d442012-11-17 14:11:25 -080072 kEntryBlock,
73 kDalvikByteCode,
74 kExitBlock,
75 kExceptionHandling,
76 kDead,
77};
78
79/*
buzbeefa57c472012-11-21 12:06:18 -080080 * Def/Use encoding in 64-bit use_mask/def_mask. Low positions used for target-specific
buzbeecbd6d442012-11-17 14:11:25 -080081 * registers (and typically use the register number as the position). High positions
82 * reserved for common and abstract resources.
83 */
84
85enum ResourceEncodingPos {
86 kMustNotAlias = 63,
buzbee02031b12012-11-23 09:41:35 -080087 kHeapRef = 62, // Default memory reference type.
88 kLiteral = 61, // Literal pool memory reference.
89 kDalvikReg = 60, // Dalvik v_reg memory reference.
buzbeecbd6d442012-11-17 14:11:25 -080090 kFPStatus = 59,
91 kCCode = 58,
92 kLowestCommonResource = kCCode
93};
94
buzbee02031b12012-11-23 09:41:35 -080095// Shared pseudo opcodes - must be < 0.
buzbeecbd6d442012-11-17 14:11:25 -080096enum LIRPseudoOpcode {
buzbeea169e1d2012-12-05 14:26:44 -080097 kPseudoExportedPC = -16,
98 kPseudoSafepointPC = -15,
99 kPseudoIntrinsicRetry = -14,
100 kPseudoSuspendTarget = -13,
101 kPseudoThrowTarget = -12,
102 kPseudoCaseLabel = -11,
103 kPseudoMethodEntry = -10,
104 kPseudoMethodExit = -9,
105 kPseudoBarrier = -8,
buzbeecbd6d442012-11-17 14:11:25 -0800106 kPseudoEntryBlock = -7,
107 kPseudoExitBlock = -6,
108 kPseudoTargetLabel = -5,
109 kPseudoDalvikByteCodeBoundary = -4,
110 kPseudoPseudoAlign4 = -3,
111 kPseudoEHBlockLabel = -2,
112 kPseudoNormalBlockLabel = -1,
113};
114
115enum ExtendedMIROpcode {
116 kMirOpFirst = kNumPackedOpcodes,
117 kMirOpPhi = kMirOpFirst,
118 kMirOpCopy,
119 kMirOpFusedCmplFloat,
120 kMirOpFusedCmpgFloat,
121 kMirOpFusedCmplDouble,
122 kMirOpFusedCmpgDouble,
123 kMirOpFusedCmpLong,
124 kMirOpNop,
125 kMirOpNullCheck,
126 kMirOpRangeCheck,
127 kMirOpDivZeroCheck,
128 kMirOpCheck,
buzbeea169e1d2012-12-05 14:26:44 -0800129 kMirOpCheckPart2,
buzbeef662a7c2013-02-12 16:19:43 -0800130 kMirOpSelect,
buzbeecbd6d442012-11-17 14:11:25 -0800131 kMirOpLast,
132};
133
134enum MIROptimizationFlagPositons {
135 kMIRIgnoreNullCheck = 0,
136 kMIRNullCheckOnly,
137 kMIRIgnoreRangeCheck,
138 kMIRRangeCheckOnly,
Vladimir Markobfea9c22014-01-17 17:49:33 +0000139 kMIRIgnoreClInitCheck,
buzbee02031b12012-11-23 09:41:35 -0800140 kMIRInlined, // Invoke is inlined (ie dead).
141 kMIRInlinedPred, // Invoke is inlined via prediction.
142 kMIRCallee, // Instruction is inlined from callee.
buzbeecbd6d442012-11-17 14:11:25 -0800143 kMIRIgnoreSuspendCheck,
144 kMIRDup,
buzbee02031b12012-11-23 09:41:35 -0800145 kMIRMark, // Temporary node mark.
buzbeecbd6d442012-11-17 14:11:25 -0800146};
147
buzbee02031b12012-11-23 09:41:35 -0800148// For successor_block_list.
buzbeecbd6d442012-11-17 14:11:25 -0800149enum BlockListType {
150 kNotUsed = 0,
151 kCatch,
152 kPackedSwitch,
153 kSparseSwitch,
154};
155
156enum AssemblerStatus {
157 kSuccess,
158 kRetryAll,
159};
160
161enum OpSize {
162 kWord,
163 kLong,
164 kSingle,
165 kDouble,
166 kUnsignedHalf,
167 kSignedHalf,
168 kUnsignedByte,
169 kSignedByte,
170};
171
172std::ostream& operator<<(std::ostream& os, const OpSize& kind);
173
174enum OpKind {
175 kOpMov,
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800176 kOpCmov,
buzbeecbd6d442012-11-17 14:11:25 -0800177 kOpMvn,
178 kOpCmp,
179 kOpLsl,
180 kOpLsr,
181 kOpAsr,
182 kOpRor,
183 kOpNot,
184 kOpAnd,
185 kOpOr,
186 kOpXor,
187 kOpNeg,
188 kOpAdd,
189 kOpAdc,
190 kOpSub,
191 kOpSbc,
192 kOpRsub,
193 kOpMul,
194 kOpDiv,
195 kOpRem,
196 kOpBic,
197 kOpCmn,
198 kOpTst,
Vladimir Markoa8b4caf2013-10-24 15:08:57 +0100199 kOpRev,
200 kOpRevsh,
buzbeecbd6d442012-11-17 14:11:25 -0800201 kOpBkpt,
202 kOpBlx,
203 kOpPush,
204 kOpPop,
205 kOp2Char,
206 kOp2Short,
207 kOp2Byte,
208 kOpCondBr,
209 kOpUncondBr,
210 kOpBx,
211 kOpInvalid,
212};
213
Razvan A Lupusoru2c498d12014-01-29 16:02:57 -0800214enum MoveType {
215 kMov8GP, // Move 8-bit general purpose register.
216 kMov16GP, // Move 16-bit general purpose register.
217 kMov32GP, // Move 32-bit general purpose register.
218 kMov64GP, // Move 64-bit general purpose register.
219 kMov32FP, // Move 32-bit FP register.
220 kMov64FP, // Move 64-bit FP register.
221 kMovLo64FP, // Move low 32-bits of 64-bit FP register.
222 kMovHi64FP, // Move high 32-bits of 64-bit FP register.
223 kMovU128FP, // Move 128-bit FP register to/from possibly unaligned region.
224 kMov128FP = kMovU128FP,
225 kMovA128FP, // Move 128-bit FP register to/from region surely aligned to 16-bytes.
226 kMovLo128FP, // Move low 64-bits of 128-bit FP register.
227 kMovHi128FP, // Move high 64-bits of 128-bit FP register.
228};
229
buzbeecbd6d442012-11-17 14:11:25 -0800230std::ostream& operator<<(std::ostream& os, const OpKind& kind);
231
232enum ConditionCode {
233 kCondEq, // equal
234 kCondNe, // not equal
Vladimir Marko58af1f92013-12-19 13:31:15 +0000235 kCondCs, // carry set
236 kCondCc, // carry clear
Vladimir Marko459f4df2013-12-20 17:03:09 +0000237 kCondUlt, // unsigned less than
238 kCondUge, // unsigned greater than or same
buzbeecbd6d442012-11-17 14:11:25 -0800239 kCondMi, // minus
240 kCondPl, // plus, positive or zero
241 kCondVs, // overflow
242 kCondVc, // no overflow
243 kCondHi, // unsigned greater than
244 kCondLs, // unsigned lower or same
245 kCondGe, // signed greater than or equal
246 kCondLt, // signed less than
247 kCondGt, // signed greater than
248 kCondLe, // signed less than or equal
249 kCondAl, // always
250 kCondNv, // never
251};
252
253std::ostream& operator<<(std::ostream& os, const ConditionCode& kind);
254
255// Target specific condition encodings
256enum ArmConditionCode {
257 kArmCondEq = 0x0, // 0000
258 kArmCondNe = 0x1, // 0001
259 kArmCondCs = 0x2, // 0010
260 kArmCondCc = 0x3, // 0011
261 kArmCondMi = 0x4, // 0100
262 kArmCondPl = 0x5, // 0101
263 kArmCondVs = 0x6, // 0110
264 kArmCondVc = 0x7, // 0111
265 kArmCondHi = 0x8, // 1000
266 kArmCondLs = 0x9, // 1001
267 kArmCondGe = 0xa, // 1010
268 kArmCondLt = 0xb, // 1011
269 kArmCondGt = 0xc, // 1100
270 kArmCondLe = 0xd, // 1101
271 kArmCondAl = 0xe, // 1110
272 kArmCondNv = 0xf, // 1111
273};
274
275std::ostream& operator<<(std::ostream& os, const ArmConditionCode& kind);
276
277enum X86ConditionCode {
278 kX86CondO = 0x0, // overflow
279 kX86CondNo = 0x1, // not overflow
280
281 kX86CondB = 0x2, // below
282 kX86CondNae = kX86CondB, // not-above-equal
283 kX86CondC = kX86CondB, // carry
284
285 kX86CondNb = 0x3, // not-below
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700286 kX86CondAe = kX86CondNb, // above-equal
287 kX86CondNc = kX86CondNb, // not-carry
buzbeecbd6d442012-11-17 14:11:25 -0800288
289 kX86CondZ = 0x4, // zero
290 kX86CondEq = kX86CondZ, // equal
291
292 kX86CondNz = 0x5, // not-zero
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700293 kX86CondNe = kX86CondNz, // not-equal
buzbeecbd6d442012-11-17 14:11:25 -0800294
295 kX86CondBe = 0x6, // below-equal
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700296 kX86CondNa = kX86CondBe, // not-above
buzbeecbd6d442012-11-17 14:11:25 -0800297
298 kX86CondNbe = 0x7, // not-below-equal
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700299 kX86CondA = kX86CondNbe, // above
buzbeecbd6d442012-11-17 14:11:25 -0800300
301 kX86CondS = 0x8, // sign
302 kX86CondNs = 0x9, // not-sign
303
304 kX86CondP = 0xa, // 8-bit parity even
305 kX86CondPE = kX86CondP,
306
307 kX86CondNp = 0xb, // 8-bit parity odd
308 kX86CondPo = kX86CondNp,
309
310 kX86CondL = 0xc, // less-than
311 kX86CondNge = kX86CondL, // not-greater-equal
312
313 kX86CondNl = 0xd, // not-less-than
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700314 kX86CondGe = kX86CondNl, // not-greater-equal
buzbeecbd6d442012-11-17 14:11:25 -0800315
316 kX86CondLe = 0xe, // less-than-equal
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700317 kX86CondNg = kX86CondLe, // not-greater
buzbeecbd6d442012-11-17 14:11:25 -0800318
319 kX86CondNle = 0xf, // not-less-than
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700320 kX86CondG = kX86CondNle, // greater
buzbeecbd6d442012-11-17 14:11:25 -0800321};
322
323std::ostream& operator<<(std::ostream& os, const X86ConditionCode& kind);
324
325enum ThrowKind {
buzbeecbd6d442012-11-17 14:11:25 -0800326 kThrowArrayBounds,
buzbee4ef3e452012-12-14 13:35:28 -0800327 kThrowConstantArrayBounds,
buzbeecbd6d442012-11-17 14:11:25 -0800328 kThrowNoSuchMethod,
buzbeecbd6d442012-11-17 14:11:25 -0800329};
330
buzbeecbd6d442012-11-17 14:11:25 -0800331enum DividePattern {
332 DivideNone,
333 Divide3,
334 Divide5,
335 Divide7,
336};
337
338std::ostream& operator<<(std::ostream& os, const DividePattern& pattern);
339
Razvan A Lupusoru99ad7232014-02-25 17:41:08 -0800340/**
341 * @brief Memory barrier types (see "The JSR-133 Cookbook for Compiler Writers").
342 * @details Without context sensitive analysis, the most conservative set of barriers
343 * must be issued to ensure the Java Memory Model. Thus the recipe is as follows:
344 * -# Use StoreStore barrier before volatile store.
345 * -# Use StoreLoad barrier after volatile store.
346 * -# Use LoadLoad and LoadStore barrier after each volatile load.
347 * -# Use StoreStore barrier after all stores but before return from any constructor whose
348 * class has final fields.
349 */
buzbee1bc37c62012-11-20 13:35:41 -0800350enum MemBarrierKind {
351 kLoadStore,
352 kLoadLoad,
353 kStoreStore,
354 kStoreLoad
355};
356
357std::ostream& operator<<(std::ostream& os, const MemBarrierKind& kind);
358
buzbee02031b12012-11-23 09:41:35 -0800359enum OpFeatureFlags {
360 kIsBranch = 0,
361 kNoOperand,
362 kIsUnaryOp,
363 kIsBinaryOp,
364 kIsTertiaryOp,
365 kIsQuadOp,
366 kIsQuinOp,
367 kIsSextupleOp,
368 kIsIT,
369 kMemLoad,
370 kMemStore,
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700371 kPCRelFixup, // x86 FIXME: add NEEDS_FIXUP to instruction attributes.
buzbee02031b12012-11-23 09:41:35 -0800372 kRegDef0,
373 kRegDef1,
Razvan A Lupusoru99ad7232014-02-25 17:41:08 -0800374 kRegDef2,
buzbee02031b12012-11-23 09:41:35 -0800375 kRegDefA,
376 kRegDefD,
377 kRegDefFPCSList0,
378 kRegDefFPCSList2,
379 kRegDefList0,
380 kRegDefList1,
381 kRegDefList2,
382 kRegDefLR,
383 kRegDefSP,
384 kRegUse0,
385 kRegUse1,
386 kRegUse2,
387 kRegUse3,
388 kRegUse4,
389 kRegUseA,
390 kRegUseC,
391 kRegUseD,
Vladimir Marko70b797d2013-12-03 15:25:24 +0000392 kRegUseB,
buzbee02031b12012-11-23 09:41:35 -0800393 kRegUseFPCSList0,
394 kRegUseFPCSList2,
395 kRegUseList0,
396 kRegUseList1,
397 kRegUseLR,
398 kRegUsePC,
399 kRegUseSP,
400 kSetsCCodes,
Serguei Katkove90501d2014-03-12 15:56:54 +0700401 kUsesCCodes,
buzbee9da5c102014-03-28 12:59:18 -0700402 kUseFpStack,
403 kUseHi,
404 kUseLo,
405 kDefHi,
406 kDefLo
buzbee02031b12012-11-23 09:41:35 -0800407};
408
buzbeef662a7c2013-02-12 16:19:43 -0800409enum SelectInstructionKind {
410 kSelectNone,
411 kSelectConst,
412 kSelectMove,
413 kSelectGoto
414};
415
buzbeea5abf702013-04-12 14:39:29 -0700416std::ostream& operator<<(std::ostream& os, const SelectInstructionKind& kind);
417
buzbeeb48819d2013-09-14 16:15:25 -0700418// LIR fixup kinds for Arm
419enum FixupKind {
420 kFixupNone,
421 kFixupLabel, // For labels we just adjust the offset.
Vladimir Marko306f0172014-01-07 18:21:20 +0000422 kFixupLoad, // Mostly for immediates.
buzbeeb48819d2013-09-14 16:15:25 -0700423 kFixupVLoad, // FP load which *may* be pc-relative.
424 kFixupCBxZ, // Cbz, Cbnz.
425 kFixupPushPop, // Not really pc relative, but changes size based on args.
426 kFixupCondBranch, // Conditional branch
427 kFixupT1Branch, // Thumb1 Unconditional branch
428 kFixupT2Branch, // Thumb2 Unconditional branch
429 kFixupBlx1, // Blx1 (start of Blx1/Blx2 pair).
430 kFixupBl1, // Bl1 (start of Bl1/Bl2 pair).
431 kFixupAdr, // Adr.
432 kFixupMovImmLST, // kThumb2MovImm16LST.
433 kFixupMovImmHST, // kThumb2MovImm16HST.
434 kFixupAlign4, // Align to 4-byte boundary.
435};
436
437std::ostream& operator<<(std::ostream& os, const FixupKind& kind);
438
buzbeecbd6d442012-11-17 14:11:25 -0800439} // namespace art
440
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700441#endif // ART_COMPILER_DEX_COMPILER_ENUMS_H_