Blame - src/compiler/codegen/x86/Assemble.cc - platform_art

2012-03-05 19:51:02 -0800

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84

0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,

85

0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,

86

0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,

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0x80, 0x0 /* RegMem8/imm8 */,

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0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),

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89

ENCODING_MAP(Or,

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0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,

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0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,

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0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,

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0x80, 0x1 /* RegMem8/imm8 */,

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0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),

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95

ENCODING_MAP(Adc,

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0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,

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0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,

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0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,

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0x80, 0x2 /* RegMem8/imm8 */,

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0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),

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101

ENCODING_MAP(Sbb,

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0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,

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0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,

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0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,

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0x80, 0x3 /* RegMem8/imm8 */,

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0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),

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ENCODING_MAP(And,

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0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,

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0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,

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0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,

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0x80, 0x4 /* RegMem8/imm8 */,

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0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),

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ENCODING_MAP(Sub,

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0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,

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0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,

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0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,

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0x80, 0x5 /* RegMem8/imm8 */,

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0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),

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119

ENCODING_MAP(Xor,

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0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,

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0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,

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0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,

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0x80, 0x6 /* RegMem8/imm8 */,

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0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),

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ENCODING_MAP(Cmp,

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0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,

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0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,

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0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,

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0x80, 0x7 /* RegMem8/imm8 */,

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0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),

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#undef ENCODING_MAP

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133

{ kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "" },

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{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "" },

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{ kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "" },

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{ kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RRI", "" },

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{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RMI", "" },

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{ kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RAI", "" },

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{ kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "" },

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{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "" },

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{ kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "" },

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{ kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },

145

{ kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },

146

{ kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },

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{ kX86Mov8RR, kRegReg, IS_BINARY_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },

148

{ kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },

149

{ kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },

150

{ kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },

151

{ kX86Mov8RI, kMovRegImm, IS_BINARY_OP, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },

152

{ kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2r" },

153

{ kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },

154

{ kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },

155

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{ kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },

157

{ kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },

158

{ kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },

159

{ kX86Mov16RR, kRegReg, IS_BINARY_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },

160

{ kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },

161

{ kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },

162

{ kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },

163

{ kX86Mov16RI, kMovRegImm, IS_BINARY_OP, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },

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{ kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2r" },

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{ kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },

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{ kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },

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{ kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },

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{ kX86Mov32RR, kRegReg, IS_BINARY_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },

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{ kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },

173

{ kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },

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{ kX86Mov32RI, kMovRegImm, IS_BINARY_OP, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },

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{ kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2r" },

177

{ kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },

179

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{ kX86Lea32RA, kRegArray, IS_QUIN_OP, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

184

{ kX86 ## opname ## 8MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "" }, \

187

{ kX86 ## opname ## 8MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "" }, \

188

{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "" }, \

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\

190

{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

191

{ kX86 ## opname ## 16MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2r" }, \

192

{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

193

{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "" }, \

194

{ kX86 ## opname ## 16MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "" }, \

195

{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "" }, \

196

\

197

{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

198

{ kX86 ## opname ## 32MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2r" }, \

199

{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

200

{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32RC", "" }, \

201

{ kX86 ## opname ## 32MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32MC", "" }, \

202

{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32AC", "" }

203

204

SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

207

SHIFT_ENCODING_MAP(Rcr, 0x3),

208

SHIFT_ENCODING_MAP(Sal, 0x4),

209

SHIFT_ENCODING_MAP(Shl, 0x5),

210

SHIFT_ENCODING_MAP(Shr, 0x6),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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#define UNARY_ENCODING_MAP(opname, modrm, \

215

reg, reg_kind, reg_flags, \

216

mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, "" }, \

219

{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | mem_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, "" }, \

220

{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | arr_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, "" }, \

221

{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, "" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | mem_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, "" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | arr_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, "" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, "" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | mem_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, "" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | arr_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, "" }

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UNARY_ENCODING_MAP(Test, 0x0, RI, kRegImm, IS_BINARY_OP, MI, kMemImm, IS_TERTIARY_OP, AI, kArrayImm, IS_QUIN_OP, 1),

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UNARY_ENCODING_MAP(Not, 0x2, R, kReg, IS_UNARY_OP, M, kMem, IS_BINARY_OP, A, kArray, IS_QUAD_OP, 0),

230

UNARY_ENCODING_MAP(Neg, 0x3, R, kReg, IS_UNARY_OP, M, kMem, IS_BINARY_OP, A, kArray, IS_QUAD_OP, 0),

231

UNARY_ENCODING_MAP(Mul, 0x4, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

232

UNARY_ENCODING_MAP(Imul, 0x5, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

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UNARY_ENCODING_MAP(Divmod, 0x6, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

234

UNARY_ENCODING_MAP(Idivmod, 0x7, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

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#undef UNARY_ENCODING_MAP

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

245

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

248

{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

249

250

EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A),

251

EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A),

252

EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C),

253

EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C),

254

EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D),

255

EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D),

256

EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E),

257

EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E),

258

EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F),

259

EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F),

260

EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58),

261

EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58),

262

EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59),

263

EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59),

264

EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF2, 0x5A),

265

EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF3, 0x5A),

266

EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C),

267

EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C),

268

EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E),

269

EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E),

270

271

EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E),

272

EXT_0F_ENCODING_MAP(Movdrx, 0x66, 0x7E),

273

274

{ kX86Set8R, kRegCond, IS_BINARY_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

275

{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

276

{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

277

278

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF),

279

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF),

280

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6),

281

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7),

282

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE),

283

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF),

284

#undef EXT_0F_ENCODING_MAP

285

286

{ kX86Jcc, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc", "!1c" },

287

{ kX86Jmp, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp", "" },

288

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "" },

289

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "" },

290

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "" },

291

{ kX86Ret, kNullary,NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

292

};

293

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

294

static size_t computeSize(X86EncodingMap* entry, int displacement, bool has_sib) {

295

size_t size = 0;

296

if (entry->skeleton.prefix1 > 0) {

297

++size;

298

if (entry->skeleton.prefix2 > 0) {

299

++size;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

300

}

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

301

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

302

++size; // opcode

303

if (entry->skeleton.opcode == 0x0F) {

304

++size;

305

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib) {

++size;

}

if (displacement != 0) {

314

if (entry->opcode != kX86Lea32RA) {

315

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0);

316

}

317

size += IS_SIMM8(displacement) ? 1 : 4;

318

}

319

size += entry->skeleton.immediate_bytes;

return size;

}

int oatGetInsnSize(LIR* lir) {

324

X86EncodingMap* entry = &EncodingMap[lir->opcode];

325

switch (entry->kind) {

326

case kData:

327

return 4; // 4 bytes of data

328

case kNop:

329

return lir->operands[0]; // length of nop is sole operand

330

case kNullary:

331

return 1; // 1 byte of opcode

332

case kReg: // lir operands - 0: reg

333

return computeSize(entry, 0, false);

334

case kMem: { // lir operands - 0: base, 1: disp

335

int base = lir->operands[0];

336

// SP requires a special extra SIB byte

337

return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0);

338

}

339

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

340

return computeSize(entry, lir->operands[3], true);

341

case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg

342

int base = lir->operands[0];

343

// SP requires a special extra SIB byte

344

return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0);

345

}

346

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

347

return computeSize(entry, lir->operands[3], true);

348

case kThreadReg: // lir operands - 0: disp, 1: reg

349

return computeSize(entry, lir->operands[0], false);

350

case kRegReg:

351

return computeSize(entry, 0, false);

352

case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp

353

int base = lir->operands[1];

354

return computeSize(entry, lir->operands[2], false) + (base == rSP ? 1 : 0);

355

}

356

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

357

return computeSize(entry, lir->operands[4], true);

358

case kRegThread: // lir operands - 0: reg, 1: disp

359

return computeSize(entry, lir->operands[1], false);

360

case kRegImm: { // lir operands - 0: reg, 1: immediate

361

int reg = lir->operands[0];

362

// AX opcodes don't require the modrm byte.

363

return computeSize(entry, 0, false) - (reg == rAX ? 1 : 0);

364

}

365

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

366

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

367

return computeSize(entry, lir->operands[1], false);

368

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

369

return computeSize(entry, lir->operands[3], true);

370

case kThreadImm: // lir operands - 0: disp, 1: imm

371

return computeSize(entry, lir->operands[0], false);

372

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

373

return computeSize(entry, 0, false);

374

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

375

CHECK_NE(lir->operands[1], static_cast<int>(rSP)); // TODO: add extra SIB byte

376

return computeSize(entry, lir->operands[2], false);

377

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

378

return computeSize(entry, lir->operands[4], true);

379

case kMovRegImm: // lir operands - 0: reg, 1: immediate

380

return 1 + entry->skeleton.immediate_bytes;

381

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

382

// Shift by immediate one has a shorter opcode.

383

return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

384

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

385

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

386

// Shift by immediate one has a shorter opcode.

387

return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);

388

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

389

// Shift by immediate one has a shorter opcode.

390

return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0);

391

case kShiftRegCl:

392

return computeSize(entry, 0, false);

393

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

394

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

395

return computeSize(entry, lir->operands[1], false);

396

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

397

return computeSize(entry, lir->operands[3], true);

398

case kRegCond: // lir operands - 0: reg, 1: cond

399

return computeSize(entry, 0, false);

400

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

401

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

402

return computeSize(entry, lir->operands[1], false);

403

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

404

return computeSize(entry, lir->operands[3], true);

405

case kJcc: case kJmp:

406

// Jumps only return the short form length, the correct length will be assigned to LIR

407

// flags.size during assembly.

408

return 2;

409

case kCall:

410

switch(lir->opcode) {

411

case kX86CallR: return 2; // opcode modrm

412

case kX86CallM: // lir operands - 0: base, 1: disp

413

return computeSize(entry, lir->operands[1], false);

414

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

415

return computeSize(entry, lir->operands[3], true);

default:

break;

}

break;

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

424

return 0;

425

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

426

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

427

static uint8_t modrmForDisp(int disp) {

428

if (disp == 0) {

429

return 0;

430

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

static void emitDisp(CompilationUnit* cUnit, int disp) {

438

if (disp == 0) {

439

return;

440

} else if (IS_SIMM8(disp)) {

441

cUnit->codeBuffer.push_back(disp & 0xFF);

442

} else {

443

cUnit->codeBuffer.push_back(disp & 0xFF);

444

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

445

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

446

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

}

}

static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) {

451

if (entry->skeleton.prefix1 != 0) {

452

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

453

if (entry->skeleton.prefix2 != 0) {

454

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

455

}

456

} else {

457

DCHECK_EQ(0, entry->skeleton.prefix2);

458

}

459

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

460

if (entry->skeleton.opcode == 0x0F) {

461

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

462

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

463

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

464

} else {

465

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

466

}

467

} else {

468

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

469

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

470

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame^]

471

if (FPREG(reg)) {

472

reg = reg & FP_REG_MASK;

473

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

474

DCHECK_LT(reg, 8);

475

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

476

cUnit->codeBuffer.push_back(modrm);

477

DCHECK_EQ(0, entry->skeleton.ax_opcode);

478

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

479

}

480

481

static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) {

482

if (entry->skeleton.prefix1 != 0) {

483

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

484

if (entry->skeleton.prefix2 != 0) {

485

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

486

}

487

} else {

488

DCHECK_EQ(0, entry->skeleton.prefix2);

489

}

490

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

491

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

492

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

493

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

494

DCHECK_LT(base, 8);

495

uint8_t modrm = (modrmForDisp(disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

496

cUnit->codeBuffer.push_back(modrm);

497

emitDisp(cUnit, disp);

498

DCHECK_EQ(0, entry->skeleton.ax_opcode);

499

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

500

}

501

502

static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

503

uint8_t base, int disp, uint8_t reg) {

504

if (entry->skeleton.prefix1 != 0) {

505

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

506

if (entry->skeleton.prefix2 != 0) {

507

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

508

}

509

} else {

510

DCHECK_EQ(0, entry->skeleton.prefix2);

511

}

512

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

513

if (entry->skeleton.opcode == 0x0F) {

514

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

515

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

516

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

517

} else {

518

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

519

}

520

} else {

521

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

522

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

523

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame^]

524

if (FPREG(reg)) {

525

reg = reg & FP_REG_MASK;

526

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

527

DCHECK_LT(reg, 8);

528

DCHECK_LT(base, 8);

529

uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | base;

530

cUnit->codeBuffer.push_back(modrm);

531

if (base == rSP) {

532

// Special SIB for SP base

533

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

534

}

535

emitDisp(cUnit, disp);

536

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

537

DCHECK_EQ(0, entry->skeleton.ax_opcode);

538

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

539

}

540

541

static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

542

uint8_t reg, uint8_t base, int disp) {

543

// Opcode will flip operands.

544

emitMemReg(cUnit, entry, base, disp, reg);

545

}

546

547

static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

548

uint8_t base, uint8_t index, int scale, int disp) {

549

if (entry->skeleton.prefix1 != 0) {

550

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

551

if (entry->skeleton.prefix2 != 0) {

552

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

553

}

554

} else {

555

DCHECK_EQ(0, entry->skeleton.prefix2);

556

}

557

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

558

if (entry->skeleton.opcode == 0x0F) {

559

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

560

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

561

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

562

} else {

563

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

564

}

565

} else {

566

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

567

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

568

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame^]

569

if (FPREG(reg)) {

570

reg = reg & FP_REG_MASK;

571

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

572

DCHECK_LT(reg, 8);

573

uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | rSP;

574

cUnit->codeBuffer.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

579

cUnit->codeBuffer.push_back(sib);

580

emitDisp(cUnit, disp);

581

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

582

DCHECK_EQ(0, entry->skeleton.ax_opcode);

583

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

584

}

585

586

static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

587

uint8_t reg1, uint8_t reg2) {

588

if (entry->skeleton.prefix1 != 0) {

589

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

590

if (entry->skeleton.prefix2 != 0) {

591

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

592

}

593

} else {

594

DCHECK_EQ(0, entry->skeleton.prefix2);

595

}

596

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

597

if (entry->skeleton.opcode == 0x0F) {

598

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

599

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

600

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

601

} else {

602

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

603

}

604

} else {

605

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

606

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

607

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame^]

608

if (FPREG(reg1)) {

609

reg1 = reg1 & FP_REG_MASK;

610

}

611

if (FPREG(reg2)) {

612

reg2 = reg2 & FP_REG_MASK;

613

}

614

DCHECK_LT(reg1, 8);

615

DCHECK_LT(reg2, 8);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

616

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

617

cUnit->codeBuffer.push_back(modrm);

618

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

619

DCHECK_EQ(0, entry->skeleton.ax_opcode);

620

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

621

}

622

623

static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

624

uint8_t reg, int imm) {

625

if (entry->skeleton.prefix1 != 0) {

626

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

627

if (entry->skeleton.prefix2 != 0) {

628

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

629

}

630

} else {

631

DCHECK_EQ(0, entry->skeleton.prefix2);

632

}

633

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

634

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

635

} else {

636

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

637

if (entry->skeleton.opcode == 0x0F) {

638

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

639

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

640

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

641

} else {

642

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

643

}

644

} else {

645

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

646

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

647

}

648

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

649

cUnit->codeBuffer.push_back(modrm);

650

}

651

switch (entry->skeleton.immediate_bytes) {

652

case 1:

653

DCHECK(IS_SIMM8(imm));

654

cUnit->codeBuffer.push_back(imm & 0xFF);

655

break;

656

case 2:

657

DCHECK(IS_SIMM16(imm));

658

cUnit->codeBuffer.push_back(imm & 0xFF);

659

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

660

break;

661

case 4:

662

cUnit->codeBuffer.push_back(imm & 0xFF);

663

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

664

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

665

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

666

break;

667

default:

668

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

669

<< ") for instruction: " << entry->name;

break;

}

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

674

/*

675

* Assemble the LIR into binary instruction format. Note that we may

676

* discover that pc-relative displacements may not fit the selected

677

* instruction. In those cases we will try to substitute a new code

678

* sequence or request that the trace be shortened and retried.

679

*/

680

AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit,

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

681

intptr_t startAddr) {

682

LIR *lir;

683

AssemblerStatus res = kSuccess; // Assume success

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

684

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

685

for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {

686

if (lir->opcode < 0) {

687

continue;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

688

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

689

690

691

if (lir->flags.isNop) {

continue;

}

if (lir->flags.pcRelFixup) {

696

UNIMPLEMENTED(WARNING) << "PC relative fix up";

}

/*

* If one of the pc-relative instructions expanded we'll have

701

* to make another pass. Don't bother to fully assemble the

702

* instruction.

703

*/

704

if (res != kSuccess) {

705

continue;

706

}

707

const X86EncodingMap *entry = &EncodingMap[lir->opcode];

708

switch(entry->kind) {

709

case kData: // 4 bytes of data

710

cUnit->codeBuffer.push_back(lir->operands[0]);

711

break;

712

case kNullary: // 1 byte of opcode

713

DCHECK_EQ(0, entry->skeleton.prefix1);

714

DCHECK_EQ(0, entry->skeleton.prefix2);

715

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

716

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

717

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

718

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

719

DCHECK_EQ(0, entry->skeleton.ax_opcode);

720

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

721

break;

722

case kReg: // lir operands - 0: reg

723

emitOpReg(cUnit, entry, lir->operands[0]);

724

break;

725

case kMem: // lir operands - 0: base, 1: disp

726

emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]);

727

break;

728

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

729

emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

730

break;

731

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

732

emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

733

break;

734

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

735

emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

736

lir->operands[3], lir->operands[4]);

737

break;

738

case kRegReg: // lir operands - 0: reg1, 1: reg2

739

emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);

740

break;

741

case kRegImm: // lir operands - 0: reg, 1: immediate

742

emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

743

break;

744

default:

745

UNIMPLEMENTED(FATAL) << "Unimplemented encoding for: " << entry->name;

break;

}

}

return res;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

750

}

751

buzbee