Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through.
Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
diff --git a/libc/kernel/arch-arm/asm/arch/fpga.h b/libc/kernel/arch-arm/asm/arch/fpga.h
index 64055a4..8439a80 100644
--- a/libc/kernel/arch-arm/asm/arch/fpga.h
+++ b/libc/kernel/arch-arm/asm/arch/fpga.h
@@ -22,19 +22,19 @@
#define fpga_read(reg) __raw_readb(reg)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fpga_write(val, reg) __raw_writeb(val, reg)
-#define H2P2_DBG_FPGA_BASE 0xE8000000
-#define H2P2_DBG_FPGA_SIZE SZ_4K
-#define H2P2_DBG_FPGA_START 0x04000000
+#define H2P2_DBG_FPGA_BASE 0xE8000000
+#define H2P2_DBG_FPGA_SIZE SZ_4K
+#define H2P2_DBG_FPGA_START 0x04000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)
-#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)
-#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)
+#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)
+#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)
+#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)
-#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)
-#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)
-#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)
+#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)
+#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)
+#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)
+#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct h2p2_dbg_fpga {
u16 smc91x[8];
@@ -57,16 +57,16 @@
#define H2P2_DBG_FPGA_LED_RED (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
-#define H2P2_DBG_FPGA_LOAD_METER (1 << 0)
+#define H2P2_DBG_FPGA_LOAD_METER (1 << 0)
#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
-#define OMAP1510_FPGA_BASE 0xE8000000
+#define OMAP1510_FPGA_BASE 0xE8000000
#define OMAP1510_FPGA_SIZE SZ_4K
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP1510_FPGA_START 0x08000000
+#define OMAP1510_FPGA_START 0x08000000
#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
@@ -122,16 +122,16 @@
#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
-#define OMAP1510_FPGA_HID_SCLK (1<<0)
-#define OMAP1510_FPGA_HID_MOSI (1<<1)
-#define OMAP1510_FPGA_HID_nSS (1<<2)
+#define OMAP1510_FPGA_HID_SCLK (1<<0)
+#define OMAP1510_FPGA_HID_MOSI (1<<1)
+#define OMAP1510_FPGA_HID_nSS (1<<2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP1510_FPGA_HID_nHSUS (1<<3)
-#define OMAP1510_FPGA_HID_MISO (1<<4)
-#define OMAP1510_FPGA_HID_ATN (1<<5)
+#define OMAP1510_FPGA_HID_nHSUS (1<<3)
+#define OMAP1510_FPGA_HID_MISO (1<<4)
+#define OMAP1510_FPGA_HID_ATN (1<<5)
#define OMAP1510_FPGA_HID_rsrvd (1<<6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP1510_FPGA_HID_RESETn (1<<7)
+#define OMAP1510_FPGA_HID_RESETn (1<<7)
#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE
#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0)