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review.blissroms.org / platform_bionic / 03e1ebbdd638c6974267c6248935fdf59a4429ea / . / libc / kernel / common / linux / msm_mdp.h
blob: b64eb7600665003a70ea8e24a8c9da35c967cbb8 [file] [log] [blame]
The Android Open Source Project1dc9e472009-03-03 19:28:35 -0800[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame]10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
The Android Open Source Project1dc9e472009-03-03 19:28:35 -0800[diff] [blame]17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _MSM_MDP_H_
20#define _MSM_MDP_H_
The Android Open Source Project1dc9e472009-03-03 19:28:35 -0800[diff] [blame]21#include <linux/types.h>
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]22#include <linux/fb.h>
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]24#define MSMFB_IOCTL_MAGIC 'm'
The Android Open Source Project1dc9e472009-03-03 19:28:35 -0800[diff] [blame]25#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
26#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]27#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]29#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
30#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
31#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
32#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
35#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
36#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay)
37#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data)
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]40#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]41#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection)
42#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]44#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]45#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
46#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt)
47#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]49#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]50#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
51#define MSMFB_NOTIFY_UPDATE _IOW(MSMFB_IOCTL_MAGIC, 146, unsigned int)
52#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]54#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]55#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data)
56#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
57#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]59#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]60#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data)
61#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data)
62#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]64#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
65#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]66#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]67#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]69#define MSMFB_OVERLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 163, unsigned int)
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]70#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit)
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]71#define FB_TYPE_3D_PANEL 0x10101010
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]72#define MDP_IMGTYPE2_START 0x10000
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]74#define MSMFB_DRIVER_VERSION 0xF9E8D701
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]75enum {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]76 NOTIFY_UPDATE_START,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]77 NOTIFY_UPDATE_STOP,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]79};
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]80enum {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]81 MDP_RGB_565,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]82 MDP_XRGB_8888,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]84 MDP_Y_CBCR_H2V2,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]85 MDP_Y_CBCR_H2V2_ADRENO,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]86 MDP_ARGB_8888,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]87 MDP_RGB_888,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]89 MDP_Y_CRCB_H2V2,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]90 MDP_YCRYCB_H2V1,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]91 MDP_Y_CRCB_H2V1,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]92 MDP_Y_CBCR_H2V1,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]94 MDP_Y_CRCB_H1V2,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]95 MDP_Y_CBCR_H1V2,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]96 MDP_RGBA_8888,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]97 MDP_BGRA_8888,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]99 MDP_RGBX_8888,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]100 MDP_Y_CRCB_H2V2_TILE,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]101 MDP_Y_CBCR_H2V2_TILE,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]102 MDP_Y_CR_CB_H2V2,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]104 MDP_Y_CR_CB_GH2V2,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]105 MDP_Y_CB_CR_H2V2,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]106 MDP_Y_CRCB_H1V1,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]107 MDP_Y_CBCR_H1V1,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]109 MDP_YCRCB_H1V1,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]110 MDP_YCBCR_H1V1,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]111 MDP_BGR_565,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]112 MDP_IMGTYPE_LIMIT,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]114 MDP_RGB_BORDERFILL,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]115 MDP_FB_FORMAT = MDP_IMGTYPE2_START,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]116 MDP_IMGTYPE_LIMIT2
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]117};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]119enum {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]120 PMEM_IMG,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]121 FB_IMG,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]122};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]124enum {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]125 HSIC_HUE = 0,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]126 HSIC_SAT,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]127 HSIC_INT,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]129 HSIC_CON,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]130 NUM_HSIC_PARAM,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]131};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]132#define MDSS_MDP_ROT_ONLY 0x80
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]134#define MDSS_MDP_RIGHT_MIXER 0x100
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]135#define MDP_ROT_NOP 0
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]136#define MDP_FLIP_LR 0x1
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]137#define MDP_FLIP_UD 0x2
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]139#define MDP_ROT_90 0x4
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]140#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]141#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]142#define MDP_DITHER 0x8
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]144#define MDP_BLUR 0x10
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]145#define MDP_BLEND_FG_PREMULT 0x20000
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]146#define MDP_DEINTERLACE 0x80000000
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]147#define MDP_SHARPENING 0x40000000
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]149#define MDP_NO_DMA_BARRIER_START 0x20000000
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]150#define MDP_NO_DMA_BARRIER_END 0x10000000
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]151#define MDP_NO_BLIT 0x08000000
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]152#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]154#define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]155#define MDP_BLIT_SRC_GEM 0x04000000
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]156#define MDP_BLIT_DST_GEM 0x02000000
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]157#define MDP_BLIT_NON_CACHED 0x01000000
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]159#define MDP_OV_PIPE_SHARE 0x00800000
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]160#define MDP_DEINTERLACE_ODD 0x00400000
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]161#define MDP_OV_PLAY_NOWAIT 0x00200000
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]162#define MDP_SOURCE_ROTATED_90 0x00100000
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]164#define MDP_OVERLAY_PP_CFG_EN 0x00080000
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]165#define MDP_BACKEND_COMPOSITION 0x00040000
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]166#define MDP_BORDERFILL_SUPPORTED 0x00010000
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]167#define MDP_SECURE_OVERLAY_SESSION 0x00008000
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]169#define MDP_MEMORY_ID_TYPE_FB 0x00001000
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]170#define MDP_TRANSP_NOP 0xffffffff
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]171#define MDP_ALPHA_NOP 0xff
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]172#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]174#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]175#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]176#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]177#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]179#define MDP_FB_PAGE_PROTECTION_INVALID (5)
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]180#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]181struct mdp_rect {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]182 uint32_t x;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]184 uint32_t y;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]185 uint32_t w;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]186 uint32_t h;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]187};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]189struct mdp_img {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]190 uint32_t width;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]191 uint32_t height;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]192 uint32_t format;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]194 uint32_t offset;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]195 int memory_id;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]196 uint32_t priv;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]197};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]199#define MDP_CCS_RGB2YUV 0
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]200#define MDP_CCS_YUV2RGB 1
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]201#define MDP_CCS_SIZE 9
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]202#define MDP_BV_SIZE 3
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]204struct mdp_ccs {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]205 int direction;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]206 uint16_t ccs[MDP_CCS_SIZE];
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]207 uint16_t bv[MDP_BV_SIZE];
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]209};
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]210struct mdp_csc {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]211 int id;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]212 uint32_t csc_mv[9];
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]214 uint32_t csc_pre_bv[3];
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]215 uint32_t csc_post_bv[3];
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]216 uint32_t csc_pre_lv[6];
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]217 uint32_t csc_post_lv[6];
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]219};
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]220#define MDP_BLIT_REQ_VERSION 2
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]221struct mdp_blit_req {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]222 struct mdp_img src;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]224 struct mdp_img dst;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]225 struct mdp_rect src_rect;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]226 struct mdp_rect dst_rect;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]227 uint32_t alpha;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]229 uint32_t transp_mask;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]230 uint32_t flags;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]231 int sharpening_strength;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]232};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]234struct mdp_blit_req_list {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]235 uint32_t count;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]236 struct mdp_blit_req req[];
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]237};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]239#define MSMFB_DATA_VERSION 2
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]240struct msmfb_data {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]241 uint32_t offset;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]242 int memory_id;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]244 int id;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]245 uint32_t flags;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]246 uint32_t priv;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]247 uint32_t iova;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]249};
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]250#define MSMFB_NEW_REQUEST -1
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]251struct msmfb_overlay_data {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]252 uint32_t id;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]254 struct msmfb_data data;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]255 uint32_t version_key;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]256 struct msmfb_data plane1_data;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]257 struct msmfb_data plane2_data;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]259 struct msmfb_data dst_data;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]260};
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]261struct msmfb_img {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]262 uint32_t width;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]264 uint32_t height;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]265 uint32_t format;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]266};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]267#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]269struct msmfb_writeback_data {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]270 struct msmfb_data buf_info;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]271 struct msmfb_img img;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]272};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]274#define MDP_PP_OPS_READ 0x2
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]275#define MDP_PP_OPS_WRITE 0x4
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]276struct mdp_qseed_cfg {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]277 uint32_t table_num;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]279 uint32_t ops;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]280 uint32_t len;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]281 uint32_t *data;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]282};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]284struct mdp_qseed_cfg_data {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]285 uint32_t block;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]286 struct mdp_qseed_cfg qseed_data;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]287};
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]289#define MDP_OVERLAY_PP_CSC_CFG 0x1
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]290#define MDP_OVERLAY_PP_QSEED_CFG 0x2
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]291#define MDP_CSC_FLAG_ENABLE 0x1
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]292#define MDP_CSC_FLAG_YUV_IN 0x2
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]294#define MDP_CSC_FLAG_YUV_OUT 0x4
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]295struct mdp_csc_cfg {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]296 uint32_t flags;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]297 uint32_t csc_mv[9];
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]299 uint32_t csc_pre_bv[3];
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]300 uint32_t csc_post_bv[3];
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]301 uint32_t csc_pre_lv[6];
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]302 uint32_t csc_post_lv[6];
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]304};
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]305struct mdp_csc_cfg_data {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]306 uint32_t block;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]307 struct mdp_csc_cfg csc_data;
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]309};
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]310struct mdp_overlay_pp_params {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]311 uint32_t config_ops;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]312 struct mdp_csc_cfg csc_cfg;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]314 struct mdp_qseed_cfg qseed_cfg[2];
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]315};
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]316struct mdp_overlay {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]317 struct msmfb_img src;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]319 struct mdp_rect src_rect;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]320 struct mdp_rect dst_rect;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]321 uint32_t z_order;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]322 uint32_t is_fg;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]324 uint32_t alpha;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]325 uint32_t transp_mask;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]326 uint32_t flags;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]327 uint32_t id;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]329 uint32_t user_data[8];
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]330 struct mdp_overlay_pp_params overlay_pp_cfg;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]331};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]332struct msmfb_overlay_3d {
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]334 uint32_t is_3d;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]335 uint32_t width;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]336 uint32_t height;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]337};
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]339struct msmfb_overlay_blt {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]340 uint32_t enable;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]341 uint32_t offset;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]342 uint32_t width;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]344 uint32_t height;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]345 uint32_t bpp;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]346};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]347struct mdp_histogram {
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]349 uint32_t frame_cnt;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]350 uint32_t bin_cnt;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]351 uint32_t *r;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]352 uint32_t *g;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]354 uint32_t *b;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]355};
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]356enum {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]357 MDP_BLOCK_RESERVED = 0,
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]359 MDP_BLOCK_OVERLAY_0,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]360 MDP_BLOCK_OVERLAY_1,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]361 MDP_BLOCK_VG_1,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]362 MDP_BLOCK_VG_2,
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]364 MDP_BLOCK_RGB_1,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]365 MDP_BLOCK_RGB_2,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]366 MDP_BLOCK_DMA_P,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]367 MDP_BLOCK_DMA_S,
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]369 MDP_BLOCK_DMA_E,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]370 MDP_BLOCK_OVERLAY_2,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]371 MDP_BLOCK_MAX,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]372};
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]374struct mdp_histogram_start_req {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]375 uint32_t block;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]376 uint8_t frame_cnt;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]377 uint8_t bit_mask;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]379 uint8_t num_bins;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]380};
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]381struct mdp_histogram_data {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]382 uint32_t block;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]384 uint8_t bin_cnt;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]385 uint32_t *c0;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]386 uint32_t *c1;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]387 uint32_t *c2;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]389 uint32_t *extra_info;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]390};
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]391struct mdp_pcc_coeff {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]392 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]394};
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]395struct mdp_pcc_cfg_data {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]396 uint32_t block;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]397 uint32_t ops;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]399 struct mdp_pcc_coeff r, g, b;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]400};
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]401enum {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]402 mdp_lut_igc,
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]404 mdp_lut_pgc,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]405 mdp_lut_hist,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]406 mdp_lut_max,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]407};
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]409struct mdp_igc_lut_data {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]410 uint32_t block;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]411 uint32_t len, ops;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]412 uint32_t *c0_c1_data;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]414 uint32_t *c2_data;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]415};
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]416struct mdp_ar_gc_lut_data {
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]417 uint32_t x_start;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]419 uint32_t slope;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]420 uint32_t offset;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]421};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]422struct mdp_pgc_lut_data {
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]424 uint32_t block;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]425 uint32_t flags;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]426 uint8_t num_r_stages;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]427 uint8_t num_g_stages;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]429 uint8_t num_b_stages;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]430 struct mdp_ar_gc_lut_data *r_data;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]431 struct mdp_ar_gc_lut_data *g_data;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]432 struct mdp_ar_gc_lut_data *b_data;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]434};
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]435struct mdp_hist_lut_data {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]436 uint32_t block;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]437 uint32_t ops;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]439 uint32_t len;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]440 uint32_t *data;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]441};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]442struct mdp_lut_cfg_data {
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]444 uint32_t lut_type;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]445 union {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]446 struct mdp_igc_lut_data igc_lut_data;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]447 struct mdp_pgc_lut_data pgc_lut_data;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]449 struct mdp_hist_lut_data hist_lut_data;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]450 } data;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]451};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]452struct mdp_bl_scale_data {
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]454 uint32_t min_lvl;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]455 uint32_t scale;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]456};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]457enum {
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]459 mdp_op_pcc_cfg,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]460 mdp_op_csc_cfg,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]461 mdp_op_lut_cfg,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]462 mdp_op_qseed_cfg,
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]464 mdp_bl_scale_cfg,
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]465 mdp_op_max,
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]466};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]467struct msmfb_mdp_pp {
Naseer Ahmed056b4bc2012-07-31 17:26:00 -0700[diff] [blame]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]469 uint32_t op;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]470 union {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]471 struct mdp_pcc_cfg_data pcc_cfg_data;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]472 struct mdp_csc_cfg_data csc_cfg_data;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]474 struct mdp_lut_cfg_data lut_cfg_data;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]475 struct mdp_qseed_cfg_data qseed_cfg_data;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]476 struct mdp_bl_scale_data bl_scale_data;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]477 } data;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]479};
480#define MDP_MAX_FENCE_FD 10
481#define MDP_BUF_SYNC_FLAG_WAIT 1
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]482struct mdp_buf_sync {
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
484 uint32_t flags;
485 uint32_t acq_fen_fd_cnt;
486 int *acq_fen_fd;
487 int *rel_fen_fd;
488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
489};
490struct mdp_buf_fence {
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]491 uint32_t flags;
492 uint32_t acq_fen_fd_cnt;
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]494 int acq_fen_fd[MDP_MAX_FENCE_FD];
495 int rel_fen_fd[MDP_MAX_FENCE_FD];
496};
497struct mdp_display_commit {
498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
499 uint32_t flags;
500 uint32_t wait_for_finish;
501 struct fb_var_screeninfo var;
502 struct mdp_buf_fence buf_fence;
503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmedf7070072012-09-17 18:44:07 -0400[diff] [blame]504};
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]505struct mdp_page_protection {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]506 uint32_t page_protection;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]507};
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed05ad6172012-06-28 17:45:11 -0700[diff] [blame]509struct mdp_mixer_info {
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]510 int pndx;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]511 int pnum;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]512 int ptype;
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed05ad6172012-06-28 17:45:11 -0700[diff] [blame]514 int mixer_num;
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]515 int z_order;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]516};
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]517#define MAX_PIPE_PER_MIXER 4
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed05ad6172012-06-28 17:45:11 -0700[diff] [blame]519struct msmfb_mixer_info_req {
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]520 int mixer_num;
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]521 int cnt;
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]522 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed05ad6172012-06-28 17:45:11 -0700[diff] [blame]524};
Naseer Ahmed240b3342012-06-18 14:54:42 -0700[diff] [blame]525enum {
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]526 DISPLAY_SUBSYSTEM_ID,
Iliyan Malchev3ad36e52012-08-27 11:08:52 -0700[diff] [blame]527 ROTATOR_SUBSYSTEM_ID,
Naseer Ahmed3ef4fec2012-10-01 16:06:50 -0400[diff] [blame]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Naseer Ahmed05ad6172012-06-28 17:45:11 -0700[diff] [blame]529};
The Android Open Source Project1dc9e472009-03-03 19:28:35 -0800[diff] [blame]530#endif
Saurabh Shah204b26b2012-09-27 12:27:53 -0700[diff] [blame]531