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review.blissroms.org / platform_bionic / 198d13e8c25e69f7dbda3f5e1a3258b13fe8db5d / . / libc / kernel / uapi / drm / savage_drm.h
blob: db873b61d75d8e00320e2929670f1e03752774b7 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __SAVAGE_DRM_H__
20#define __SAVAGE_DRM_H__
21#ifndef __SAVAGE_SAREA_DEFINES__
22#define __SAVAGE_SAREA_DEFINES__
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define SAVAGE_CARD_HEAP 0
25#define SAVAGE_AGP_HEAP 1
26#define SAVAGE_NR_TEX_HEAPS 2
27#define SAVAGE_NR_TEX_REGIONS 16
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
30#endif
31typedef struct _drm_savage_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]32 struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + 1];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]34 unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
35 int ctxOwner;
36} drm_savage_sarea_t, * drm_savage_sarea_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]37#define DRM_SAVAGE_BCI_INIT 0x00
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define DRM_SAVAGE_BCI_CMDBUF 0x01
40#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
41#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]42#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]45#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]46#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]47#define SAVAGE_DMA_PCI 1
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49#define SAVAGE_DMA_AGP 3
50typedef struct drm_savage_init {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]51 enum {
52 SAVAGE_INIT_BCI = 1,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]54 SAVAGE_CLEANUP_BCI = 2
55 } func;
56 unsigned int sarea_priv_offset;
57 unsigned int cob_size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]59 unsigned int bci_threshold_lo, bci_threshold_hi;
60 unsigned int dma_type;
61 unsigned int fb_bpp;
62 unsigned int front_offset, front_pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]64 unsigned int back_offset, back_pitch;
65 unsigned int depth_bpp;
66 unsigned int depth_offset, depth_pitch;
67 unsigned int texture_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]69 unsigned int texture_size;
70 unsigned long status_offset;
71 unsigned long buffers_offset;
72 unsigned long agp_textures_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]74 unsigned long cmd_dma_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]75} drm_savage_init_t;
76typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]77typedef struct drm_savage_cmdbuf {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]79 drm_savage_cmd_header_t __user * cmd_addr;
80 unsigned int size;
81 unsigned int dma_idx;
82 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]84 unsigned int __user * vb_addr;
85 unsigned int vb_size;
86 unsigned int vb_stride;
87 struct drm_clip_rect __user * box_addr;
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89 unsigned int nbox;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]90} drm_savage_cmdbuf_t;
91#define SAVAGE_WAIT_2D 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]92#define SAVAGE_WAIT_3D 0x2
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94#define SAVAGE_WAIT_IRQ 0x4
95typedef struct drm_savage_event {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]96 unsigned int count;
97 unsigned int flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99} drm_savage_event_emit_t, drm_savage_event_wait_t;
100#define SAVAGE_CMD_STATE 0
101#define SAVAGE_CMD_DMA_PRIM 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]102#define SAVAGE_CMD_VB_PRIM 2
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104#define SAVAGE_CMD_DMA_IDX 3
105#define SAVAGE_CMD_VB_IDX 4
106#define SAVAGE_CMD_CLEAR 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]107#define SAVAGE_CMD_SWAP 6
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109#define SAVAGE_PRIM_TRILIST 0
110#define SAVAGE_PRIM_TRISTRIP 1
111#define SAVAGE_PRIM_TRIFAN 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]112#define SAVAGE_PRIM_TRILIST_201 3
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114#define SAVAGE_SKIP_Z 0x01
115#define SAVAGE_SKIP_W 0x02
116#define SAVAGE_SKIP_C0 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]117#define SAVAGE_SKIP_C1 0x08
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119#define SAVAGE_SKIP_S0 0x10
120#define SAVAGE_SKIP_T0 0x20
121#define SAVAGE_SKIP_ST0 0x30
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]122#define SAVAGE_SKIP_S1 0x40
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124#define SAVAGE_SKIP_T1 0x80
125#define SAVAGE_SKIP_ST1 0xc0
126#define SAVAGE_SKIP_ALL_S3D 0x3f
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]127#define SAVAGE_SKIP_ALL_S4 0xff
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define SAVAGE_FRONT 0x1
130#define SAVAGE_BACK 0x2
131#define SAVAGE_DEPTH 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]132union drm_savage_cmd_header {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]134 struct {
135 unsigned char cmd;
136 unsigned char pad0;
137 unsigned short pad1;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]139 unsigned short pad2;
140 unsigned short pad3;
141 } cmd;
142 struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]144 unsigned char cmd;
145 unsigned char global;
146 unsigned short count;
147 unsigned short start;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]149 unsigned short pad3;
150 } state;
151 struct {
152 unsigned char cmd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]154 unsigned char prim;
155 unsigned short skip;
156 unsigned short count;
157 unsigned short start;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]159 } prim;
160 struct {
161 unsigned char cmd;
162 unsigned char prim;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]164 unsigned short skip;
165 unsigned short count;
166 unsigned short pad3;
167 } idx;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]169 struct {
170 unsigned char cmd;
171 unsigned char pad0;
172 unsigned short pad1;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]174 unsigned int flags;
175 } clear0;
176 struct {
177 unsigned int mask;
178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
179 unsigned int value;
180 } clear1;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]181};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]182#endif
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */