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review.blissroms.org / platform_bionic / 198d13e8c25e69f7dbda3f5e1a3258b13fe8db5d / . / libc / kernel / uapi / linux / synclink.h
blob: ba5372f6dd4cf6e2d1b1d26f8aa95b4c4bdbcb85 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_SYNCLINK_H_
20#define _UAPI_SYNCLINK_H_
21#define SYNCLINK_H_VERSION 3.6
22#include <linux/types.h>
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define BIT0 0x0001
25#define BIT1 0x0002
26#define BIT2 0x0004
27#define BIT3 0x0008
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define BIT4 0x0010
30#define BIT5 0x0020
31#define BIT6 0x0040
32#define BIT7 0x0080
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define BIT8 0x0100
35#define BIT9 0x0200
36#define BIT10 0x0400
37#define BIT11 0x0800
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define BIT12 0x1000
40#define BIT13 0x2000
41#define BIT14 0x4000
42#define BIT15 0x8000
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define BIT16 0x00010000
45#define BIT17 0x00020000
46#define BIT18 0x00040000
47#define BIT19 0x00080000
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define BIT20 0x00100000
50#define BIT21 0x00200000
51#define BIT22 0x00400000
52#define BIT23 0x00800000
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define BIT24 0x01000000
55#define BIT25 0x02000000
56#define BIT26 0x04000000
57#define BIT27 0x08000000
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define BIT28 0x10000000
60#define BIT29 0x20000000
61#define BIT30 0x40000000
62#define BIT31 0x80000000
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64#define HDLC_MAX_FRAME_SIZE 65535
65#define MAX_ASYNC_TRANSMIT 4096
66#define MAX_ASYNC_BUFFER_SIZE 4096
67#define ASYNC_PARITY_NONE 0
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69#define ASYNC_PARITY_EVEN 1
70#define ASYNC_PARITY_ODD 2
71#define ASYNC_PARITY_SPACE 3
72#define HDLC_FLAG_UNDERRUN_ABORT7 0x0000
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74#define HDLC_FLAG_UNDERRUN_ABORT15 0x0001
75#define HDLC_FLAG_UNDERRUN_FLAG 0x0002
76#define HDLC_FLAG_UNDERRUN_CRC 0x0004
77#define HDLC_FLAG_SHARE_ZERO 0x0010
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define HDLC_FLAG_AUTO_CTS 0x0020
80#define HDLC_FLAG_AUTO_DCD 0x0040
81#define HDLC_FLAG_AUTO_RTS 0x0080
82#define HDLC_FLAG_RXC_DPLL 0x0100
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84#define HDLC_FLAG_RXC_BRG 0x0200
85#define HDLC_FLAG_RXC_TXCPIN 0x8000
86#define HDLC_FLAG_RXC_RXCPIN 0x0000
87#define HDLC_FLAG_TXC_DPLL 0x0400
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89#define HDLC_FLAG_TXC_BRG 0x0800
90#define HDLC_FLAG_TXC_TXCPIN 0x0000
91#define HDLC_FLAG_TXC_RXCPIN 0x0008
92#define HDLC_FLAG_DPLL_DIV8 0x1000
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94#define HDLC_FLAG_DPLL_DIV16 0x2000
95#define HDLC_FLAG_DPLL_DIV32 0x0000
96#define HDLC_FLAG_HDLC_LOOPMODE 0x4000
97#define HDLC_CRC_NONE 0
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99#define HDLC_CRC_16_CCITT 1
100#define HDLC_CRC_32_CCITT 2
101#define HDLC_CRC_MASK 0x00ff
102#define HDLC_CRC_RETURN_EX 0x8000
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104#define RX_OK 0
105#define RX_CRC_ERROR 1
106#define HDLC_TXIDLE_FLAGS 0
107#define HDLC_TXIDLE_ALT_ZEROS_ONES 1
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109#define HDLC_TXIDLE_ZEROS 2
110#define HDLC_TXIDLE_ONES 3
111#define HDLC_TXIDLE_ALT_MARK_SPACE 4
112#define HDLC_TXIDLE_SPACE 5
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114#define HDLC_TXIDLE_MARK 6
115#define HDLC_TXIDLE_CUSTOM_8 0x10000000
116#define HDLC_TXIDLE_CUSTOM_16 0x20000000
117#define HDLC_ENCODING_NRZ 0
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119#define HDLC_ENCODING_NRZB 1
120#define HDLC_ENCODING_NRZI_MARK 2
121#define HDLC_ENCODING_NRZI_SPACE 3
122#define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124#define HDLC_ENCODING_BIPHASE_MARK 4
125#define HDLC_ENCODING_BIPHASE_SPACE 5
126#define HDLC_ENCODING_BIPHASE_LEVEL 6
127#define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129#define HDLC_PREAMBLE_LENGTH_8BITS 0
130#define HDLC_PREAMBLE_LENGTH_16BITS 1
131#define HDLC_PREAMBLE_LENGTH_32BITS 2
132#define HDLC_PREAMBLE_LENGTH_64BITS 3
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134#define HDLC_PREAMBLE_PATTERN_NONE 0
135#define HDLC_PREAMBLE_PATTERN_ZEROS 1
136#define HDLC_PREAMBLE_PATTERN_FLAGS 2
137#define HDLC_PREAMBLE_PATTERN_10 3
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139#define HDLC_PREAMBLE_PATTERN_01 4
140#define HDLC_PREAMBLE_PATTERN_ONES 5
141#define MGSL_MODE_ASYNC 1
142#define MGSL_MODE_HDLC 2
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144#define MGSL_MODE_MONOSYNC 3
145#define MGSL_MODE_BISYNC 4
146#define MGSL_MODE_RAW 6
147#define MGSL_MODE_BASE_CLOCK 7
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149#define MGSL_MODE_XSYNC 8
150#define MGSL_BUS_TYPE_ISA 1
151#define MGSL_BUS_TYPE_EISA 2
152#define MGSL_BUS_TYPE_PCI 5
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154#define MGSL_INTERFACE_MASK 0xf
155#define MGSL_INTERFACE_DISABLE 0
156#define MGSL_INTERFACE_RS232 1
157#define MGSL_INTERFACE_V35 2
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
159#define MGSL_INTERFACE_RS422 3
160#define MGSL_INTERFACE_RTS_EN 0x10
161#define MGSL_INTERFACE_LL 0x20
162#define MGSL_INTERFACE_RL 0x40
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
164#define MGSL_INTERFACE_MSB_FIRST 0x80
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]165typedef struct _MGSL_PARAMS {
166 unsigned long mode;
167 unsigned char loopback;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]169 unsigned short flags;
170 unsigned char encoding;
171 unsigned long clock_speed;
172 unsigned char addr_filter;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]174 unsigned short crc_type;
175 unsigned char preamble_length;
176 unsigned char preamble;
177 unsigned long data_rate;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]179 unsigned char data_bits;
180 unsigned char stop_bits;
181 unsigned char parity;
182} MGSL_PARAMS, * PMGSL_PARAMS;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define MICROGATE_VENDOR_ID 0x13c0
185#define SYNCLINK_DEVICE_ID 0x0010
186#define MGSCC_DEVICE_ID 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]187#define SYNCLINK_SCA_DEVICE_ID 0x0030
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define SYNCLINK_GT_DEVICE_ID 0x0070
190#define SYNCLINK_GT4_DEVICE_ID 0x0080
191#define SYNCLINK_AC_DEVICE_ID 0x0090
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]192#define SYNCLINK_GT2_DEVICE_ID 0x00A0
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194#define MGSL_MAX_SERIAL_NUMBER 30
195#define DiagStatus_OK 0
196#define DiagStatus_AddressFailure 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]197#define DiagStatus_AddressConflict 2
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]199#define DiagStatus_IrqFailure 3
200#define DiagStatus_IrqConflict 4
201#define DiagStatus_DmaFailure 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]202#define DiagStatus_DmaConflict 6
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204#define DiagStatus_PciAdapterNotFound 7
205#define DiagStatus_CantAssignPciResources 8
206#define DiagStatus_CantAssignPciMemAddr 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]207#define DiagStatus_CantAssignPciIoAddr 10
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]209#define DiagStatus_CantAssignPciIrq 11
210#define DiagStatus_MemoryError 12
211#define SerialSignal_DCD 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]212#define SerialSignal_TXD 0x02
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214#define SerialSignal_RI 0x04
215#define SerialSignal_RXD 0x08
216#define SerialSignal_CTS 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]217#define SerialSignal_RTS 0x20
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define SerialSignal_DSR 0x40
220#define SerialSignal_DTR 0x80
221struct mgsl_icount {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]222 __u32 cts, dsr, rng, dcd, tx, rx;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]224 __u32 frame, parity, overrun, brk;
225 __u32 buf_overrun;
226 __u32 txok;
227 __u32 txunder;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]229 __u32 txabort;
230 __u32 txtimeout;
231 __u32 rxshort;
232 __u32 rxlong;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]234 __u32 rxabort;
235 __u32 rxover;
236 __u32 rxcrc;
237 __u32 rxok;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]239 __u32 exithunt;
240 __u32 rxidle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]241};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]242struct gpio_desc {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]244 __u32 state;
245 __u32 smask;
246 __u32 dir;
247 __u32 dmask;
248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]249};
250#define DEBUG_LEVEL_DATA 1
251#define DEBUG_LEVEL_ERROR 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]252#define DEBUG_LEVEL_INFO 3
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]254#define DEBUG_LEVEL_BH 4
255#define DEBUG_LEVEL_ISR 5
256#define MgslEvent_DsrActive 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]257#define MgslEvent_DsrInactive 0x0002
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]259#define MgslEvent_Dsr 0x0003
260#define MgslEvent_CtsActive 0x0004
261#define MgslEvent_CtsInactive 0x0008
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]262#define MgslEvent_Cts 0x000c
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]264#define MgslEvent_DcdActive 0x0010
265#define MgslEvent_DcdInactive 0x0020
266#define MgslEvent_Dcd 0x0030
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]267#define MgslEvent_RiActive 0x0040
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]269#define MgslEvent_RiInactive 0x0080
270#define MgslEvent_Ri 0x00c0
271#define MgslEvent_ExitHuntMode 0x0100
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]272#define MgslEvent_IdleReceived 0x0200
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]274#define MGSL_MAGIC_IOC 'm'
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]275#define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC, 0, struct _MGSL_PARAMS)
276#define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC, 1, struct _MGSL_PARAMS)
277#define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC, 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]279#define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC, 3)
280#define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC, 4)
281#define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC, 5)
282#define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC, 6)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]284#define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC, 7)
285#define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC, 8, int)
286#define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC, 15)
287#define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC, 9)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]289#define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC, 10)
290#define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC, 11)
291#define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC, 16, struct gpio_desc)
292#define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC, 17, struct gpio_desc)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]294#define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC, 18, struct gpio_desc)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]295#define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19)
296#define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]297#define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]299#define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22)
300#endif