| Calin Juravle | 2d36790 | 2014-02-25 14:49:41 +0000 | [diff] [blame^] | 1 | /*- |
| 2 | * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in the |
| 12 | * documentation and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 24 | * SUCH DAMAGE. |
| 25 | * |
| 26 | * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * Rewritten for Android. |
| 31 | * |
| 32 | * The ARM FPSCR (Floating-point Status and Control Register) described here: |
| 33 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Chdfafia.html |
| 34 | * has been split into the FPCR (Floating-point Control Register) and FPSR |
| 35 | * (Floating-point Status Register) on the ARMv8. These are described briefly in |
| 36 | * "Procedure Call Standard for the ARM 64-bit Architecture" |
| 37 | * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055a/IHI0055A_aapcs64.pdf |
| 38 | * section 5.1.2 SIMD and Floating-Point Registers |
| 39 | */ |
| 40 | |
| 41 | #ifndef _ARM64_FENV_H_ |
| 42 | #define _ARM64_FENV_H_ |
| 43 | |
| 44 | #include <sys/types.h> |
| 45 | |
| 46 | __BEGIN_DECLS |
| 47 | |
| 48 | typedef __uint32_t fenv_t; |
| 49 | typedef __uint32_t fexcept_t; |
| 50 | |
| 51 | /* Exception flags. */ |
| 52 | #define FE_INVALID 0x01 |
| 53 | #define FE_DIVBYZERO 0x02 |
| 54 | #define FE_OVERFLOW 0x04 |
| 55 | #define FE_UNDERFLOW 0x08 |
| 56 | #define FE_INEXACT 0x10 |
| 57 | #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ |
| 58 | FE_OVERFLOW | FE_UNDERFLOW) |
| 59 | |
| 60 | #define _FPSCR_ENABLE_SHIFT 8 |
| 61 | #define _FPSCR_ENABLE_MASK (FE_ALL_EXCEPT << _FPSCR_ENABLE_SHIFT) |
| 62 | |
| 63 | /* Rounding modes. */ |
| 64 | #define FE_TONEAREST 0x0 |
| 65 | #define FE_UPWARD 0x1 |
| 66 | #define FE_DOWNWARD 0x2 |
| 67 | #define FE_TOWARDZERO 0x3 |
| 68 | |
| 69 | #define _FPSCR_RMODE_SHIFT 22 |
| 70 | |
| 71 | #define FPCR_IOE (1 << 8) |
| 72 | #define FPCR_DZE (1 << 9) |
| 73 | #define FPCR_OFE (1 << 10) |
| 74 | #define FPCR_UFE (1 << 11) |
| 75 | #define FPCR_IXE (1 << 12) |
| 76 | #define FPCR_IDE (1 << 15) |
| 77 | #define FPCR_LEN (7 << 16) |
| 78 | #define FPCR_STRIDE (3 << 20) |
| 79 | #define FPCR_RMODE (3 << 22) |
| 80 | #define FPCR_FZ (1 << 24) |
| 81 | #define FPCR_DN (1 << 25) |
| 82 | #define FPCR_AHP (1 << 26) |
| 83 | #define FPCR_MASK (FPCR_IOE | \ |
| 84 | FPCR_DZE | \ |
| 85 | FPCR_OFE | \ |
| 86 | FPCR_UFE | \ |
| 87 | FPCR_IXE | \ |
| 88 | FPCR_IDE | \ |
| 89 | FPCR_LEN | \ |
| 90 | FPCR_STRIDE | \ |
| 91 | FPCR_RMODE | \ |
| 92 | FPCR_FZ | \ |
| 93 | FPCR_DN | \ |
| 94 | FPCR_AHP ) |
| 95 | |
| 96 | #define FPSR_IOC (1 << 0) |
| 97 | #define FPSR_DZC (1 << 1) |
| 98 | #define FPSR_OFC (1 << 2) |
| 99 | #define FPSR_UFC (1 << 3) |
| 100 | #define FPSR_IXC (1 << 4) |
| 101 | #define FPSR_IDC (1 << 7) |
| 102 | #define FPSR_QC (1 << 27) |
| 103 | #define FPSR_V (1 << 28) |
| 104 | #define FPSR_C (1 << 29) |
| 105 | #define FPSR_Z (1 << 30) |
| 106 | #define FPSR_N (1 << 31) |
| 107 | #define FPSR_MASK (FPSR_IOC | \ |
| 108 | FPSR_DZC | \ |
| 109 | FPSR_OFC | \ |
| 110 | FPSR_UFC | \ |
| 111 | FPSR_IXC | \ |
| 112 | FPSR_IDC | \ |
| 113 | FPSR_QC | \ |
| 114 | FPSR_V | \ |
| 115 | FPSR_C | \ |
| 116 | FPSR_Z | \ |
| 117 | FPSR_N ) |
| 118 | |
| 119 | __END_DECLS |
| 120 | |
| 121 | #endif /* !_ARM64_FENV_H_ */ |