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review.blissroms.org / platform_bionic / 38062f954c637861348dd8078cefb73554e6f12c / . / libc / kernel / uapi / linux / pci_regs.h
blob: d20f5001908b8c11f3c61119fc2fc7b3c34442f9 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef LINUX_PCI_REGS_H
20#define LINUX_PCI_REGS_H
21#define PCI_STD_HEADER_SIZEOF 64
22#define PCI_VENDOR_ID 0x00
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define PCI_DEVICE_ID 0x02
25#define PCI_COMMAND 0x04
26#define PCI_COMMAND_IO 0x1
27#define PCI_COMMAND_MEMORY 0x2
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define PCI_COMMAND_MASTER 0x4
30#define PCI_COMMAND_SPECIAL 0x8
31#define PCI_COMMAND_INVALIDATE 0x10
32#define PCI_COMMAND_VGA_PALETTE 0x20
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define PCI_COMMAND_PARITY 0x40
35#define PCI_COMMAND_WAIT 0x80
36#define PCI_COMMAND_SERR 0x100
37#define PCI_COMMAND_FAST_BACK 0x200
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define PCI_COMMAND_INTX_DISABLE 0x400
40#define PCI_STATUS 0x06
41#define PCI_STATUS_INTERRUPT 0x08
42#define PCI_STATUS_CAP_LIST 0x10
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define PCI_STATUS_66MHZ 0x20
45#define PCI_STATUS_UDF 0x40
46#define PCI_STATUS_FAST_BACK 0x80
47#define PCI_STATUS_PARITY 0x100
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define PCI_STATUS_DEVSEL_MASK 0x600
50#define PCI_STATUS_DEVSEL_FAST 0x000
51#define PCI_STATUS_DEVSEL_MEDIUM 0x200
52#define PCI_STATUS_DEVSEL_SLOW 0x400
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define PCI_STATUS_SIG_TARGET_ABORT 0x800
55#define PCI_STATUS_REC_TARGET_ABORT 0x1000
56#define PCI_STATUS_REC_MASTER_ABORT 0x2000
57#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define PCI_STATUS_DETECTED_PARITY 0x8000
60#define PCI_CLASS_REVISION 0x08
61#define PCI_REVISION_ID 0x08
62#define PCI_CLASS_PROG 0x09
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64#define PCI_CLASS_DEVICE 0x0a
65#define PCI_CACHE_LINE_SIZE 0x0c
66#define PCI_LATENCY_TIMER 0x0d
67#define PCI_HEADER_TYPE 0x0e
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69#define PCI_HEADER_TYPE_NORMAL 0
70#define PCI_HEADER_TYPE_BRIDGE 1
71#define PCI_HEADER_TYPE_CARDBUS 2
72#define PCI_BIST 0x0f
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74#define PCI_BIST_CODE_MASK 0x0f
75#define PCI_BIST_START 0x40
76#define PCI_BIST_CAPABLE 0x80
77#define PCI_BASE_ADDRESS_0 0x10
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define PCI_BASE_ADDRESS_1 0x14
80#define PCI_BASE_ADDRESS_2 0x18
81#define PCI_BASE_ADDRESS_3 0x1c
82#define PCI_BASE_ADDRESS_4 0x20
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84#define PCI_BASE_ADDRESS_5 0x24
85#define PCI_BASE_ADDRESS_SPACE 0x01
86#define PCI_BASE_ADDRESS_SPACE_IO 0x01
87#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
90#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00
91#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02
92#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
95#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
96#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
97#define PCI_CARDBUS_CIS 0x28
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
100#define PCI_SUBSYSTEM_ID 0x2e
101#define PCI_ROM_ADDRESS 0x30
102#define PCI_ROM_ADDRESS_ENABLE 0x01
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
105#define PCI_CAPABILITY_LIST 0x34
106#define PCI_INTERRUPT_LINE 0x3c
107#define PCI_INTERRUPT_PIN 0x3d
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109#define PCI_MIN_GNT 0x3e
110#define PCI_MAX_LAT 0x3f
111#define PCI_PRIMARY_BUS 0x18
112#define PCI_SECONDARY_BUS 0x19
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114#define PCI_SUBORDINATE_BUS 0x1a
115#define PCI_SEC_LATENCY_TIMER 0x1b
116#define PCI_IO_BASE 0x1c
117#define PCI_IO_LIMIT 0x1d
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119#define PCI_IO_RANGE_TYPE_MASK 0x0fUL
120#define PCI_IO_RANGE_TYPE_16 0x00
121#define PCI_IO_RANGE_TYPE_32 0x01
122#define PCI_IO_RANGE_MASK (~0x0fUL)
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124#define PCI_IO_1K_RANGE_MASK (~0x03UL)
125#define PCI_SEC_STATUS 0x1e
126#define PCI_MEMORY_BASE 0x20
127#define PCI_MEMORY_LIMIT 0x22
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
130#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
131#define PCI_PREF_MEMORY_BASE 0x24
132#define PCI_PREF_MEMORY_LIMIT 0x26
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
135#define PCI_PREF_RANGE_TYPE_32 0x00
136#define PCI_PREF_RANGE_TYPE_64 0x01
137#define PCI_PREF_RANGE_MASK (~0x0fUL)
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139#define PCI_PREF_BASE_UPPER32 0x28
140#define PCI_PREF_LIMIT_UPPER32 0x2c
141#define PCI_IO_BASE_UPPER16 0x30
142#define PCI_IO_LIMIT_UPPER16 0x32
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144#define PCI_ROM_ADDRESS1 0x38
145#define PCI_BRIDGE_CONTROL 0x3e
146#define PCI_BRIDGE_CTL_PARITY 0x01
147#define PCI_BRIDGE_CTL_SERR 0x02
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149#define PCI_BRIDGE_CTL_ISA 0x04
150#define PCI_BRIDGE_CTL_VGA 0x08
151#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20
152#define PCI_BRIDGE_CTL_BUS_RESET 0x40
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154#define PCI_BRIDGE_CTL_FAST_BACK 0x80
155#define PCI_CB_CAPABILITY_LIST 0x14
156#define PCI_CB_SEC_STATUS 0x16
157#define PCI_CB_PRIMARY_BUS 0x18
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
159#define PCI_CB_CARD_BUS 0x19
160#define PCI_CB_SUBORDINATE_BUS 0x1a
161#define PCI_CB_LATENCY_TIMER 0x1b
162#define PCI_CB_MEMORY_BASE_0 0x1c
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
164#define PCI_CB_MEMORY_LIMIT_0 0x20
165#define PCI_CB_MEMORY_BASE_1 0x24
166#define PCI_CB_MEMORY_LIMIT_1 0x28
167#define PCI_CB_IO_BASE_0 0x2c
168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
169#define PCI_CB_IO_BASE_0_HI 0x2e
170#define PCI_CB_IO_LIMIT_0 0x30
171#define PCI_CB_IO_LIMIT_0_HI 0x32
172#define PCI_CB_IO_BASE_1 0x34
173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
174#define PCI_CB_IO_BASE_1_HI 0x36
175#define PCI_CB_IO_LIMIT_1 0x38
176#define PCI_CB_IO_LIMIT_1_HI 0x3a
177#define PCI_CB_IO_RANGE_MASK (~0x03UL)
178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
179#define PCI_CB_BRIDGE_CONTROL 0x3e
180#define PCI_CB_BRIDGE_CTL_PARITY 0x01
181#define PCI_CB_BRIDGE_CTL_SERR 0x02
182#define PCI_CB_BRIDGE_CTL_ISA 0x04
183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
184#define PCI_CB_BRIDGE_CTL_VGA 0x08
185#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
186#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40
187#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
189#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
190#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
191#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
192#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
194#define PCI_CB_SUBSYSTEM_ID 0x42
195#define PCI_CB_LEGACY_MODE_BASE 0x44
196#define PCI_CAP_LIST_ID 0
197#define PCI_CAP_ID_PM 0x01
198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
199#define PCI_CAP_ID_AGP 0x02
200#define PCI_CAP_ID_VPD 0x03
201#define PCI_CAP_ID_SLOTID 0x04
202#define PCI_CAP_ID_MSI 0x05
203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
204#define PCI_CAP_ID_CHSWP 0x06
205#define PCI_CAP_ID_PCIX 0x07
206#define PCI_CAP_ID_HT 0x08
207#define PCI_CAP_ID_VNDR 0x09
208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
209#define PCI_CAP_ID_DBG 0x0A
210#define PCI_CAP_ID_CCRC 0x0B
211#define PCI_CAP_ID_SHPC 0x0C
212#define PCI_CAP_ID_SSVID 0x0D
213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
214#define PCI_CAP_ID_AGP3 0x0E
215#define PCI_CAP_ID_SECDEV 0x0F
216#define PCI_CAP_ID_EXP 0x10
217#define PCI_CAP_ID_MSIX 0x11
218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
219#define PCI_CAP_ID_SATA 0x12
220#define PCI_CAP_ID_AF 0x13
221#define PCI_CAP_ID_MAX PCI_CAP_ID_AF
222#define PCI_CAP_LIST_NEXT 1
223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
224#define PCI_CAP_FLAGS 2
225#define PCI_CAP_SIZEOF 4
226#define PCI_PM_PMC 2
227#define PCI_PM_CAP_VER_MASK 0x0007
228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
229#define PCI_PM_CAP_PME_CLOCK 0x0008
230#define PCI_PM_CAP_RESERVED 0x0010
231#define PCI_PM_CAP_DSI 0x0020
232#define PCI_PM_CAP_AUX_POWER 0x01C0
233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
234#define PCI_PM_CAP_D1 0x0200
235#define PCI_PM_CAP_D2 0x0400
236#define PCI_PM_CAP_PME 0x0800
237#define PCI_PM_CAP_PME_MASK 0xF800
238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
239#define PCI_PM_CAP_PME_D0 0x0800
240#define PCI_PM_CAP_PME_D1 0x1000
241#define PCI_PM_CAP_PME_D2 0x2000
242#define PCI_PM_CAP_PME_D3 0x4000
243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
244#define PCI_PM_CAP_PME_D3cold 0x8000
245#define PCI_PM_CAP_PME_SHIFT 11
246#define PCI_PM_CTRL 4
247#define PCI_PM_CTRL_STATE_MASK 0x0003
248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
249#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008
250#define PCI_PM_CTRL_PME_ENABLE 0x0100
251#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00
252#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000
253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
254#define PCI_PM_CTRL_PME_STATUS 0x8000
255#define PCI_PM_PPB_EXTENSIONS 6
256#define PCI_PM_PPB_B2_B3 0x40
257#define PCI_PM_BPCC_ENABLE 0x80
258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
259#define PCI_PM_DATA_REGISTER 7
260#define PCI_PM_SIZEOF 8
261#define PCI_AGP_VERSION 2
262#define PCI_AGP_RFU 3
263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
264#define PCI_AGP_STATUS 4
265#define PCI_AGP_STATUS_RQ_MASK 0xff000000
266#define PCI_AGP_STATUS_SBA 0x0200
267#define PCI_AGP_STATUS_64BIT 0x0020
268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
269#define PCI_AGP_STATUS_FW 0x0010
270#define PCI_AGP_STATUS_RATE4 0x0004
271#define PCI_AGP_STATUS_RATE2 0x0002
272#define PCI_AGP_STATUS_RATE1 0x0001
273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
274#define PCI_AGP_COMMAND 8
275#define PCI_AGP_COMMAND_RQ_MASK 0xff000000
276#define PCI_AGP_COMMAND_SBA 0x0200
277#define PCI_AGP_COMMAND_AGP 0x0100
278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
279#define PCI_AGP_COMMAND_64BIT 0x0020
280#define PCI_AGP_COMMAND_FW 0x0010
281#define PCI_AGP_COMMAND_RATE4 0x0004
282#define PCI_AGP_COMMAND_RATE2 0x0002
283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
284#define PCI_AGP_COMMAND_RATE1 0x0001
285#define PCI_AGP_SIZEOF 12
286#define PCI_VPD_ADDR 2
287#define PCI_VPD_ADDR_MASK 0x7fff
288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
289#define PCI_VPD_ADDR_F 0x8000
290#define PCI_VPD_DATA 4
291#define PCI_CAP_VPD_SIZEOF 8
292#define PCI_SID_ESR 2
293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
294#define PCI_SID_ESR_NSLOTS 0x1f
295#define PCI_SID_ESR_FIC 0x20
296#define PCI_SID_CHASSIS_NR 3
297#define PCI_MSI_FLAGS 2
298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
299#define PCI_MSI_FLAGS_ENABLE 0x0001
300#define PCI_MSI_FLAGS_QMASK 0x000e
301#define PCI_MSI_FLAGS_QSIZE 0x0070
302#define PCI_MSI_FLAGS_64BIT 0x0080
303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
304#define PCI_MSI_FLAGS_MASKBIT 0x0100
305#define PCI_MSI_RFU 3
306#define PCI_MSI_ADDRESS_LO 4
307#define PCI_MSI_ADDRESS_HI 8
308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
309#define PCI_MSI_DATA_32 8
310#define PCI_MSI_MASK_32 12
311#define PCI_MSI_PENDING_32 16
312#define PCI_MSI_DATA_64 12
313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
314#define PCI_MSI_MASK_64 16
315#define PCI_MSI_PENDING_64 20
316#define PCI_MSIX_FLAGS 2
317#define PCI_MSIX_FLAGS_QSIZE 0x07FF
318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
319#define PCI_MSIX_FLAGS_MASKALL 0x4000
320#define PCI_MSIX_FLAGS_ENABLE 0x8000
321#define PCI_MSIX_TABLE 4
322#define PCI_MSIX_TABLE_BIR 0x00000007
323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
324#define PCI_MSIX_TABLE_OFFSET 0xfffffff8
325#define PCI_MSIX_PBA 8
326#define PCI_MSIX_PBA_BIR 0x00000007
327#define PCI_MSIX_PBA_OFFSET 0xfffffff8
328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]329#define PCI_CAP_MSIX_SIZEOF 12
330#define PCI_MSIX_ENTRY_SIZE 16
331#define PCI_MSIX_ENTRY_LOWER_ADDR 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]332#define PCI_MSIX_ENTRY_UPPER_ADDR 4
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]334#define PCI_MSIX_ENTRY_DATA 8
335#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
336#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]337#define PCI_CHSWP_CSR 2
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]339#define PCI_CHSWP_DHA 0x01
340#define PCI_CHSWP_EIM 0x02
341#define PCI_CHSWP_PIE 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]342#define PCI_CHSWP_LOO 0x08
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]344#define PCI_CHSWP_PI 0x30
345#define PCI_CHSWP_EXT 0x40
346#define PCI_CHSWP_INS 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]347#define PCI_AF_LENGTH 2
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]349#define PCI_AF_CAP 3
350#define PCI_AF_CAP_TP 0x01
351#define PCI_AF_CAP_FLR 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]352#define PCI_AF_CTRL 4
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]354#define PCI_AF_CTRL_FLR 0x01
355#define PCI_AF_STATUS 5
356#define PCI_AF_STATUS_TP 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]357#define PCI_CAP_AF_SIZEOF 6
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]359#define PCI_X_CMD 2
360#define PCI_X_CMD_DPERR_E 0x0001
361#define PCI_X_CMD_ERO 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]362#define PCI_X_CMD_READ_512 0x0000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]364#define PCI_X_CMD_READ_1K 0x0004
365#define PCI_X_CMD_READ_2K 0x0008
366#define PCI_X_CMD_READ_4K 0x000c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]367#define PCI_X_CMD_MAX_READ 0x000c
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]369#define PCI_X_CMD_SPLIT_1 0x0000
370#define PCI_X_CMD_SPLIT_2 0x0010
371#define PCI_X_CMD_SPLIT_3 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]372#define PCI_X_CMD_SPLIT_4 0x0030
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]374#define PCI_X_CMD_SPLIT_8 0x0040
375#define PCI_X_CMD_SPLIT_12 0x0050
376#define PCI_X_CMD_SPLIT_16 0x0060
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]377#define PCI_X_CMD_SPLIT_32 0x0070
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]379#define PCI_X_CMD_MAX_SPLIT 0x0070
380#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3)
381#define PCI_X_STATUS 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]382#define PCI_X_STATUS_DEVFN 0x000000ff
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]384#define PCI_X_STATUS_BUS 0x0000ff00
385#define PCI_X_STATUS_64BIT 0x00010000
386#define PCI_X_STATUS_133MHZ 0x00020000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]387#define PCI_X_STATUS_SPL_DISC 0x00040000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]389#define PCI_X_STATUS_UNX_SPL 0x00080000
390#define PCI_X_STATUS_COMPLEX 0x00100000
391#define PCI_X_STATUS_MAX_READ 0x00600000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]392#define PCI_X_STATUS_MAX_SPLIT 0x03800000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]394#define PCI_X_STATUS_MAX_CUM 0x1c000000
395#define PCI_X_STATUS_SPL_ERR 0x20000000
396#define PCI_X_STATUS_266MHZ 0x40000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]397#define PCI_X_STATUS_533MHZ 0x80000000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]399#define PCI_X_ECC_CSR 8
400#define PCI_CAP_PCIX_SIZEOF_V0 8
401#define PCI_CAP_PCIX_SIZEOF_V1 24
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]402#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]404#define PCI_X_BRIDGE_SSTATUS 2
405#define PCI_X_SSTATUS_64BIT 0x0001
406#define PCI_X_SSTATUS_133MHZ 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]407#define PCI_X_SSTATUS_FREQ 0x03c0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]409#define PCI_X_SSTATUS_VERS 0x3000
410#define PCI_X_SSTATUS_V1 0x1000
411#define PCI_X_SSTATUS_V2 0x2000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]412#define PCI_X_SSTATUS_266MHZ 0x4000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]414#define PCI_X_SSTATUS_533MHZ 0x8000
415#define PCI_X_BRIDGE_STATUS 4
416#define PCI_SSVID_VENDOR_ID 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]417#define PCI_SSVID_DEVICE_ID 6
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]419#define PCI_EXP_FLAGS 2
420#define PCI_EXP_FLAGS_VERS 0x000f
421#define PCI_EXP_FLAGS_TYPE 0x00f0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]422#define PCI_EXP_TYPE_ENDPOINT 0x0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]424#define PCI_EXP_TYPE_LEG_END 0x1
425#define PCI_EXP_TYPE_ROOT_PORT 0x4
426#define PCI_EXP_TYPE_UPSTREAM 0x5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]427#define PCI_EXP_TYPE_DOWNSTREAM 0x6
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]429#define PCI_EXP_TYPE_PCI_BRIDGE 0x7
430#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8
431#define PCI_EXP_TYPE_RC_END 0x9
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]432#define PCI_EXP_TYPE_RC_EC 0xa
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]434#define PCI_EXP_FLAGS_SLOT 0x0100
435#define PCI_EXP_FLAGS_IRQ 0x3e00
436#define PCI_EXP_DEVCAP 4
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]437#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]439#define PCI_EXP_DEVCAP_PHANTOM 0x00000018
440#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020
441#define PCI_EXP_DEVCAP_L0S 0x000001c0
442#define PCI_EXP_DEVCAP_L1 0x00000e00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]444#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000
445#define PCI_EXP_DEVCAP_ATN_IND 0x00002000
446#define PCI_EXP_DEVCAP_PWR_IND 0x00004000
447#define PCI_EXP_DEVCAP_RBER 0x00008000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]449#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000
450#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]451#define PCI_EXP_DEVCAP_FLR 0x10000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]452#define PCI_EXP_DEVCTL 8
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]454#define PCI_EXP_DEVCTL_CERE 0x0001
455#define PCI_EXP_DEVCTL_NFERE 0x0002
456#define PCI_EXP_DEVCTL_FERE 0x0004
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]457#define PCI_EXP_DEVCTL_URRE 0x0008
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]459#define PCI_EXP_DEVCTL_RELAX_EN 0x0010
460#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
461#define PCI_EXP_DEVCTL_EXT_TAG 0x0100
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]462#define PCI_EXP_DEVCTL_PHANTOM 0x0200
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]464#define PCI_EXP_DEVCTL_AUX_PME 0x0400
465#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800
466#define PCI_EXP_DEVCTL_READRQ 0x7000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]467#define PCI_EXP_DEVCTL_BCR_FLR 0x8000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]469#define PCI_EXP_DEVSTA 10
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]470#define PCI_EXP_DEVSTA_CED 0x0001
471#define PCI_EXP_DEVSTA_NFED 0x0002
472#define PCI_EXP_DEVSTA_FED 0x0004
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]474#define PCI_EXP_DEVSTA_URD 0x0008
475#define PCI_EXP_DEVSTA_AUXPD 0x0010
476#define PCI_EXP_DEVSTA_TRPND 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]477#define PCI_EXP_LNKCAP 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]479#define PCI_EXP_LNKCAP_SLS 0x0000000f
480#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001
481#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]482#define PCI_EXP_LNKCAP_MLW 0x000003f0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]484#define PCI_EXP_LNKCAP_ASPMS 0x00000c00
485#define PCI_EXP_LNKCAP_L0SEL 0x00007000
486#define PCI_EXP_LNKCAP_L1EL 0x00038000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]487#define PCI_EXP_LNKCAP_CLKPM 0x00040000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]489#define PCI_EXP_LNKCAP_SDERC 0x00080000
490#define PCI_EXP_LNKCAP_DLLLARC 0x00100000
491#define PCI_EXP_LNKCAP_LBNC 0x00200000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]492#define PCI_EXP_LNKCAP_PN 0xff000000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]494#define PCI_EXP_LNKCTL 16
495#define PCI_EXP_LNKCTL_ASPMC 0x0003
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]496#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001
497#define PCI_EXP_LNKCTL_ASPM_L1 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]499#define PCI_EXP_LNKCTL_RCB 0x0008
500#define PCI_EXP_LNKCTL_LD 0x0010
501#define PCI_EXP_LNKCTL_RL 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]502#define PCI_EXP_LNKCTL_CCC 0x0040
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]504#define PCI_EXP_LNKCTL_ES 0x0080
505#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100
506#define PCI_EXP_LNKCTL_HAWD 0x0200
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]507#define PCI_EXP_LNKCTL_LBMIE 0x0400
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]509#define PCI_EXP_LNKCTL_LABIE 0x0800
510#define PCI_EXP_LNKSTA 18
511#define PCI_EXP_LNKSTA_CLS 0x000f
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]512#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]514#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002
515#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]516#define PCI_EXP_LNKSTA_NLW 0x03f0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]517#define PCI_EXP_LNKSTA_NLW_X1 0x0010
518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
519#define PCI_EXP_LNKSTA_NLW_X2 0x0020
520#define PCI_EXP_LNKSTA_NLW_X4 0x0040
521#define PCI_EXP_LNKSTA_NLW_X8 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]522#define PCI_EXP_LNKSTA_NLW_SHIFT 4
523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
524#define PCI_EXP_LNKSTA_LT 0x0800
525#define PCI_EXP_LNKSTA_SLC 0x1000
526#define PCI_EXP_LNKSTA_DLLLA 0x2000
527#define PCI_EXP_LNKSTA_LBMS 0x4000
528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
529#define PCI_EXP_LNKSTA_LABS 0x8000
530#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20
531#define PCI_EXP_SLTCAP 20
532#define PCI_EXP_SLTCAP_ABP 0x00000001
533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
534#define PCI_EXP_SLTCAP_PCP 0x00000002
535#define PCI_EXP_SLTCAP_MRLSP 0x00000004
536#define PCI_EXP_SLTCAP_AIP 0x00000008
537#define PCI_EXP_SLTCAP_PIP 0x00000010
538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
539#define PCI_EXP_SLTCAP_HPS 0x00000020
540#define PCI_EXP_SLTCAP_HPC 0x00000040
541#define PCI_EXP_SLTCAP_SPLV 0x00007f80
542#define PCI_EXP_SLTCAP_SPLS 0x00018000
543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
544#define PCI_EXP_SLTCAP_EIP 0x00020000
545#define PCI_EXP_SLTCAP_NCCS 0x00040000
546#define PCI_EXP_SLTCAP_PSN 0xfff80000
547#define PCI_EXP_SLTCTL 24
548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
549#define PCI_EXP_SLTCTL_ABPE 0x0001
550#define PCI_EXP_SLTCTL_PFDE 0x0002
551#define PCI_EXP_SLTCTL_MRLSCE 0x0004
552#define PCI_EXP_SLTCTL_PDCE 0x0008
553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
554#define PCI_EXP_SLTCTL_CCIE 0x0010
555#define PCI_EXP_SLTCTL_HPIE 0x0020
556#define PCI_EXP_SLTCTL_AIC 0x00c0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]557#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]559#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080
560#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0
561#define PCI_EXP_SLTCTL_PIC 0x0300
562#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100
563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
564#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200
565#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]566#define PCI_EXP_SLTCTL_PCC 0x0400
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]567#define PCI_EXP_SLTCTL_PWR_ON 0x0000
568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
569#define PCI_EXP_SLTCTL_PWR_OFF 0x0400
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]570#define PCI_EXP_SLTCTL_EIC 0x0800
571#define PCI_EXP_SLTCTL_DLLSCE 0x1000
572#define PCI_EXP_SLTSTA 26
573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
574#define PCI_EXP_SLTSTA_ABP 0x0001
575#define PCI_EXP_SLTSTA_PFD 0x0002
576#define PCI_EXP_SLTSTA_MRLSC 0x0004
577#define PCI_EXP_SLTSTA_PDC 0x0008
578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
579#define PCI_EXP_SLTSTA_CC 0x0010
580#define PCI_EXP_SLTSTA_MRLSS 0x0020
581#define PCI_EXP_SLTSTA_PDS 0x0040
582#define PCI_EXP_SLTSTA_EIS 0x0080
583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
584#define PCI_EXP_SLTSTA_DLLSC 0x0100
585#define PCI_EXP_RTCTL 28
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]586#define PCI_EXP_RTCTL_SECEE 0x0001
587#define PCI_EXP_RTCTL_SENFEE 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]589#define PCI_EXP_RTCTL_SEFEE 0x0004
590#define PCI_EXP_RTCTL_PMEIE 0x0008
591#define PCI_EXP_RTCTL_CRSSVE 0x0010
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]592#define PCI_EXP_RTCAP 30
593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
594#define PCI_EXP_RTSTA 32
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]595#define PCI_EXP_RTSTA_PME 0x00010000
596#define PCI_EXP_RTSTA_PENDING 0x00020000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]597#define PCI_EXP_DEVCAP2 36
598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]599#define PCI_EXP_DEVCAP2_ARI 0x00000020
600#define PCI_EXP_DEVCAP2_LTR 0x00000800
601#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000
602#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]604#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]605#define PCI_EXP_DEVCTL2 40
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]606#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f
607#define PCI_EXP_DEVCTL2_ARI 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]609#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100
610#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200
611#define PCI_EXP_DEVCTL2_LTR_EN 0x0400
612#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]614#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000
615#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000
616#define PCI_EXP_DEVSTA2 42
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]617#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]619#define PCI_EXP_LNKCAP2 44
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]620#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002
621#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004
622#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]624#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]625#define PCI_EXP_LNKCTL2 48
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]626#define PCI_EXP_LNKSTA2 50
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]627#define PCI_EXP_SLTCAP2 52
628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]629#define PCI_EXP_SLTCTL2 56
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]630#define PCI_EXP_SLTSTA2 58
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]631#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
632#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
634#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
635#define PCI_EXT_CAP_ID_ERR 0x01
636#define PCI_EXT_CAP_ID_VC 0x02
637#define PCI_EXT_CAP_ID_DSN 0x03
638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
639#define PCI_EXT_CAP_ID_PWR 0x04
640#define PCI_EXT_CAP_ID_RCLD 0x05
641#define PCI_EXT_CAP_ID_RCILC 0x06
642#define PCI_EXT_CAP_ID_RCEC 0x07
643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
644#define PCI_EXT_CAP_ID_MFVC 0x08
645#define PCI_EXT_CAP_ID_VC9 0x09
646#define PCI_EXT_CAP_ID_RCRB 0x0A
647#define PCI_EXT_CAP_ID_VNDR 0x0B
648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
649#define PCI_EXT_CAP_ID_CAC 0x0C
650#define PCI_EXT_CAP_ID_ACS 0x0D
651#define PCI_EXT_CAP_ID_ARI 0x0E
652#define PCI_EXT_CAP_ID_ATS 0x0F
653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
654#define PCI_EXT_CAP_ID_SRIOV 0x10
655#define PCI_EXT_CAP_ID_MRIOV 0x11
656#define PCI_EXT_CAP_ID_MCAST 0x12
657#define PCI_EXT_CAP_ID_PRI 0x13
658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
659#define PCI_EXT_CAP_ID_AMD_XXX 0x14
660#define PCI_EXT_CAP_ID_REBAR 0x15
661#define PCI_EXT_CAP_ID_DPA 0x16
662#define PCI_EXT_CAP_ID_TPH 0x17
663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
664#define PCI_EXT_CAP_ID_LTR 0x18
665#define PCI_EXT_CAP_ID_SECPCI 0x19
666#define PCI_EXT_CAP_ID_PMUX 0x1A
667#define PCI_EXT_CAP_ID_PASID 0x1B
668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
669#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
670#define PCI_EXT_CAP_DSN_SIZEOF 12
671#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
672#define PCI_ERR_UNCOR_STATUS 4
673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
674#define PCI_ERR_UNC_TRAIN 0x00000001
675#define PCI_ERR_UNC_DLP 0x00000010
676#define PCI_ERR_UNC_SURPDN 0x00000020
677#define PCI_ERR_UNC_POISON_TLP 0x00001000
678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
679#define PCI_ERR_UNC_FCP 0x00002000
680#define PCI_ERR_UNC_COMP_TIME 0x00004000
681#define PCI_ERR_UNC_COMP_ABORT 0x00008000
682#define PCI_ERR_UNC_UNX_COMP 0x00010000
683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
684#define PCI_ERR_UNC_RX_OVER 0x00020000
685#define PCI_ERR_UNC_MALF_TLP 0x00040000
686#define PCI_ERR_UNC_ECRC 0x00080000
687#define PCI_ERR_UNC_UNSUP 0x00100000
688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
689#define PCI_ERR_UNC_ACSV 0x00200000
690#define PCI_ERR_UNC_INTN 0x00400000
691#define PCI_ERR_UNC_MCBTLP 0x00800000
692#define PCI_ERR_UNC_ATOMEG 0x01000000
693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
694#define PCI_ERR_UNC_TLPPRE 0x02000000
695#define PCI_ERR_UNCOR_MASK 8
696#define PCI_ERR_UNCOR_SEVER 12
697#define PCI_ERR_COR_STATUS 16
698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
699#define PCI_ERR_COR_RCVR 0x00000001
700#define PCI_ERR_COR_BAD_TLP 0x00000040
701#define PCI_ERR_COR_BAD_DLLP 0x00000080
702#define PCI_ERR_COR_REP_ROLL 0x00000100
703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
704#define PCI_ERR_COR_REP_TIMER 0x00001000
705#define PCI_ERR_COR_ADV_NFAT 0x00002000
706#define PCI_ERR_COR_INTERNAL 0x00004000
707#define PCI_ERR_COR_LOG_OVER 0x00008000
708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
709#define PCI_ERR_COR_MASK 20
710#define PCI_ERR_CAP 24
711#define PCI_ERR_CAP_FEP(x) ((x) & 31)
712#define PCI_ERR_CAP_ECRC_GENC 0x00000020
713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
714#define PCI_ERR_CAP_ECRC_GENE 0x00000040
715#define PCI_ERR_CAP_ECRC_CHKC 0x00000080
716#define PCI_ERR_CAP_ECRC_CHKE 0x00000100
717#define PCI_ERR_HEADER_LOG 28
718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
719#define PCI_ERR_ROOT_COMMAND 44
720#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
721#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
722#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
724#define PCI_ERR_ROOT_STATUS 48
725#define PCI_ERR_ROOT_COR_RCV 0x00000001
726#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
727#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
729#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
730#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010
731#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020
732#define PCI_ERR_ROOT_FATAL_RCV 0x00000040
733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
734#define PCI_ERR_ROOT_ERR_SRC 52
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]735#define PCI_VC_PORT_CAP1 4
736#define PCI_VC_CAP1_EVCC 0x00000007
737#define PCI_VC_CAP1_LPEVCC 0x00000070
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]739#define PCI_VC_CAP1_ARB_SIZE 0x00000c00
740#define PCI_VC_PORT_CAP2 8
741#define PCI_VC_CAP2_32_PHASE 0x00000002
742#define PCI_VC_CAP2_64_PHASE 0x00000004
743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
744#define PCI_VC_CAP2_128_PHASE 0x00000008
745#define PCI_VC_CAP2_ARB_OFF 0xff000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]746#define PCI_VC_PORT_CTRL 12
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]747#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
749#define PCI_VC_PORT_STATUS 14
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]750#define PCI_VC_PORT_STATUS_TABLE 0x00000001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]751#define PCI_VC_RES_CAP 16
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]752#define PCI_VC_RES_CAP_32_PHASE 0x00000002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]754#define PCI_VC_RES_CAP_64_PHASE 0x00000004
755#define PCI_VC_RES_CAP_128_PHASE 0x00000008
756#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010
757#define PCI_VC_RES_CAP_256_PHASE 0x00000020
758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
759#define PCI_VC_RES_CAP_ARB_OFF 0xff000000
760#define PCI_VC_RES_CTRL 20
761#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000
762#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000
763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
764#define PCI_VC_RES_CTRL_ID 0x07000000
765#define PCI_VC_RES_CTRL_ENABLE 0x80000000
766#define PCI_VC_RES_STATUS 26
767#define PCI_VC_RES_STATUS_TABLE 0x00000001
768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
769#define PCI_VC_RES_STATUS_NEGO 0x00000002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]770#define PCI_CAP_VC_BASE_SIZEOF 0x10
771#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C
772#define PCI_PWR_DSR 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]774#define PCI_PWR_DATA 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]775#define PCI_PWR_DATA_BASE(x) ((x) & 0xff)
776#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3)
777#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]779#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]780#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7)
781#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7)
782#define PCI_PWR_CAP 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]784#define PCI_PWR_CAP_BUDGET(x) ((x) & 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]785#define PCI_EXT_CAP_PWR_SIZEOF 16
786#define PCI_VNDR_HEADER 4
787#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]789#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]790#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff)
791#define HT_3BIT_CAP_MASK 0xE0
792#define HT_CAPTYPE_SLAVE 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]794#define HT_CAPTYPE_HOST 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]795#define HT_5BIT_CAP_MASK 0xF8
796#define HT_CAPTYPE_IRQ 0x80
797#define HT_CAPTYPE_REMAPPING_40 0xA0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]799#define HT_CAPTYPE_REMAPPING_64 0xA2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]800#define HT_CAPTYPE_UNITID_CLUMP 0x90
801#define HT_CAPTYPE_EXTCONF 0x98
802#define HT_CAPTYPE_MSI_MAPPING 0xA8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]804#define HT_MSI_FLAGS 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]805#define HT_MSI_FLAGS_ENABLE 0x1
806#define HT_MSI_FLAGS_FIXED 0x2
807#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]809#define HT_MSI_ADDR_LO 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]810#define HT_MSI_ADDR_LO_MASK 0xFFF00000
811#define HT_MSI_ADDR_HI 0x08
812#define HT_CAPTYPE_DIRECT_ROUTE 0xB0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]814#define HT_CAPTYPE_VCSET 0xB8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]815#define HT_CAPTYPE_ERROR_RETRY 0xC0
816#define HT_CAPTYPE_GEN3 0xD0
817#define HT_CAPTYPE_PM 0xE0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]819#define HT_CAP_SIZEOF_LONG 28
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]820#define HT_CAP_SIZEOF_SHORT 24
821#define PCI_ARI_CAP 0x04
822#define PCI_ARI_CAP_MFVC 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]824#define PCI_ARI_CAP_ACS 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]825#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff)
826#define PCI_ARI_CTRL 0x06
827#define PCI_ARI_CTRL_MFVC 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]829#define PCI_ARI_CTRL_ACS 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]830#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7)
831#define PCI_EXT_CAP_ARI_SIZEOF 8
832#define PCI_ATS_CAP 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]834#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]835#define PCI_ATS_MAX_QDEP 32
836#define PCI_ATS_CTRL 0x06
837#define PCI_ATS_CTRL_ENABLE 0x8000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]839#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]840#define PCI_ATS_MIN_STU 12
841#define PCI_EXT_CAP_ATS_SIZEOF 8
842#define PCI_PRI_CTRL 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]844#define PCI_PRI_CTRL_ENABLE 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]845#define PCI_PRI_CTRL_RESET 0x02
846#define PCI_PRI_STATUS 0x06
847#define PCI_PRI_STATUS_RF 0x001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]849#define PCI_PRI_STATUS_UPRGI 0x002
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]850#define PCI_PRI_STATUS_STOPPED 0x100
851#define PCI_PRI_MAX_REQ 0x08
852#define PCI_PRI_ALLOC_REQ 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]854#define PCI_EXT_CAP_PRI_SIZEOF 16
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]855#define PCI_PASID_CAP 0x04
856#define PCI_PASID_CAP_EXEC 0x02
857#define PCI_PASID_CAP_PRIV 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]859#define PCI_PASID_CTRL 0x06
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]860#define PCI_PASID_CTRL_ENABLE 0x01
861#define PCI_PASID_CTRL_EXEC 0x02
862#define PCI_PASID_CTRL_PRIV 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]864#define PCI_EXT_CAP_PASID_SIZEOF 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]865#define PCI_SRIOV_CAP 0x04
866#define PCI_SRIOV_CAP_VFM 0x01
867#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]869#define PCI_SRIOV_CTRL 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]870#define PCI_SRIOV_CTRL_VFE 0x01
871#define PCI_SRIOV_CTRL_VFM 0x02
872#define PCI_SRIOV_CTRL_INTR 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]874#define PCI_SRIOV_CTRL_MSE 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]875#define PCI_SRIOV_CTRL_ARI 0x10
876#define PCI_SRIOV_STATUS 0x0a
877#define PCI_SRIOV_STATUS_VFM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]879#define PCI_SRIOV_INITIAL_VF 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]880#define PCI_SRIOV_TOTAL_VF 0x0e
881#define PCI_SRIOV_NUM_VF 0x10
882#define PCI_SRIOV_FUNC_LINK 0x12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]884#define PCI_SRIOV_VF_OFFSET 0x14
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]885#define PCI_SRIOV_VF_STRIDE 0x16
886#define PCI_SRIOV_VF_DID 0x1a
887#define PCI_SRIOV_SUP_PGSIZE 0x1c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]889#define PCI_SRIOV_SYS_PGSIZE 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]890#define PCI_SRIOV_BAR 0x24
891#define PCI_SRIOV_NUM_BARS 6
892#define PCI_SRIOV_VFM 0x3c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]894#define PCI_SRIOV_VFM_BIR(x) ((x) & 7)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]895#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)
896#define PCI_SRIOV_VFM_UA 0x0
897#define PCI_SRIOV_VFM_MI 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]899#define PCI_SRIOV_VFM_MO 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]900#define PCI_SRIOV_VFM_AV 0x3
901#define PCI_EXT_CAP_SRIOV_SIZEOF 64
902#define PCI_LTR_MAX_SNOOP_LAT 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]904#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]905#define PCI_LTR_VALUE_MASK 0x000003ff
906#define PCI_LTR_SCALE_MASK 0x00001c00
907#define PCI_LTR_SCALE_SHIFT 10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]909#define PCI_EXT_CAP_LTR_SIZEOF 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]910#define PCI_ACS_CAP 0x04
911#define PCI_ACS_SV 0x01
912#define PCI_ACS_TB 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]914#define PCI_ACS_RR 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]915#define PCI_ACS_CR 0x08
916#define PCI_ACS_UF 0x10
917#define PCI_ACS_EC 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]919#define PCI_ACS_DT 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]920#define PCI_ACS_EGRESS_BITS 0x05
921#define PCI_ACS_CTRL 0x06
922#define PCI_ACS_EGRESS_CTL_V 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]924#define PCI_VSEC_HDR 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]925#define PCI_VSEC_HDR_LEN_SHIFT 20
926#define PCI_SATA_REGS 4
927#define PCI_SATA_REGS_MASK 0xF
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]929#define PCI_SATA_REGS_INLINE 0xF
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]930#define PCI_SATA_SIZEOF_SHORT 8
931#define PCI_SATA_SIZEOF_LONG 16
932#define PCI_REBAR_CTRL 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]934#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]935#define PCI_REBAR_CTRL_NBAR_SHIFT 5
936#define PCI_DPA_CAP 4
937#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]939#define PCI_DPA_BASE_SIZEOF 16
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]940#define PCI_TPH_CAP 4
941#define PCI_TPH_CAP_LOC_MASK 0x600
942#define PCI_TPH_LOC_NONE 0x000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]944#define PCI_TPH_LOC_CAP 0x200
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]945#define PCI_TPH_LOC_MSIX 0x400
946#define PCI_TPH_CAP_ST_MASK 0x07FF0000
947#define PCI_TPH_CAP_ST_SHIFT 16
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame^]949#define PCI_TPH_BASE_SIZEOF 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]950#endif