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review.blissroms.org / platform_bionic / 3d5a42408ca24f86b8b81697b20012736cb48c2b / . / libc / kernel / uapi / drm / i810_drm.h
blob: 946833d1d121db5902e7ef5515295faae72d13e9 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _I810_DRM_H_
20#define _I810_DRM_H_
21#ifndef _I810_DEFINES_
22#define _I810_DEFINES_
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define I810_DMA_BUF_ORDER 12
25#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER)
26#define I810_DMA_BUF_NR 256
27#define I810_NR_SAREA_CLIPRECTS 8
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define I810_NR_TEX_REGIONS 64
30#define I810_LOG_MIN_TEX_REGION_SIZE 16
31#endif
32#define I810_UPLOAD_TEX0IMAGE 0x1
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define I810_UPLOAD_TEX1IMAGE 0x2
35#define I810_UPLOAD_CTX 0x4
36#define I810_UPLOAD_BUFFERS 0x8
37#define I810_UPLOAD_TEX0 0x10
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define I810_UPLOAD_TEX1 0x20
40#define I810_UPLOAD_CLIPRECTS 0x40
41#define I810_DESTREG_DI0 0
42#define I810_DESTREG_DI1 1
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define I810_DESTREG_DV0 2
45#define I810_DESTREG_DV1 3
46#define I810_DESTREG_DR0 4
47#define I810_DESTREG_DR1 5
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define I810_DESTREG_DR2 6
50#define I810_DESTREG_DR3 7
51#define I810_DESTREG_DR4 8
52#define I810_DEST_SETUP_SIZE 10
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define I810_CTXREG_CF0 0
55#define I810_CTXREG_CF1 1
56#define I810_CTXREG_ST0 2
57#define I810_CTXREG_ST1 3
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define I810_CTXREG_VF 4
60#define I810_CTXREG_MT 5
61#define I810_CTXREG_MC0 6
62#define I810_CTXREG_MC1 7
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64#define I810_CTXREG_MC2 8
65#define I810_CTXREG_MA0 9
66#define I810_CTXREG_MA1 10
67#define I810_CTXREG_MA2 11
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69#define I810_CTXREG_SDM 12
70#define I810_CTXREG_FOG 13
71#define I810_CTXREG_B1 14
72#define I810_CTXREG_B2 15
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74#define I810_CTXREG_LCS 16
75#define I810_CTXREG_PV 17
76#define I810_CTXREG_ZA 18
77#define I810_CTXREG_AA 19
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define I810_CTX_SETUP_SIZE 20
80#define I810_TEXREG_MI0 0
81#define I810_TEXREG_MI1 1
82#define I810_TEXREG_MI2 2
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84#define I810_TEXREG_MI3 3
85#define I810_TEXREG_MF 4
86#define I810_TEXREG_MLC 5
87#define I810_TEXREG_MLL 6
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89#define I810_TEXREG_MCS 7
90#define I810_TEX_SETUP_SIZE 8
91#define I810_FRONT 0x1
92#define I810_BACK 0x2
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94#define I810_DEPTH 0x4
95typedef enum _drm_i810_init_func {
96 I810_INIT_DMA = 0x01,
97 I810_CLEANUP_DMA = 0x02,
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99 I810_INIT_DMA_1_4 = 0x03
100} drm_i810_init_func_t;
101typedef struct _drm_i810_init {
102 drm_i810_init_func_t func;
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104 unsigned int mmio_offset;
105 unsigned int buffers_offset;
106 int sarea_priv_offset;
107 unsigned int ring_start;
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109 unsigned int ring_end;
110 unsigned int ring_size;
111 unsigned int front_offset;
112 unsigned int back_offset;
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114 unsigned int depth_offset;
115 unsigned int overlay_offset;
116 unsigned int overlay_physical;
117 unsigned int w;
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119 unsigned int h;
120 unsigned int pitch;
121 unsigned int pitch_bits;
122} drm_i810_init_t;
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124typedef struct _drm_i810_pre12_init {
125 drm_i810_init_func_t func;
126 unsigned int mmio_offset;
127 unsigned int buffers_offset;
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129 int sarea_priv_offset;
130 unsigned int ring_start;
131 unsigned int ring_end;
132 unsigned int ring_size;
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134 unsigned int front_offset;
135 unsigned int back_offset;
136 unsigned int depth_offset;
137 unsigned int w;
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139 unsigned int h;
140 unsigned int pitch;
141 unsigned int pitch_bits;
142} drm_i810_pre12_init_t;
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144typedef struct _drm_i810_tex_region {
145 unsigned char next, prev;
146 unsigned char in_use;
147 int age;
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149} drm_i810_tex_region_t;
150typedef struct _drm_i810_sarea {
151 unsigned int ContextState[I810_CTX_SETUP_SIZE];
152 unsigned int BufferState[I810_DEST_SETUP_SIZE];
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
155 unsigned int dirty;
156 unsigned int nbox;
157 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
159 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
160 int texAge;
161 int last_enqueue;
162 int last_dispatch;
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
164 int last_quiescent;
165 int ctxOwner;
166 int vertex_prim;
167 int pf_enabled;
168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
169 int pf_active;
170 int pf_current_page;
171} drm_i810_sarea_t;
172#define DRM_I810_INIT 0x00
173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
174#define DRM_I810_VERTEX 0x01
175#define DRM_I810_CLEAR 0x02
176#define DRM_I810_FLUSH 0x03
177#define DRM_I810_GETAGE 0x04
178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
179#define DRM_I810_GETBUF 0x05
180#define DRM_I810_SWAP 0x06
181#define DRM_I810_COPY 0x07
182#define DRM_I810_DOCOPY 0x08
183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
184#define DRM_I810_OV0INFO 0x09
185#define DRM_I810_FSTATUS 0x0a
186#define DRM_I810_OV0FLIP 0x0b
187#define DRM_I810_MC 0x0c
188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
189#define DRM_I810_RSTATUS 0x0d
190#define DRM_I810_FLIP 0x0e
191#define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
192#define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
194#define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
195#define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH)
196#define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE)
197#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
199#define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP)
200#define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
201#define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY)
202#define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
204#define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
205#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
206#define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
207#define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
209#define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
210typedef struct _drm_i810_clear {
211 int clear_color;
212 int clear_depth;
213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
214 int flags;
215} drm_i810_clear_t;
216typedef struct _drm_i810_vertex {
217 int idx;
218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
219 int used;
220 int discard;
221} drm_i810_vertex_t;
222typedef struct _drm_i810_copy_t {
223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
224 int idx;
225 int used;
226 void *address;
227} drm_i810_copy_t;
228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
229#define PR_TRIANGLES (0x0<<18)
230#define PR_TRISTRIP_0 (0x1<<18)
231#define PR_TRISTRIP_1 (0x2<<18)
232#define PR_TRIFAN (0x3<<18)
233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
234#define PR_POLYGON (0x4<<18)
235#define PR_LINES (0x5<<18)
236#define PR_LINESTRIP (0x6<<18)
237#define PR_RECTS (0x7<<18)
238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
239#define PR_MASK (0x7<<18)
240typedef struct drm_i810_dma {
241 void *virtual;
242 int request_idx;
243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
244 int request_size;
245 int granted;
246} drm_i810_dma_t;
247typedef struct _drm_i810_overlay_t {
248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
249 unsigned int offset;
250 unsigned int physical;
251} drm_i810_overlay_t;
252typedef struct _drm_i810_mc {
253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
254 int idx;
255 int used;
256 int num_blocks;
257 int *length;
258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
259 unsigned int last_render;
260} drm_i810_mc_t;
261#endif