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review.blissroms.org / platform_bionic / 40596aa0054bcfa76148f55321bf4b979e2242be / . / libc / kernel / uapi / drm / tegra_drm.h
blob: 0bace280a3ed1c82a858abc27c56aaf6516a6509 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_TEGRA_DRM_H_
20#define _UAPI_TEGRA_DRM_H_
21#include <drm/drm.h>
22struct drm_tegra_gem_create {
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24 __u64 size;
25 __u32 flags;
26 __u32 handle;
27};
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29struct drm_tegra_gem_mmap {
30 __u32 handle;
31 __u32 offset;
32};
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34struct drm_tegra_syncpt_read {
35 __u32 id;
36 __u32 value;
37};
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39struct drm_tegra_syncpt_incr {
40 __u32 id;
41 __u32 pad;
42};
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44struct drm_tegra_syncpt_wait {
45 __u32 id;
46 __u32 thresh;
47 __u32 timeout;
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49 __u32 value;
50};
51#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
52struct drm_tegra_open_channel {
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54 __u32 client;
55 __u32 pad;
56 __u64 context;
57};
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59struct drm_tegra_close_channel {
60 __u64 context;
61};
62struct drm_tegra_get_syncpt {
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64 __u64 context;
65 __u32 index;
66 __u32 id;
67};
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69struct drm_tegra_syncpt {
70 __u32 id;
71 __u32 incrs;
72};
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74struct drm_tegra_cmdbuf {
75 __u32 handle;
76 __u32 offset;
77 __u32 words;
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79 __u32 pad;
80};
81struct drm_tegra_reloc {
82 struct {
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84 __u32 handle;
85 __u32 offset;
86 } cmdbuf;
87 struct {
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89 __u32 handle;
90 __u32 offset;
91 } target;
92 __u32 shift;
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94 __u32 pad;
95};
96struct drm_tegra_waitchk {
97 __u32 handle;
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99 __u32 offset;
100 __u32 syncpt;
101 __u32 thresh;
102};
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104struct drm_tegra_submit {
105 __u64 context;
106 __u32 num_syncpts;
107 __u32 num_cmdbufs;
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109 __u32 num_relocs;
110 __u32 num_waitchks;
111 __u32 waitchk_mask;
112 __u32 timeout;
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114 __u32 pad;
115 __u64 syncpts;
116 __u64 cmdbufs;
117 __u64 relocs;
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119 __u64 waitchks;
120 __u32 fence;
121 __u32 reserved[5];
122};
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124#define DRM_TEGRA_GEM_CREATE 0x00
125#define DRM_TEGRA_GEM_MMAP 0x01
126#define DRM_TEGRA_SYNCPT_READ 0x02
127#define DRM_TEGRA_SYNCPT_INCR 0x03
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129#define DRM_TEGRA_SYNCPT_WAIT 0x04
130#define DRM_TEGRA_OPEN_CHANNEL 0x05
131#define DRM_TEGRA_CLOSE_CHANNEL 0x06
132#define DRM_TEGRA_GET_SYNCPT 0x07
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134#define DRM_TEGRA_SUBMIT 0x08
135#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
136#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
137#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
140#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
141#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
142#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
145#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
146#endif