Gitiles
Code Review Sign In
review.blissroms.org / platform_bionic / 5e52226f02b7199fa7870a6195b3e5c0efb1c8d3 / . / libc / kernel / uapi / drm / drm.h
blob: 32a76a7aaef4288a6d0c932a7f836d9ce772fe87 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_H_
20#define _DRM_H_
21#ifdef __linux__
22#include <linux/types.h>
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#include <asm/ioctl.h>
25typedef unsigned int drm_handle_t;
26#else
27#include <sys/ioccom.h>
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#include <sys/types.h>
30typedef int8_t __s8;
31typedef uint8_t __u8;
32typedef int16_t __s16;
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34typedef uint16_t __u16;
35typedef int32_t __s32;
36typedef uint32_t __u32;
37typedef int64_t __s64;
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39typedef uint64_t __u64;
40typedef unsigned long drm_handle_t;
41#endif
42#define DRM_NAME "drm"
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define DRM_MIN_ORDER 5
45#define DRM_MAX_ORDER 22
46#define DRM_RAM_PERCENT 10
47#define _DRM_LOCK_HELD 0x80000000U
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define _DRM_LOCK_CONT 0x40000000U
50#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
51#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
52#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54typedef unsigned int drm_context_t;
55typedef unsigned int drm_drawable_t;
56typedef unsigned int drm_magic_t;
57struct drm_clip_rect {
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59 unsigned short x1;
60 unsigned short y1;
61 unsigned short x2;
62 unsigned short y2;
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64};
65struct drm_drawable_info {
66 unsigned int num_rects;
67 struct drm_clip_rect *rects;
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69};
70struct drm_tex_region {
71 unsigned char next;
72 unsigned char prev;
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74 unsigned char in_use;
75 unsigned char padding;
76 unsigned int age;
77};
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79struct drm_hw_lock {
80 __volatile__ unsigned int lock;
81 char padding[60];
82};
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84struct drm_version {
85 int version_major;
86 int version_minor;
87 int version_patchlevel;
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89 size_t name_len;
90 char __user *name;
91 size_t date_len;
92 char __user *date;
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94 size_t desc_len;
95 char __user *desc;
96};
97struct drm_unique {
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99 size_t unique_len;
100 char __user *unique;
101};
102struct drm_list {
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104 int count;
105 struct drm_version __user *version;
106};
107struct drm_block {
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109 int unused;
110};
111struct drm_control {
112 enum {
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114 DRM_ADD_COMMAND,
115 DRM_RM_COMMAND,
116 DRM_INST_HANDLER,
117 DRM_UNINST_HANDLER
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119 } func;
120 int irq;
121};
122enum drm_map_type {
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124 _DRM_FRAME_BUFFER = 0,
125 _DRM_REGISTERS = 1,
126 _DRM_SHM = 2,
127 _DRM_AGP = 3,
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129 _DRM_SCATTER_GATHER = 4,
130 _DRM_CONSISTENT = 5,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]131};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]132enum drm_map_flags {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134 _DRM_RESTRICTED = 0x01,
135 _DRM_READ_ONLY = 0x02,
136 _DRM_LOCKED = 0x04,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]137 _DRM_KERNEL = 0x08,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139 _DRM_WRITE_COMBINING = 0x10,
140 _DRM_CONTAINS_LOCK = 0x20,
141 _DRM_REMOVABLE = 0x40,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]142 _DRM_DRIVER = 0x80
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144};
145struct drm_ctx_priv_map {
146 unsigned int ctx_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]147 void *handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149};
150struct drm_map {
151 unsigned long offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]152 unsigned long size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154 enum drm_map_type type;
155 enum drm_map_flags flags;
156 void *handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]157 int mtrr;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]159};
160struct drm_client {
161 int idx;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]162 int auth;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164 unsigned long pid;
165 unsigned long uid;
166 unsigned long magic;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]167 unsigned long iocs;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169};
170enum drm_stat_type {
171 _DRM_STAT_LOCK,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]172 _DRM_STAT_OPENS,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174 _DRM_STAT_CLOSES,
175 _DRM_STAT_IOCTLS,
176 _DRM_STAT_LOCKS,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]177 _DRM_STAT_UNLOCKS,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179 _DRM_STAT_VALUE,
180 _DRM_STAT_BYTE,
181 _DRM_STAT_COUNT,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]182 _DRM_STAT_IRQ,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184 _DRM_STAT_PRIMARY,
185 _DRM_STAT_SECONDARY,
186 _DRM_STAT_DMA,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]187 _DRM_STAT_SPECIAL,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189 _DRM_STAT_MISSED
190};
191struct drm_stats {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]192 unsigned long count;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194 struct {
195 unsigned long value;
196 enum drm_stat_type type;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]197 } data[15];
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]199};
200enum drm_lock_flags {
201 _DRM_LOCK_READY = 0x01,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]202 _DRM_LOCK_QUIESCENT = 0x02,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204 _DRM_LOCK_FLUSH = 0x04,
205 _DRM_LOCK_FLUSH_ALL = 0x08,
206 _DRM_HALT_ALL_QUEUES = 0x10,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]207 _DRM_HALT_CUR_QUEUES = 0x20
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]209};
210struct drm_lock {
211 int context;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]212 enum drm_lock_flags flags;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214};
215enum drm_dma_flags {
216 _DRM_DMA_BLOCK = 0x01,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]217 _DRM_DMA_WHILE_LOCKED = 0x02,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219 _DRM_DMA_PRIORITY = 0x04,
220 _DRM_DMA_WAIT = 0x10,
221 _DRM_DMA_SMALLER_OK = 0x20,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]222 _DRM_DMA_LARGER_OK = 0x40
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224};
225struct drm_buf_desc {
226 int count;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]227 int size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]229 int low_mark;
230 int high_mark;
231 enum {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]232 _DRM_PAGE_ALIGN = 0x01,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]234 _DRM_AGP_BUFFER = 0x02,
235 _DRM_SG_BUFFER = 0x04,
236 _DRM_FB_BUFFER = 0x08,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]237 _DRM_PCI_BUFFER_RO = 0x10
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]239 } flags;
240 unsigned long agp_start;
241};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]242struct drm_buf_info {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]244 int count;
245 struct drm_buf_desc __user *list;
246};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]247struct drm_buf_free {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]249 int count;
250 int __user *list;
251};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]252struct drm_buf_pub {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]254 int idx;
255 int total;
256 int used;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]257 void __user *address;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]259};
260struct drm_buf_map {
261 int count;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]262 void __user *virtual;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]264 struct drm_buf_pub __user *list;
265};
266struct drm_dma {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]267 int context;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]269 int send_count;
270 int __user *send_indices;
271 int __user *send_sizes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]272 enum drm_dma_flags flags;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]274 int request_count;
275 int request_size;
276 int __user *request_indices;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]277 int __user *request_sizes;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]279 int granted_count;
280};
281enum drm_ctx_flags {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]282 _DRM_CONTEXT_PRESERVED = 0x01,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]284 _DRM_CONTEXT_2DONLY = 0x02
285};
286struct drm_ctx {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]287 drm_context_t handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]289 enum drm_ctx_flags flags;
290};
291struct drm_ctx_res {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]292 int count;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]294 struct drm_ctx __user *contexts;
295};
296struct drm_draw {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]297 drm_drawable_t handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]299};
300typedef enum {
301 DRM_DRAWABLE_CLIPRECTS,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]302} drm_drawable_info_type_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]304struct drm_update_draw {
305 drm_drawable_t handle;
306 unsigned int type;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]307 unsigned int num;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]309 unsigned long long data;
310};
311struct drm_auth {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]312 drm_magic_t magic;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]314};
315struct drm_irq_busid {
316 int irq;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]317 int busnum;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]319 int devnum;
320 int funcnum;
321};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]322enum drm_vblank_seq_type {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]324 _DRM_VBLANK_ABSOLUTE = 0x0,
325 _DRM_VBLANK_RELATIVE = 0x1,
326 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]327 _DRM_VBLANK_EVENT = 0x4000000,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]329 _DRM_VBLANK_FLIP = 0x8000000,
330 _DRM_VBLANK_NEXTONMISS = 0x10000000,
331 _DRM_VBLANK_SECONDARY = 0x20000000,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]332 _DRM_VBLANK_SIGNAL = 0x40000000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]334};
335#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
336#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]337#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]339struct drm_wait_vblank_request {
340 enum drm_vblank_seq_type type;
341 unsigned int sequence;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]342 unsigned long signal;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]344};
345struct drm_wait_vblank_reply {
346 enum drm_vblank_seq_type type;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]347 unsigned int sequence;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]349 long tval_sec;
350 long tval_usec;
351};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]352union drm_wait_vblank {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]354 struct drm_wait_vblank_request request;
355 struct drm_wait_vblank_reply reply;
356};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]357#define _DRM_PRE_MODESET 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]359#define _DRM_POST_MODESET 2
360struct drm_modeset_ctl {
361 __u32 crtc;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]362 __u32 cmd;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]364};
365struct drm_agp_mode {
366 unsigned long mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]367};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]369struct drm_agp_buffer {
370 unsigned long size;
371 unsigned long handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]372 unsigned long type;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]374 unsigned long physical;
375};
376struct drm_agp_binding {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]377 unsigned long handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]379 unsigned long offset;
380};
381struct drm_agp_info {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]382 int agp_version_major;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]384 int agp_version_minor;
385 unsigned long mode;
386 unsigned long aperture_base;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]387 unsigned long aperture_size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]389 unsigned long memory_allowed;
390 unsigned long memory_used;
391 unsigned short id_vendor;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]392 unsigned short id_device;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]394};
395struct drm_scatter_gather {
396 unsigned long size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]397 unsigned long handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]399};
400struct drm_set_version {
401 int drm_di_major;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]402 int drm_di_minor;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]404 int drm_dd_major;
405 int drm_dd_minor;
406};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]407struct drm_gem_close {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]409 __u32 handle;
410 __u32 pad;
411};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]412struct drm_gem_flink {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]414 __u32 handle;
415 __u32 name;
416};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]417struct drm_gem_open {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]419 __u32 name;
420 __u32 handle;
421 __u64 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]422};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
424#define DRM_CAP_DUMB_BUFFER 0x1
425#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
426#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
427#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
429#define DRM_CAP_PRIME 0x5
430#define DRM_PRIME_CAP_IMPORT 0x1
431#define DRM_PRIME_CAP_EXPORT 0x2
432#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
434#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
435#define DRM_CAP_CURSOR_WIDTH 0x8
436#define DRM_CAP_CURSOR_HEIGHT 0x9
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]437struct drm_get_cap {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]439 __u64 capability;
440 __u64 value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]441};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]442#define DRM_CLIENT_CAP_STEREO_3D 1
443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]444#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]445struct drm_set_client_cap {
446 __u64 capability;
447 __u64 value;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]449};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]450#define DRM_CLOEXEC O_CLOEXEC
451struct drm_prime_handle {
452 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]454 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]455 __s32 fd;
456};
457#include <drm/drm_mode.h>
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]459#define DRM_IOCTL_BASE 'd'
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]460#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
461#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
462#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]464#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]465#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
466#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
467#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]469#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]470#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
471#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
472#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]474#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]475#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
476#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
477#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]479#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]480#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]481#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]482#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]484#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]485#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
486#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
487#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]489#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]490#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
491#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
492#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]494#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]495#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
496#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
497#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]499#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]500#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
501#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
502#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]504#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]505#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
506#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
507#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]509#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]510#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
511#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
512#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]514#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]515#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
516#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
517#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]519#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]520#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
521#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
522#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]524#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]525#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
526#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
527#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]529#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]530#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
531#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
532#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]534#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]535#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
536#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
537#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]539#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]540#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
541#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
542#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]544#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]545#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
546#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
547#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]549#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]550#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
551#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
552#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]554#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]555#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
556#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
557#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]559#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]560#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
561#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
562#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]564#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]565#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
566#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
567#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]569#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]570#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]571#define DRM_COMMAND_BASE 0x40
572#define DRM_COMMAND_END 0xA0
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]574struct drm_event {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]575 __u32 type;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]576 __u32 length;
577};
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]579#define DRM_EVENT_VBLANK 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]580#define DRM_EVENT_FLIP_COMPLETE 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]581struct drm_event_vblank {
582 struct drm_event base;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]584 __u64 user_data;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]585 __u32 tv_sec;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]586 __u32 tv_usec;
587 __u32 sequence;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]589 __u32 reserved;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]590};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]591typedef struct drm_clip_rect drm_clip_rect_t;
592typedef struct drm_drawable_info drm_drawable_info_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]594typedef struct drm_tex_region drm_tex_region_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]595typedef struct drm_hw_lock drm_hw_lock_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]596typedef struct drm_version drm_version_t;
597typedef struct drm_unique drm_unique_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]599typedef struct drm_list drm_list_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]600typedef struct drm_block drm_block_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]601typedef struct drm_control drm_control_t;
602typedef enum drm_map_type drm_map_type_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]604typedef enum drm_map_flags drm_map_flags_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]605typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]606typedef struct drm_map drm_map_t;
607typedef struct drm_client drm_client_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]609typedef enum drm_stat_type drm_stat_type_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]610typedef struct drm_stats drm_stats_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]611typedef enum drm_lock_flags drm_lock_flags_t;
612typedef struct drm_lock drm_lock_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]614typedef enum drm_dma_flags drm_dma_flags_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]615typedef struct drm_buf_desc drm_buf_desc_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]616typedef struct drm_buf_info drm_buf_info_t;
617typedef struct drm_buf_free drm_buf_free_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]619typedef struct drm_buf_pub drm_buf_pub_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]620typedef struct drm_buf_map drm_buf_map_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]621typedef struct drm_dma drm_dma_t;
622typedef union drm_wait_vblank drm_wait_vblank_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]624typedef struct drm_agp_mode drm_agp_mode_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]625typedef enum drm_ctx_flags drm_ctx_flags_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]626typedef struct drm_ctx drm_ctx_t;
627typedef struct drm_ctx_res drm_ctx_res_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]629typedef struct drm_draw drm_draw_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]630typedef struct drm_update_draw drm_update_draw_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]631typedef struct drm_auth drm_auth_t;
632typedef struct drm_irq_busid drm_irq_busid_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]634typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]635typedef struct drm_agp_buffer drm_agp_buffer_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]636typedef struct drm_agp_binding drm_agp_binding_t;
637typedef struct drm_agp_info drm_agp_info_t;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]639typedef struct drm_scatter_gather drm_scatter_gather_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]640typedef struct drm_set_version drm_set_version_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]641#endif